WO2009017070A1 - 積層型半導体装置 - Google Patents

積層型半導体装置 Download PDF

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Publication number
WO2009017070A1
WO2009017070A1 PCT/JP2008/063442 JP2008063442W WO2009017070A1 WO 2009017070 A1 WO2009017070 A1 WO 2009017070A1 JP 2008063442 W JP2008063442 W JP 2008063442W WO 2009017070 A1 WO2009017070 A1 WO 2009017070A1
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WO
WIPO (PCT)
Prior art keywords
circuit region
semiconductor device
heat
multilayer semiconductor
improved
Prior art date
Application number
PCT/JP2008/063442
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English (en)
French (fr)
Inventor
Isao Sugaya
Kazuya Okamoto
Original Assignee
Nikon Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corporation filed Critical Nikon Corporation
Priority to JP2009525379A priority Critical patent/JP5600939B2/ja
Priority to CN2008801088879A priority patent/CN101836294B/zh
Publication of WO2009017070A1 publication Critical patent/WO2009017070A1/ja
Priority to US12/694,008 priority patent/US8299848B2/en
Priority to US13/528,220 priority patent/US8436680B2/en

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
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  • Materials Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　熱分散を向上させ、さらに放熱効率を向上させることができる積層型半導体装置を提供する。複数の半導体チップ（２０－１、２０－２）が積層され、該半導体チップの各々が少なくとも一つの回路領域を有する積層型半導体装置（１００）であって、回路領域の駆動に伴って回路領域から発せられた熱が分散するように、回路領域が配される。上記積層型半導体装置（１００）において、回路領域から発せられた熱を放熱する放熱部（５０）をさらに備え、複数の回路領域のうち単位面積当たりの発熱量が多いものほど放熱部との間における熱抵抗がより小さくなるように、回路領域が配置されてもよい。
PCT/JP2008/063442 2007-07-27 2008-07-25 積層型半導体装置 WO2009017070A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009525379A JP5600939B2 (ja) 2007-07-27 2008-07-25 積層型半導体装置
CN2008801088879A CN101836294B (zh) 2007-07-27 2008-07-25 层叠型半导体器件
US12/694,008 US8299848B2 (en) 2007-07-27 2010-01-26 Multi-layered semiconductor apparatus
US13/528,220 US8436680B2 (en) 2007-07-27 2012-06-20 Multi-layered semiconductor apparatus

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-196767 2007-07-27
JP2007196767 2007-07-27
JP2007325604 2007-12-18
JP2007-325604 2007-12-18

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/694,008 Continuation US8299848B2 (en) 2007-07-27 2010-01-26 Multi-layered semiconductor apparatus

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WO2009017070A1 true WO2009017070A1 (ja) 2009-02-05

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PCT/JP2008/063442 WO2009017070A1 (ja) 2007-07-27 2008-07-25 積層型半導体装置

Country Status (6)

Country Link
US (3) US8299848B2 (ja)
JP (2) JP5600939B2 (ja)
KR (1) KR101477323B1 (ja)
CN (3) CN103219326B (ja)
TW (1) TWI470762B (ja)
WO (1) WO2009017070A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014115791A (ja) * 2012-12-07 2014-06-26 Canon Inc 情報処理装置、その制御方法、及びプログラム
JP2015527734A (ja) * 2012-07-12 2015-09-17 マイクロン テクノロジー， インク． 断熱材を含む半導体デバイスパッケージおよび、係る半導体パッケージの作製および使用の方法
JP2021501435A (ja) * 2017-10-26 2021-01-14 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ ３ｄ積層メモリにおけるスウィズリング

Families Citing this family (8)

* Cited by examiner, † Cited by third party
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US20130286595A1 (en) * 2012-04-27 2013-10-31 Qualcomm Incorporated Thermal management floorplan for a multi-tier stacked ic package
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