WO2009011052A1 - メモリリフレッシュ装置およびメモリリフレッシュ方法 - Google Patents

メモリリフレッシュ装置およびメモリリフレッシュ方法 Download PDF

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Publication number
WO2009011052A1
WO2009011052A1 PCT/JP2007/064199 JP2007064199W WO2009011052A1 WO 2009011052 A1 WO2009011052 A1 WO 2009011052A1 JP 2007064199 W JP2007064199 W JP 2007064199W WO 2009011052 A1 WO2009011052 A1 WO 2009011052A1
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WO
WIPO (PCT)
Prior art keywords
error
memory
memory refresh
ordinary
patrol
Prior art date
Application number
PCT/JP2007/064199
Other languages
English (en)
French (fr)
Inventor
Masanori Higeta
Kenji Suzuki
Takatsugu Sasaki
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009523490A priority Critical patent/JP5012898B2/ja
Priority to CN2007800538099A priority patent/CN101796497B/zh
Priority to PCT/JP2007/064199 priority patent/WO2009011052A1/ja
Priority to KR1020107001001A priority patent/KR101043013B1/ko
Priority to EP07790953.9A priority patent/EP2169558B1/en
Publication of WO2009011052A1 publication Critical patent/WO2009011052A1/ja
Priority to US12/683,059 priority patent/US8549366B2/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

　メモリ（１１）のパトロールを行なう通常パトロール動作を制御する通常パトロール制御部（２４）と、通常パトロール動作においてメモリ（１１）のエラーを検出した場合に、メモリ（１１）におけるエラー発生箇所に対してパトロールを行なう追加パトロール動作を制御する追加パトロール制御部（２５）と、追加パトロール動作においてエラーを検出した場合に、エラー発生箇所におけるエラーに関する情報をエラー頻度として計測する計測部（１５）と、計測部（１５）によって計測されたエラー頻度に応じて、リフレッシュ周期を調整するリフレッシュ周期調整部（２６）とをそなえることにより、メモリにおけるエラーの発生状態に合わせたリフレッシュ周期の最適化を効率よく行なう。
PCT/JP2007/064199 2007-07-18 2007-07-18 メモリリフレッシュ装置およびメモリリフレッシュ方法 WO2009011052A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009523490A JP5012898B2 (ja) 2007-07-18 2007-07-18 メモリリフレッシュ装置およびメモリリフレッシュ方法
CN2007800538099A CN101796497B (zh) 2007-07-18 2007-07-18 存储器刷新装置和存储器刷新方法
PCT/JP2007/064199 WO2009011052A1 (ja) 2007-07-18 2007-07-18 メモリリフレッシュ装置およびメモリリフレッシュ方法
KR1020107001001A KR101043013B1 (ko) 2007-07-18 2007-07-18 메모리 리프레시 장치 및 메모리 리프레시 방법
EP07790953.9A EP2169558B1 (en) 2007-07-18 2007-07-18 Memory refresh device and memory refresh method
US12/683,059 US8549366B2 (en) 2007-07-18 2010-01-06 Memory refreshing circuit and method for memory refresh

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/064199 WO2009011052A1 (ja) 2007-07-18 2007-07-18 メモリリフレッシュ装置およびメモリリフレッシュ方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/683,059 Continuation US8549366B2 (en) 2007-07-18 2010-01-06 Memory refreshing circuit and method for memory refresh

Publications (1)

Publication Number Publication Date
WO2009011052A1 true WO2009011052A1 (ja) 2009-01-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/064199 WO2009011052A1 (ja) 2007-07-18 2007-07-18 メモリリフレッシュ装置およびメモリリフレッシュ方法

Country Status (6)

Country Link
US (1) US8549366B2 (ja)
EP (1) EP2169558B1 (ja)
JP (1) JP5012898B2 (ja)
KR (1) KR101043013B1 (ja)
CN (1) CN101796497B (ja)
WO (1) WO2009011052A1 (ja)

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JP2014059939A (ja) * 2012-09-19 2014-04-03 Fujitsu Semiconductor Ltd リフレッシュ制御装置およびリフレッシュ制御方法、並びに、半導体装置
JP2014059831A (ja) * 2012-09-19 2014-04-03 Nec Computertechno Ltd メモリリフレッシュ装置、情報処理システム、メモリリフレッシュ方法、および、コンピュータ・プログラム
US8918699B2 (en) 2012-07-31 2014-12-23 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage apparatus
JP2016505184A (ja) * 2013-01-31 2016-02-18 ヒューレット−パッカード デベロップメント カンパニー エル．ピー．Ｈｅｗｌｅｔｔ‐Ｐａｃｋａｒｄ Ｄｅｖｅｌｏｐｍｅｎｔ Ｃｏｍｐａｎｙ， Ｌ．Ｐ． Ｒａｍリフレッシュレート

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Cited By (5)

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US8918699B2 (en) 2012-07-31 2014-12-23 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage apparatus
US9940192B2 (en) 2012-07-31 2018-04-10 Toshiba Memory Corporation Non-volatile semiconductor storage apparatus
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JP2014059831A (ja) * 2012-09-19 2014-04-03 Nec Computertechno Ltd メモリリフレッシュ装置、情報処理システム、メモリリフレッシュ方法、および、コンピュータ・プログラム
JP2016505184A (ja) * 2013-01-31 2016-02-18 ヒューレット−パッカード デベロップメント カンパニー エル．ピー．Ｈｅｗｌｅｔｔ‐Ｐａｃｋａｒｄ Ｄｅｖｅｌｏｐｍｅｎｔ Ｃｏｍｐａｎｙ， Ｌ．Ｐ． Ｒａｍリフレッシュレート

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CN101796497A (zh) 2010-08-04
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CN101796497B (zh) 2012-03-21
JPWO2009011052A1 (ja) 2010-09-09
KR101043013B1 (ko) 2011-06-21
US20100106901A1 (en) 2010-04-29
KR20100018082A (ko) 2010-02-16
EP2169558A4 (en) 2010-09-15
EP2169558B1 (en) 2015-01-07
EP2169558A1 (en) 2010-03-31

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