WO2008102438A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2008102438A1
WO2008102438A1 PCT/JP2007/053138 JP2007053138W WO2008102438A1 WO 2008102438 A1 WO2008102438 A1 WO 2008102438A1 JP 2007053138 W JP2007053138 W JP 2007053138W WO 2008102438 A1 WO2008102438 A1 WO 2008102438A1
Authority
WO
WIPO (PCT)
Prior art keywords
interlayer insulating
insulating film
same
contact hole
etching stopper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/053138
Other languages
English (en)
French (fr)
Inventor
Kouichi Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to KR1020097017358A priority Critical patent/KR101109028B1/ko
Priority to JP2009500034A priority patent/JP5399232B2/ja
Priority to PCT/JP2007/053138 priority patent/WO2008102438A1/ja
Publication of WO2008102438A1 publication Critical patent/WO2008102438A1/ja
Priority to US12/545,469 priority patent/US8212300B2/en
Anticipated expiration legal-status Critical
Priority to US13/396,129 priority patent/US8796043B2/en
Priority to US14/310,407 priority patent/US9305996B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Semiconductor Memories (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

第１の層間絶縁膜１２１を形成した後、その上にＳｉＯＮからなるエッチングストッパ膜１２２を形成する。次に、エッチングストッパ膜１２２の上面から高濃度不純物領域１１８に到達する第１のコンタクトホールを形成し、Ｗを充填してプラグ１２４を形成する。その後、強誘電体キャパシタ１３１及び第２の層間絶縁膜１３２等を形成した後、第２の層間絶縁膜１３２の上面からプラグ１２４に到達する第２のコンタクトホールを形成し、Ｗを充填してプラグ１３４を形成する。エッチングストッパ膜１２２により、第２のコンタクトホールに位置ずれが発生しても、第１の層間絶縁膜１２１がエッチングされず、水分や不純物が溜まる窪みが発生しない。
PCT/JP2007/053138 2007-02-21 2007-02-21 半導体装置及びその製造方法 Ceased WO2008102438A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020097017358A KR101109028B1 (ko) 2007-02-21 2007-02-21 반도체 장치 및 그 제조 방법
JP2009500034A JP5399232B2 (ja) 2007-02-21 2007-02-21 半導体装置の製造方法
PCT/JP2007/053138 WO2008102438A1 (ja) 2007-02-21 2007-02-21 半導体装置及びその製造方法
US12/545,469 US8212300B2 (en) 2007-02-21 2009-08-21 Semiconductor device
US13/396,129 US8796043B2 (en) 2007-02-21 2012-02-14 Semiconductor device and method for manufacturing the same
US14/310,407 US9305996B2 (en) 2007-02-21 2014-06-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053138 WO2008102438A1 (ja) 2007-02-21 2007-02-21 半導体装置及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/545,469 Continuation US8212300B2 (en) 2007-02-21 2009-08-21 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2008102438A1 true WO2008102438A1 (ja) 2008-08-28

Family

ID=39709724

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053138 Ceased WO2008102438A1 (ja) 2007-02-21 2007-02-21 半導体装置及びその製造方法

Country Status (4)

Country Link
US (3) US8212300B2 (ja)
JP (1) JP5399232B2 (ja)
KR (1) KR101109028B1 (ja)
WO (1) WO2008102438A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018182319A (ja) * 2017-04-07 2018-11-15 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． ３次元半導体メモリ装置及びその製造方法
US11235112B2 (en) 2012-02-29 2022-02-01 Pulmatrix Operating Company, Inc. Inhalable dry powders

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101109028B1 (ko) * 2007-02-21 2012-02-09 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
CN101617399B (zh) * 2007-02-27 2011-05-18 富士通半导体股份有限公司 半导体存储器件及其制造、测试方法、封装树脂形成方法
JP2009231445A (ja) * 2008-03-21 2009-10-08 Toshiba Corp 半導体記憶装置
JP4845937B2 (ja) * 2008-07-24 2011-12-28 株式会社東芝 スピンｍｏｓｆｅｔおよびこのスピンｍｏｓｆｅｔを用いたリコンフィギュラブル論理回路
US8202766B2 (en) * 2009-06-19 2012-06-19 United Microelectronics Corp. Method for fabricating through-silicon via structure
JP2011066126A (ja) * 2009-09-16 2011-03-31 Elpida Memory Inc 半導体記憶装置およびその製造方法
US8669644B2 (en) 2009-10-07 2014-03-11 Texas Instruments Incorporated Hydrogen passivation of integrated circuits
KR101429160B1 (ko) * 2013-06-21 2014-09-23 한국과학기술원 멀티비트 메모리 소자
US9006808B2 (en) 2013-09-09 2015-04-14 Cypress Semiconductor Corporation Eliminating shorting between ferroelectric capacitors and metal contacts during ferroelectric random access memory fabrication
US10090360B2 (en) 2015-02-13 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor structure including a plurality of trenches
US9735049B2 (en) 2015-11-25 2017-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating semiconductor structure with passivation sidewall block
KR102739623B1 (ko) * 2019-09-16 2024-12-06 삼성전자주식회사 반도체 장치
US12469834B2 (en) * 2021-08-27 2025-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823079A (ja) * 1994-07-08 1996-01-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH08204012A (ja) * 1994-07-29 1996-08-09 Nec Corp 半導体装置及びその製造方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243517A (ja) 1992-02-25 1993-09-21 Nec Corp 半導体装置
KR960006068A (ko) * 1994-07-29 1996-02-23 가네꼬 히사시 반도체 장치 및 이의 제조 방법
JP2956482B2 (ja) 1994-07-29 1999-10-04 日本電気株式会社 半導体記憶装置及びその製造方法
EP0720227B1 (en) 1994-12-29 2004-12-01 STMicroelectronics, Inc. Electrical connection structure on an integrated circuit device comprising a plug with an enlarged head
JPH10289950A (ja) 1997-04-15 1998-10-27 Oki Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
JPH11186391A (ja) 1997-12-25 1999-07-09 Toshiba Corp 半導体装置およびその製造方法
JP2000315778A (ja) * 1999-04-30 2000-11-14 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3626058B2 (ja) 2000-01-25 2005-03-02 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP2002110932A (ja) 2000-09-28 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
JP4282245B2 (ja) * 2001-01-31 2009-06-17 富士通株式会社 容量素子及びその製造方法並びに半導体装置
US6734477B2 (en) 2001-08-08 2004-05-11 Agilent Technologies, Inc. Fabricating an embedded ferroelectric memory cell
JP4053307B2 (ja) * 2002-02-15 2008-02-27 富士通株式会社 半導体装置の製造方法
JP2004146772A (ja) * 2002-03-18 2004-05-20 Fujitsu Ltd 半導体装置及びその製造方法
JP2003273217A (ja) * 2002-03-19 2003-09-26 Fujitsu Ltd 半導体装置及びその製造方法
JP4316188B2 (ja) * 2002-05-29 2009-08-19 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
JP2004095861A (ja) * 2002-08-30 2004-03-25 Fujitsu Ltd 半導体装置及びその製造方法
JP4601896B2 (ja) * 2002-10-30 2010-12-22 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8552484B2 (en) * 2004-07-02 2013-10-08 Fujitsu Semiconductor Limited Semiconductor device and method for fabricating the same
JP4785030B2 (ja) 2005-01-18 2011-10-05 富士通セミコンダクター株式会社 半導体装置とその製造方法
TWI295506B (en) 2005-02-03 2008-04-01 Samsung Electronics Co Ltd Semiconductor device having transistor with vertical gate electrode and method of fabricating the same
KR100693249B1 (ko) * 2005-02-03 2007-03-13 삼성전자주식회사 수직한 게이트 전극의 트랜지스터들을 구비하는 반도체장치 및 그 제조 방법
JP4953580B2 (ja) * 2005-03-03 2012-06-13 富士通セミコンダクター株式会社 半導体装置の製造方法
WO2006134664A1 (ja) * 2005-06-17 2006-12-21 Fujitsu Limited 半導体装置及びその製造方法
JP4890804B2 (ja) * 2005-07-19 2012-03-07 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP4800711B2 (ja) * 2005-08-31 2011-10-26 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4690234B2 (ja) * 2006-03-31 2011-06-01 富士通セミコンダクター株式会社 半導体装置及びその製造方法
KR101109028B1 (ko) * 2007-02-21 2012-02-09 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823079A (ja) * 1994-07-08 1996-01-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH08204012A (ja) * 1994-07-29 1996-08-09 Nec Corp 半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11235112B2 (en) 2012-02-29 2022-02-01 Pulmatrix Operating Company, Inc. Inhalable dry powders
JP2018182319A (ja) * 2017-04-07 2018-11-15 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． ３次元半導体メモリ装置及びその製造方法

Also Published As

Publication number Publication date
US9305996B2 (en) 2016-04-05
KR101109028B1 (ko) 2012-02-09
US20120146185A1 (en) 2012-06-14
KR20100004976A (ko) 2010-01-13
US20100019348A1 (en) 2010-01-28
JPWO2008102438A1 (ja) 2010-05-27
US20140299965A1 (en) 2014-10-09
JP5399232B2 (ja) 2014-01-29
US8796043B2 (en) 2014-08-05
US8212300B2 (en) 2012-07-03

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