WO2008092309A1 - Procédé de galvanoplastie d'une carte de circuit imprimé à orifices de passage découverts par masque - Google Patents

Procédé de galvanoplastie d'une carte de circuit imprimé à orifices de passage découverts par masque Download PDF

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Publication number
WO2008092309A1
WO2008092309A1 PCT/CN2007/000573 CN2007000573W WO2008092309A1 WO 2008092309 A1 WO2008092309 A1 WO 2008092309A1 CN 2007000573 W CN2007000573 W CN 2007000573W WO 2008092309 A1 WO2008092309 A1 WO 2008092309A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
copper
hole
via hole
plating
Prior art date
Application number
PCT/CN2007/000573
Other languages
English (en)
Chinese (zh)
Inventor
Dongming Li
Original Assignee
Dongming Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongming Li filed Critical Dongming Li
Publication of WO2008092309A1 publication Critical patent/WO2008092309A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Definitions

  • the invention relates to a process for a via hole wall of a printed circuit board, a soldering place, a partial line thickening of a circuit board or a plating of different metal layers.
  • the printed circuit board via hole metallization and circuit pattern forming process, the double-sided multilayer and flexible circuit board process is: CCL material cutting CNC drilling a surface grinding plate (surface copper foil 'corrosion reduction) a circuit board Electroless plating hole metallization a circuit board surface electroplating copper or surface plating thick copper a surface grinding plate a printing photosensitive ink or a photosensitive film a circuit pattern type film exposure a pattern development a board surface degreasing a pattern electroplating copper ⁇ graphic electroplating tin
  • the circuit pattern is stripped and the circuit board is etched - the board surface and the hole in the hole are removed or the board surface and the hole surface are protected.
  • the photosensitive dry film is cleaned and printed into the solder resist ink.
  • the copper metal plating in the hole of the via hole on the circuit board is made to a certain thickness on the chemically-thickened copper circuit board.
  • the portion of the copper layer that extends beyond the copper of the hole, the surface area of the via hole of the board is about 10% to 20% of the surface area of the board, because the current process cannot solve the problem of plating the via hole without plating the board surface.
  • the problem is that the copper of the hole reaches a certain thickness of the copper of the hole and the copper is again plated on the copper clad copper foil, causing the side of the circuit board to be etched during the etching of the circuit pattern, and the etching is not clean.
  • the through hole copper is etched and the hole is free of copper, which affects the quality of the circuit board and causes waste of copper resources.
  • the current process is a full circuit board circuit pattern and a precious metal layer on the surface of the via hole, especially after the tin plating protective layer is etched. It is etched away or the surface of the circuit board and the surface of the via hole are plated with gold and nickel to make an etching protection layer, which causes great waste of precious metals and chemicals and pollutes the environment.
  • the object of the present invention is to reduce the waste of copper resources and unnecessary waste of precious metals, etc. due to the thickening of the copper layer in the holes of the via holes in the manufacture of the existing circuit board, high energy consumption, complicated process, and environmental pollution.
  • Circuit board mask open hole plating process The object of the present invention can be achieved by the following technical solutions: a printed circuit board mask open-hole plating process includes the following steps -
  • the via hole has been drilled according to the circuit requirements, and the through hole has been metallized copper clad plate, or the via hole has been a circuit board that is metallized and has a conductive circuit pattern;
  • the copper-clad plate or circuit board through the mask plating hole is used to remove the ink or the photosensitive dry film covered by the surface, and the copper-plated plate or circuit board with the through-hole hole position or the soldering position or the portion of the line portion to be thickened locally is obtained. .
  • the circuit board is micro-etched, and the surface of the circuit board is removed except for the thickened portion.
  • the electroless copper plating layer remaining in the surface line gap due to the chemical copper deposition process restores the circuit pattern of the circuit board.
  • the circuit board is micro-etched, the micro-etching agent is divided into an acid micro-etching agent and an alkaline micro-etching agent, and the acid micro-etching is applied to the via hole or the soldering place. Or a partially nickel-plated, gold, silver metal layer of a partially thickened circuit board.
  • the acid micro-etching agent is sulfuric acid plus sodium persulfate, diluted with a concentration of 90% - 95% sulfuric acid to a concentration of 2 - 8%, and persulfuric acid diluted to a concentration of 2-8% in each dilution of sulfuric acid Sodium 30-60 g, room temperature, time 40-60 seconds.
  • Alkaline micro-etching is suitable for the localized tinned metal layer of the via hole or the soldered bit or the partially thickened circuit board of the line part.
  • the alkaline micro-etching agent is added with ammonium chloride solution and ammonium chloride at a concentration of 25%-30. % ammonia water volume solution pH 8 - 9, • Copper ion content is 20-25 grams per liter, chloride ion content is 150-175 grams per liter, temperature is 45-50 degrees, micro-etching time is 30-50 seconds.
  • the positional exposure is developed to expose the vacancies required for the via hole position;
  • the aperture in the aperture film is equal to or greater than the via aperture that is formed on the copper clad block or circuit board according to the design requirements of the circuit board.
  • a copper plate or a circuit board painted with a neon light is partially plated with a metal layer of gold, silver, nickel, tin, etc., and a copper plate or a circuit board is in positional exposure;
  • a mask plating vacancy that is, plating a metal layer of gold, silver, nickel, tin or the like on the copper clad plate or the circuit board exposed by the development to a desired thickness
  • the copper-clad plate or circuit board through the mask vacancy removes the ink or the photosensitive dry film covered by the surface, and the copper-clad plate or circuit board with the desired metal layer is vacated.
  • the desired metal is plated on the vacancy or soldering position of the developed circuit board to a desired thickness, and the developed circuit board is developed.
  • the vacancy is plated with a metal layer of gold, silver, nickel, tin, etc. to a board of the desired thickness, and the solder resist ink is printed.
  • the thickness of the plated copper layer on the surface of the plate is not uniform, so that the thickness of the copper plated in the via hole is lower than the thickness of the plated copper layer on the surface of the copper clad work block and the thickness of the plated copper layer on the surface of the circuit board pattern.
  • the current process board is plated with thick copper or circuit diagram.
  • the type of electroplated copper is only for plating the via hole copper plating and plating a copper plating layer thicker than the hole copper on the copper foil. Since the thickness of the plating layer on the surface of the circuit board is uneven, it appears in the circuit pattern line.
  • the circuit board of the fine thin circuit caused by eclipse or excessive etching is difficult to manufacture, the yield is low, the cost is high, and the copper foil of the original copper clad plate
  • the thickness is relatively uniform, and it is easier to make a circuit pattern.
  • the copper foil with the same thickness on the original copper clad plate cannot be fully utilized in the circuit pattern manufacturing process of the current process.
  • the surface of the soldering surface of the electronic components of the finished circuit board is then subjected to hot air leveling and tin-plating, chemical precipitation, chemical sinking, The process of chemical immersion silver, electroless nickel, gold, and many processes, excessive use of chemical raw materials, causing environmental pollution.
  • the present invention solves the above deficiencies.
  • the technology of the present invention is joined, and the entire process technology can include the following steps:
  • the copper clad plate is opened, and the copper clad plate of the required size is opened.
  • the through hole is drilled by CNC (CNC drilling rig) according to the design requirements of the circuit board.
  • the via hole of the circuit board is degreased and chemically deposited to make a thin layer of copper metal in the via hole and the plate surface.
  • the thickness of the copper layer of the electroless copper plating layer is about 0.3- 0.5 ⁇ m ; the electroless copper plating layer communicates with the via hole in the process of the non-conducting line between the lines of the etched circuit board, and plays an electrically conductive connection when the via hole is plated.
  • the photosensitive ink or the photosensitive dry film is printed, and the photosensitive ink is dried, and the light-drawn through-hole hole film is used, and the alignment exposure is exposed to be exposed. Hole location or required weld or weld or insertion.
  • the wiring gap between the circuit board surface and the via hole is communicated during the metallization of the via hole.
  • the chemically-preserved copper metal layer allows the non-conducting lines to communicate with the via holes, facilitating the conduction of the circuit board during the masking of the open-hole plating, or the conductive effect of plating other metal plating layers on the soldering or insertion positions of the electronic components. Because the copper layer of the chemical copper layer is extremely thin 0.3-0.5 ⁇ m, it is easily micro-etched. After the mask is exposed, the circuit board is micro-etched to remove the via hole during the metallization process.
  • the electroless copper plating process remains in the surface line gap and the electroless copper plating layer between the via hole and the line gap, and the circuit pattern type circuit board which is plated and turned on by the mask open hole via hole is restored, or in the soldering position of the electronic component or The board is plated with other metal-plated boards.
  • the process of plating the metal to the board vacancies or solder pads or lines to the desired thickness may include the following steps:
  • the slag and the chemical immersion copper are used to deposit a thin layer of copper metal in the via hole and the plate surface, and the thickness of the copper layer of the electroless copper plating layer is about 0.3. — 0.5 ⁇ m ;
  • the electroless copper plating layer communicates with the via hole in the process for the non-conducting line between the lines of the etched circuit board, and plays an electrically conductive connection when the via hole is plated.
  • the metallization process to the desired thickness can include the following steps -
  • the copper-plated plate is plated through a mask or plated with other metal bits to remove the ink or photosensitive dry film covered by the surface.
  • the circuit pattern exposure of the copper clad plate is performed by using the prepared photo-electric circuit diagram type film.
  • the process of the printed circuit board through-hole metallization mask dew hole electroplating forming process is to first etch the circuit board on the copper clad working block of the drilled through hole, or to make the circuit pattern of the circuit board, or
  • the surface of the circuit board of the circuit pattern and the via hole are chemically copper-metallized, and the via hole is directly plated with copper, and the via hole of the plated copper metallization is no longer etched.
  • the total surface area of the via hole of the circuit board is smaller than the total surface area of the circuit board, and the surface area of the via hole is about 10%-20% of the surface area of the circuit board, which is more convenient to be turned on.
  • the thickness of the hole copper during the hole plating reaches the required hole copper thickness, and the hole edge of the via hole is slightly larger than the hole diameter of the via hole after plating, and is slightly higher than the copper surface of the circuit board, so that the connection performance of the via hole is more reliable. , to meet the circuit board circuit design requirements.
  • the phosphor bronze used in the copper plating of the process via hole is only 10%-20° when the current circuit board surface or the plating circuit pattern and the via hole are used.
  • the use of the process can save a lot of electric energy, and can save about 80% of phosphor bronze for electroplating, and the process is making electricity.
  • the road pattern and the via hole are copper plated, it is not necessary to add a tin plating or a metal layer such as nickel or gold to the circuit pattern and the via hole as a protective layer for the via hole and the circuit pattern during etching, and no strong nitric acid type is used.
  • the tin liquid saves tin resources, reduces the consumption of precious metals, saves chemical raw materials, saves raw materials and reduces pollution sources at the source of production.
  • the process can directly electroplate the required soldering holes on the circuit board when directly plating the via holes of the circuit board.
  • the metal layers required for the soldering of electronic components such as gold, silver, nickel and tin are directly completed in the process, or the process of hot-air leveling and tin-plating, chemical immersion silver, chemical immersion tin, etc.
  • the process saves energy, reduces production costs, and is environmentally friendly in line with the characteristics of circular economy production.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

L'invention concerne un procédé de galvanoplastie d'une carte de circuit imprimé à orifices de passage découverts par un masque comprenant les étapes suivantes : (1) préparation d'un stratifié cuivré ou d'une carte à orifices de passage métallisés; (2) impression sur la surface du panneau d'un masque réserve à l'encre sensible ou en film sec d'encollage, suivie du séchage; (3) exposition du masque réserve à l'encre sensible ou en film sec au moyen d'un film à motif; (4) développement en vue de l'exposition de la position de l'orifice de passage ou de la partie de la tache laissée par l'impression à épaissir; (5) galvanoplastie du panneau avec le masque à une épaisseur prédéterminée; (6) retrait de l'encre sensible ou du film sec afin d'obtenir un stratifié cuivré ou une carte à orifices de passage ou une partie de circuit épaissie. Le procédé permet d'économiser le cuivre ou d'autres composés métalliques ou chimiques tout en réduisant la pollution environnementale.
PCT/CN2007/000573 2007-01-23 2007-02-15 Procédé de galvanoplastie d'une carte de circuit imprimé à orifices de passage découverts par masque WO2008092309A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200710073024.X 2007-01-23
CNB200710073024XA CN100531527C (zh) 2007-01-23 2007-01-23 印刷电路板掩膜露孔电镀成型工艺

Publications (1)

Publication Number Publication Date
WO2008092309A1 true WO2008092309A1 (fr) 2008-08-07

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PCT/CN2007/000573 WO2008092309A1 (fr) 2007-01-23 2007-02-15 Procédé de galvanoplastie d'une carte de circuit imprimé à orifices de passage découverts par masque

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CN (1) CN100531527C (fr)
WO (1) WO2008092309A1 (fr)

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CN101772270B (zh) * 2009-12-31 2011-11-09 广州杰赛科技股份有限公司 一种挠性印制线路板图形转移的预处理方法
CN107092164A (zh) * 2017-05-09 2017-08-25 苏州固睿特模塑制造有限公司 在多曲面型芯表面加工纹路的方法
CN109287063A (zh) * 2018-11-24 2019-01-29 开平依利安达电子第三有限公司 一种双面多层pcb板及其工艺
CN110719698A (zh) * 2019-11-28 2020-01-21 苏州晶鼎鑫光电科技有限公司 一种用于5g光模块中基于覆铜板上制作预制金锡的制作方法
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CN114096080A (zh) * 2021-11-11 2022-02-25 江苏普诺威电子股份有限公司 印刷电路板中厚孔铜的制作工艺

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EP0472158A2 (fr) * 1990-08-20 1992-02-26 Mitsubishi Rayon Company Ltd. Procédé de fabrication d'un panneau à circuit imprimé
JPH05129778A (ja) * 1991-10-11 1993-05-25 Mitsubishi Rayon Co Ltd プリント配線板の製造方法
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Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101772270B (zh) * 2009-12-31 2011-11-09 广州杰赛科技股份有限公司 一种挠性印制线路板图形转移的预处理方法
CN107092164A (zh) * 2017-05-09 2017-08-25 苏州固睿特模塑制造有限公司 在多曲面型芯表面加工纹路的方法
CN109287063A (zh) * 2018-11-24 2019-01-29 开平依利安达电子第三有限公司 一种双面多层pcb板及其工艺
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