Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0135—Manufacturing their gate conductors
  • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0144—Manufacturing their gate insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0181—Manufacturing their gate insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0172—Manufacturing their gate conductors
  • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants

Definitions

• This invention relates generally to semiconductor devices, and more specifically, to semiconductor devices having an interlayer between a conductive material and a dielectric material.
• CMOS complementary metal-oxide semiconductor
• NMOS complementary metal-oxide semiconductor
• V T threshold voltage
• the materials should be thermally stable at the temperatures used to activate the subsequently formed source and drain regions.
• FIG. 1 illustrates a cross-sectional view of a portion of a semiconductor substrate after forming a dielectric layer and a first interlayer in accordance with an embodiment
• FIG. 2 illustrates the semiconductor substrate of FIG. 1. after forming a first metal electrode and a patterned mask in accordance with an embodiment
• FIG. 3 illustrates the semiconductor substrate of FIG. 2 after removing portions of the first interlayer and the first metal electrode in an NMOS area in accordance with an embodiment
• FIG. 4 illustrates the semiconductor substrate of FIG. 3 after forming the second interlayer and the second metal electrode in accordance with an embodiment
• FIG. 5 illustrates the semiconductor substrate of FIG. 4 after forming a polysilicon gate electrode in accordance with an embodiment
• FIG. 6 illustrates the semiconductor substrate of FIG. 5 after patterning the semiconductor substrate of FIG. 5 in accordance with an embodiment
• FIG. 7 illustrates the semiconductor substrate of FIG. 6 after further processing.
• An interlayer between a conductive material (e.g., an electrode) and a dielectric material is used, in one embodiment, to set the work function of NMOS and PMOS MOSFET (metal oxide semiconductor field effect transistor) devices.
• a substrate is provided and a first stack is formed over the substrate, and forming the first stack includes forming a dielectric layer over the substrate, forming a first layer including a halogen and a metal over the dielectric layer, and forming a metal layer over the first layer.
• an interlayer such as AIF3
• a dielectric e.g., a high dielectric constant dielectric
• a conductive material e.g., a metal gate electrode
• the metal/dielectric interface dipole may be modulated to increase the effective metal work function.
• the interface may be used to modify the electrical properties of interfaces in MOSFETs.
• the interlayer includes a halogen, such as fluorine, V T instability under electrical stress may be improved if the dielectric is doped with the fluorine as a result of forming the interlayer.
• Fluorine may be desirable because it can replace the undesirable chlorine (Cl) impurities that result when high dielectric constants dielectrics are formed.
• the interlayer can be used in other devices, such as DRAM (dynamic random access memory) capacitors and MIM (metal- insulator-metal) capacitors.
• the interlayer (or more than one interlayer) is within a control electrode stack.
• the control electrode stack can be a gate stack (e.g., a gate stack for MOSFETs), a stack for a capacitor (e.g. it may include a metal, a dielectric, and interlayer(s)), a stack for a DRAM, a stack for a non-volatile memory device (NVM), or a stack for another similar device.
• FIG. 1 illustrates a semiconductor device 10 including a substrate 12, a dielectric layer 16, and a first interlayer 18.
• the substrate 12 may be a metal, a semiconductor substrate, the like or combinations of the above.
• the substrate is a semiconductor substrate 12 and includes an isolation region 14, such as a shallow trench isolation (STI) region.
• the semiconductor substrate 12 can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI) (e.g., fully depleted SOI (FDSOI)), silicon, monocrystalline silicon, the like, and combinations of the above.
• SOI silicon-on-insulator
• FDSOI fully depleted SOI
• the dielectric layer 16 in the embodiments illustrated in the figures is a first gate insulating layer 16, such as a high dielectric constant (high-k or hi-k) material (e.g., HfO 2 , Hf x Zr ⁇ x O 2 , or Hf x Zr y O z ), silicon dioxide, or combinations of the above.
• a high-k material has a dielectric constant greater than that of silicon dioxide.
• the dielectric layer 16 can be formed by any suitable process such as thermal growth, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), the like, or combinations of the above.
• the first interlay er 18 is an interlayer between the dielectric layer 16 and a conductive layer, such as a metal gate electrode.
• the first interlayer 18 is an interlayer for a PMOS transistor.
• the first interlayer 18 is any metal halide, such as a metal fluoride, a metal chloride, a metal bromide, a metal iodide, or combinations of the above.
• a metal fluoride may be preferred because fluorine is more electronegative than other halides.
• the first interlayer 18 is a metal fluoride, it may be rubidium fluoride (RbF), lithium fluoride (LiF), cesium fluoride (CsF), magnesium fluoride (MgF 2 ), strontium flrodie (SrF), and scandium fluoride (ScF), aluminum fluoride (AIF 3 ), any combination of a metal and a fluorine (e.g., a material including aluminum and fluorine, such as fluorinated aluminum oxide (AI2O3)), the like, or combinations of the above.
• RbF rubidium fluoride
• LiF lithium fluoride
• CsF cesium fluoride
• MgF 2 magnesium fluoride
• ScF scandium fluoride
• AIF 3 aluminum fluoride
• any combination of a metal and a fluorine e.g., a material including aluminum and fluorine, such as fluorinated aluminum oxide (AI2O3)
• metal fluorides such as rubidium fluoride (RbF), lithium fluoride (LiF), cesium fluoride (CsF), magnesium fluoride (MgF 2 ), strontium fluoride (SrF), and scandium fluoride (ScF), may be more suitable for setting work functions for NMOS devices.
• RbF rubidium fluoride
• LiF lithium fluoride
• CsF cesium fluoride
• MgF 2 magnesium fluoride
• strontium fluoride SrF
• ScF scandium fluoride
• the material chosen for the first interlayer 18 includes a relatively electronegative metal combined with a halogen, such as fluorine.
• a halogen such as fluorine.
• One suitable material is a material including aluminum and fluorine, such as AIF 3 .
• AIF3 is a preferred interlayer for PMOS devices, especially, because it includes a high concentration of electronegative fluorine atoms and a metal cation (aluminum) that is relatively electronegative compared to other metals.
• the high electronegativity of the elements in AIF3 is expected to increase the effective work function of the PMOS device to a desirable level. Metals with higher electronegativity have higher vacuum work functions.
• effective work functions (barrier heights), at metal-dielectric (metal-semiconductor) interfaces are also related to the relative electronegativites of the contacting metal and dielectric.
• AIF3 has a melting temperature of approximately 1260 degrees
• AlF 3 should work well with an underlying hafnium oxide (HfO 2 ) layer, which may be used as the gate oxide, since AlF 3 is reported to not absorb water (H 2 O.) Furthermore, AlF 3 is reported to have good mechanical strength.
• HfO 2 hafnium oxide
• the first interlay er 18 is AlF 3 it can be formed over the dielectric layer 16 by any suitable process such as PVD (e.g., sputtering from an AlF 3 target or reactive sputtering of Al in an Ar/F 2 environment), ALD, CVD, e-beam deposited, the like, or combinations of the above.
• the first layer 18 is AlF 3 , it may be formed by fluorinating an aluminum layer that was previously formed (e.g., formed by CVD, ALD, or PVD).
• the first interlay er 18 is fluorinated Al 2 O 3 , it can be formed by forming the Al 2 O 3 and then fluorinating it. Whether fluorinating Al or Al 2 O 3 (e.g., by ALD, CVD, or PVD), the fluorination can occur by using a gas or plasma of F 2 , CF 4 , C x H y F z , NF 3 , the like, or a combination of the above.
• fluorinating Al or Al 2 O 3 e.g., by ALD, CVD, or PVD
• the fluorination can occur by using a gas or plasma of F 2 , CF 4 , C x H y F z , NF 3 , the like, or a combination of the above.
• the first interlayer 18 may be between approximately 1 to approximately 15
• Capacitance (C) is defined as the dielectric constant (K) times the permittivity of real space ( ⁇ 0 ) times the area of the capacitor (A) all divided by the thickness of the dielectric (t), as shown below:
• C ⁇ '- Since capacitance is inversely proportional to dielectric thickness, it is desirable to minimize the thickness of the metal halide layer.
• the metal halide may have a lower dielectric constant than the dielectric layer which can also degrade the capacitance value.
• the dielectric layer 16 is a high-k dielectric and the first interlay er 18 is AIF 3 , which has a dielectric constant of approximately 4.
• the AIF3 is too thick it will undesirably offset the high dielectric constant of the high-k dielectric so that in effect, the AIF 3 , which is insulating, and the high-k dielectric will both serve as the gate oxide with a lower dielectric constant than just the high-k dielectric alone; this is undesirable.
• the first interlayer 18 does not negatively effect the gate oxide and instead serves as an work-function modulating interlayer between the metal gate and the gate oxide. However, part or all of the first layer 18 may serve as part of the gate oxide.
• a first metal electrode 20 may be formed over the first interlayer 18.
• the first metal electrode 20 may be molybdenum nitride, molybdenum oxynitride, tungsten nitride, ruthenium oxide, ruthenium, titanium nitride, iridium oxide, the like or combinations of the above, which may be particularly suitable for a PMOS device, or tantalum carbide, tantalum silicon nitride, tantalum nitride, titanium nitride, hafnium carbide, hafnium nitride, zirconium carbide, zirconium nitride, tantalum carbide alloyed with another metal, the like, or combinations of the above, which may be particularly suitable for an NMOS device.
• the first metal electrode 20 is the gate electrode for a PMOS device.
• the first metal electrode 20 can be formed by any suitable process, such as CVD, ALD, PVD, sputtering, the like, or combinations of the above.
• a first patterned mask 22 may be formed over the semiconductor device 10, as illustrated in FIG. 2.
• the first patterned mask 22 is formed over the area of the semiconductor device where a PMOS device will be formed (PMOS area).
• the first patterned mask 22 exposes areas of the semiconductor device 10 where NMOS devices will be formed (NMOS area).
• the semiconductor substrate 12 may include wells that are doped either p-type or n-type depending on whether an NMOS or PMOS device is to be formed in that well.
• the first patterned mask 22 can be any suitable mask, such as photoresist.
• the exposed portions of the first metal electrode 20 and the first interlayer 18 may be removed.
• the first metal electrode 20 may be removed by wet etching in piranha or SC-I (Standard Clean 1).
• a piranha clean consists of sulfuric acid, hydrogen peroxide, and water.
• An SC-I clean consists of ammonium hydroxide, hydrogen peroxide, and water.
• the first interlayer 18, in one embodiment, may be removed in a wet etch by HPO 4 , HNO3, CH3COOH, HCl, any other suitable chemistry, or combinations of the above.
• the first interlayer 18 may be removed using a gas that includes HCl, Br 2 , Cl 2 , any other suitable chemistry, or combinations of the above.
• TMAH tetra-methyl ammonium hydroxide
• the first electrode 20 could be dry-etched using a chemical plasma selective to first interlayer 18 and then the interlayer 18 could be removed in a wet etch using chemistries described above.
• a second interlayer 24 and a second metal electrode 26 may be formed over the semiconductor device, as illustrated in FIG. 4.
• the second interlayer 24 and the second metal electrode 26 are formed over the dielectric layer 16 in the NMOS area and over the dielectric layer 16, the first interlayer 18, and the first metal electrode 20 in the PMOS area.
• the second interlayer 24 can be any material previously discussed for the first interlayer 18 and can be formed by any process previously discussed for the first interlayer 18.
• the interlayer 24 is the interlayer for the NMOS area in the embodiments illustrated in the figures, the interlayer is preferably an interlayer material most suitable for NMOS devices, such as RbF, LiF, CsF, MgF 2 , SrF, ScF, the like, or combinations of the above.
• the interlayer includes a metal that is relatively electropositive combined with a halogen, such as fluorine.
• a polysilicon gate electrode 28 may be formed, as shown in FIG. 5.
• the polysilicon gate electrode 28 may be formed by any suitable process, such as CVD.
• the polysilicon gate electrode 28 is much thicker (even than that illustrated in the figures) than the underlying dielectric layer 16, first interlayer 18, first metal electrode 20, the second interlayer 24, and the second metal electrode 26. In one embodiment, the polysilicon gate electrode 28 is approximately 1,000 Angstroms thick.
• the gate stacks are patterned to form the NMOS gate stack 30 and the PMOS gate stack 32, as shown in FIG. 7.
• the NMOS gate includes a portion of the dielectric layer 16, the second interlayer 24, the second metal electrode 26, and the polysilicon gate electrode 28.
• the PMOS gate includes a portion of the dielectric layer 16, the first interlayer 18, the first metal electrode 20, the second interlayer 24, the second metal electrode 26, and the polysilicon gate electrode 28.
• the second interlayer 24 is thin enough to be discontinuous (e.g., approximately 1- approximately 15 Angstroms) so that the first metal electrode 20 and the second metal electrode 26 are electrically connected to each other. If the second interlayer 24 is not thin enough, it (and perhaps the second metal electrode 26) may be removed in the PMOS area. Thus, the PMOS gate stack may not include the second interlayer 24 or the second metal electrode 26.
• the polysilicon gate electrode 28 when forming the NMOS gate stack 30, can be patterned using (masks and) any suitable chemistry, such as Cl 2 , HBr, CF 4 , CH 2 F 2 Ae like and combinations of the above.
• the second metal electrode 26 can be etched using any suitable process, such as a mask and the etching process previously discussed for removing the first metal electrode 20 from the NMOS area.
• the second interlayer 24 may be removed using any suitable process, such as a mask and the chemistries previously discussed for removing the first interlayer 18 from the NMOS area.
• the polysilicon 28 when forming the PMOS gate stack 32, can be patterned using (masks and) any suitable chemistry, as previously discussed for patterning the NMOS gate stack 30.
• the first interlayer 18, the first metal electrode 20, the second interlayer 24 (if present), and the second metal electrode 26 (if present) can be patterned using any suitable process previously discussed for patterning the second interlayer 24 and the second metal electrode 26.
• NMOS source/drain regions 36, the PMOS source/drain region 38, and spacers 34 are formed.
• the NMOS source/drain regions 36 and the PMOS source/drain regions 38 may include extension regions and halo regions (not shown).
• the spacers 34 may be any suitable spacers, such as nitride spacers, L-shaped spacers, or spacers that include combinations of materials (e.g., nitrides and oxides).
• exposed portions of the dielectric layer 16 may be removed (i.e., the dielectric layer 16 may be patterned) using conventional processing. Subsequent conventional processing that is not illustrated may be performed to form features, such as interlevel dielectric layers and interconnect layers to connect various devices on the semiconductor substrates 12.
• the interlayer described also can be used in other devices, such as DRAM capacitors and MIM capacitor structures.
• DRAM and MIM capacitors it may be desirable to form an interlayer that has a metal and a halide (e.g., fluorine) between the top electrode and the dielectric, the bottom electrode and the dielectric, or both.
• the semiconductor substrate 12 may be a metal substrate.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Electrodes Of Semiconductors (AREA)
• Thin Film Transistor (AREA)

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• 2006
  • 2006-05-26 US US11/420,525 patent/US7445976B2/en not_active Expired - Fee Related
• 2007
  • 2007-03-21 JP JP2009513345A patent/JP5254220B2/ja not_active Expired - Fee Related
  • 2007-03-21 WO PCT/US2007/064482 patent/WO2007140037A2/en not_active Ceased
  • 2007-03-21 CN CN2007800192936A patent/CN101569005B/zh not_active Expired - Fee Related
  • 2007-03-30 TW TW096111431A patent/TWI415255B/zh not_active IP Right Cessation

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