Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/05—Making the transistor
  • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B99/00—Subject matter not provided for in other groups of this subclass
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/63—Vertical IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6728—Vertical TFTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
  • H10D62/118—Nanostructure semiconductor bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
  • H10D62/118—Nanostructure semiconductor bodies
  • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
  • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates

Definitions

• This disclosure relates generally to semiconductor devices, and more particularly, to nanofin transistors.
• FIG. 1 illustrates general trends and relationships for a variety of device parameters with scaling by a factor k.
• the continuous scaling of MOSFET technology to the deep sub-micron region where channel lengths are less than 0.1 micron (100 nm or 1000 A) causes significant problems in the conventional transistor structures.
• junction depths should be much less than the channel length.
• the junctions depths 101 should be on the order of a few hundred Angstroms for channels lengths 102 that are approximately 1000 A long. Such shallow junctions are difficult to form by conventional implantation and diffusion techniques.
• Leakage current is a significant issue in low voltage and lower power battery-operated CMOS circuits and systems, and particularly in DRAM circuits.
• the threshold voltage magnitudes are small to achieve significant overdrive and reasonable switching speeds. However, as illustrated in FIG. 2, the small threshold results in a relatively large sub-threshold leakage current.
• Dual-gated or double-gated transistor structures also have been proposed to scale down transistors.
• dual-gate refers to a transistor with a front gate and a back gate which can be driven with separate and independent voltages
• double-gated refers to structures where both gates are driven when the same potential.
• An example of a double-gated device structure is the FinFET.
• TriGate structures and surrounding gate structures have also been proposed. In the “TriGate” structure, the gate is on three sides of the channel. In the surrounding gate structure, the gate surrounds or encircles the transistor channel. The surrounding gate structure provides desirable control over the transistor channel, but the structure has been difficult to realize in practice.
• FIG. 3 illustrates a dual-gated MOSFET with a drain, a source, and front and back gates separated from a semiconductor body by gate insulators, and also illustrates an electric field generated by the drain.
• Some characteristics of the dual-gated and/or double-gated MOSFET are better than the conventional bulk silicon MOSFETs, because compared to a single gate, the two gates better screen the electric field generated by the drain electrode from the source-end of the channel. The surrounding gate further screens the electric field generated by the drain electrode from the source.
• FIG. 4 generally illustrates the improved sub-threshold characteristics of dual gate, double-gate, or surrounding gates MOSFETs in comparison to the sub-threshold characteristics of conventional bulk silicon MOSFETs.
• FIGS. 5A-C illustrate a conventional Fi ⁇ FET.
• FIG. 5 A illustrates a top view of the FinFET and
• FIG. 5B illustrates an end view of the FinFET along line 5B-5B.
• the illustrated FinFET 503 includes a first source/drain region 504, a second source/drain region 505, and a silicon fin 506 extending between the first and second source/drain regions.
• the silicon fin functions as a transistor body, where the channel between the first and second source/drain regions is horizontal.
• a gate insulator 507, such as silicon oxide, is formed over the fin, and a gate 508 is formed over the fin after the oxide is formed thereon.
• the fin of the illustrated conventional FinFET is formed over buried oxide 509.
• FIG. 5 A illustrates a top view of the FinFET
• FIG. 5B illustrates an end view of the FinFET along line 5B-5B.
• the illustrated FinFET 503 includes a first source/drain region 504,
• the fin width is defined by photolithography or e-beam lithography and etch.
• the fin width is initially a minimum feature size (IF).
• the width of the fin is subsequently reduced by oxidation or etch, as illustrated by arrows 510.
• aspects of the present subject matter use a sidewall spacer technique to etch ultrathin nanofins into a wafer, and fabricate nanofin transistors with surrounding gates using these etched nanofins.
• Various embodiments etch silicon nanofins in a silicon substrate.
• the silicon nanofins are used as the body regions of CMOS transistors where both the thickness of the body of the transistor and channel length have dimensions smaller than lithographic dimensions.
• some embodiments provide ⁇ ltrathin nanofins with a thickness on the order of 20 run to 50 nm.
• a fin is formed from a crystalline substrate.
• a first source/drain region is formed in the substrate beneath the fin.
• a surrounding gate insulator is formed around the fin.
• a surrounding gate is formed around the fin and separated from the fin by the surrounding gate insulator.
• a second source/drain region is formed in a top portion of the fin.
• Various embodiments etch a hole in a layer over the substrate, form sidewall spacers in the hole, form a fin pattern from the sidewall spacers, and etch into the crystalline substrate to form the fin from the substrate using a mask corresponding to the fin pattern.
• a transistor embodiment includes a crystalline substrate with trenches etched therein to form a crystalline semiconductor fin from the substrate, a first source/drain region formed in the crystalline substrate at a bottom of the fin and a second source/drain region formed in a top portion of the fin to define a vertically-oriented channel region in the fin between the first and second source/drain regions.
• the transistor also includes a gate insulator formed around the fin, and a surrounding gate formed around and separated from the fin by the gate insulator.
• the fin has a cross- sectional dimension that is less than a minimum feature size.
• FIG. 1 illustrates general trends and relationships for a variety of device parameters with scaling by a factor k.
• FIG. 2 illustrates sub-threshold leakage in a conventional silicon MOSFET.
• FIG. 3 illustrates a dual-gated MOSFET with a drain, a source, front and back gates separated from a semiconductor body by gate insulators, and an electric field generated by the drain.
• FIG. 4 generally illustrates the improved sub-threshold characteristics of dual gate, double-gate, and surrounding gate MOSFETs in comparison to the sub-threshold characteristics of conventional bulk silicon MOSFETs.
• FIGS. 5A-C illustrate a conventional FINFET.
• FIGS. 6A-6L illustrate a process for forming a nanofin transistor, according to various embodiments of the present subject matter.
• FIG. 7 illustrates a top view of a layout of nanofins for an array of nanofin transistors, according to various embodiments.
• FIG. 8 illustrates a process to fabricate a nanofin transistor, according to various embodiments of the present subject matter.
• FIG. 9 illustrates a process to form a fin from a crystalline substrate, according to various embodiments of the present subject matter.
• FIG. 10 is a simplified block diagram of a high-level organization of various embodiments of a memory device according to various embodiments of the present subject matter.
• FIG. 11 illustrates a diagram for an electronic system having one or more nanofin transistors, according to various embodiments.
• FIG. 12 depicts a diagram of an embodiment of a system having a controller and a memory.
• Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art.
• the term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate.
• the term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side”, “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
• nanofin transistors and a fabrication technique in which nanofins are etched into a substrate or wafer and used to make single crystalline nanofin transistors.
• the following discussion refers to a silicon nanofin embodiment.
• Those of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to form nanofins using other semiconductors.
• Aspects of the present subject matter provide nanofin transistors with vertical channels, where there is a first source/drain region at the bottom of the fin and a second source/drain region at the top of the fin.
• FIGS. 6A-6L illustrate a process for forming a nanofin transistor, according to various embodiments of the present subject matter.
• FIG. 6A illustrates a side view of the structure 611 after holes 612 are defined in the amorphous silicon 613 and sidewall spacers 614 are formed. The holes 612 extend to the silicon nitride layer 615, which lies over a substrate 616 such as a silicon wafer. Various embodiments form the sidewall spacers by oxidizing the amorphous silicon.
• FIG. 6B illustrates a side view of the structure 611, after the structure is covered with a thick layer of amorphous silicon 616.
• FIG. 6C illustrates the structure 611 after the structure is planarized, illustrated by the arrow, at least to a level to remove the oxide on top of the amorphous silicon.
• the structure can be planarized using a chemical mechanical polishing (CMP) process, for example. This leaves an elongated rectangular pattern, also referred to as a "racetrack" pattern, of oxide 614 exposed on the surface.
• CMP chemical mechanical polishing
• the width of the pattern lines is determined by the oxide thickness rather than masking and lithography.
• the oxide thickness can be within a range on the order of 20 nm to 50 nm, according to various embodiments.
• FIG. 6D illustrates a mask over the racetrack pattern, which selectively covers portions of the oxide and exposes other portions of the oxide.
• the exposed oxide portions illustrated by the shaded strips, are removed.
• An etch process such as a potassium hydroxide (KOH) etch, is performed to remove the amorphous silicon.
• KOH potassium hydroxide
• the nitride 615 can be etched, followed by a directional silicon etch that etches the wafer 616 to a predetermined depth below the nitride layer.
• FIGS. 6F and 6G illustrate, top and side views of the structure, after the tops of the fins and trenches at the bottom of the fins are implanted with a dopant.
• the dopant in the trench forms a conductive line 618 (e.g. source line).
• the dopant also forms a source/drain region at the bottom or a bottom portion of the fin. Because the fins are extremely thin, the doping in the trench is able to diffuse completely under the fins.
• the strips can be in either the row or column direction.
• FIG. 6H illustrates the structure 611 after a gate insulator 619 has been formed around the fin 617, and a gate material 620 is formed around and separated from the fin by the gate insulator.
• a gate material 620 is formed around and separated from the fin by the gate insulator.
• an embodiment oxidizes the silicon fins using a thermal oxidation process.
• the gate material 620 may be polysilicon or metal, according to various embodiments.
• FIGS. 61 and 6J illustrate a top view and a cross-section view along line 6J-6J, respectively, of a first array embodiment.
• the structure 611 is backfilled with an insulator 621 (e.g. oxide) and trenches are created on the sides of the fins.
• Gate wiring material 622 such as polysilicon or metal, can be deposited and directionally etched to leave on the sidewalls only and contacting the surrounding gates 620 for the fins.
• the gate material and gate wiring material can be etched to recess it below the tops of the fins.
• the whole structure can be again backfilled with oxide and planarized to leave only oxide on the surface.
• Contact openings and drain doping regions can then be etched to the top of the pillars and drain regions implanted and metal contacts to the drain regions made by conventional techniques.
• the metal wiring could run in the "x- direction" and the buried source wiring could run perpendicular to the plane of the paper in the illustration.
• FIGS. 6K and 6L illustrate a top view and a cross-section view along 6L- 6L, respectively, of a second array embodiment.
• the structure 611 is backfilled with an insulator 621 (e.g. oxide) and trenches are created along the side of the fins 617, in the "y-cuiection".
• Q a j e wiring material 622 such as polysilicon or metal, can be deposited and directionally etched to leave on the sidewalls only and contacting the gates on the fins.
• the gate material and gate wiring material can be etched to recess it below the tops of the fins.
• the whole structure can be backfilled with an insulator (e.g. oxide) and planarized to leave only oxide on the surface.
• Contact openings and drain doping regions can then be etched to the top of the pillars and drain regions implanted and metal contacts to the drain regions made by conventional techniques.
• the metal wiring could run perpendicular to the plane of the paper in the illustration and the buried source wiring could run in the "x-direction".
• the buried source/drains can be implanted before the formation of the surrounding gate insulator and surrounding gate.
• FIG. 6L illustrates one of the completed fin structures with drain/source regions 623 and 624, recessed gates 620, and source/drain region wiring 618. These nanofin FET's can have a large W/L ratio and will conduct more current than nanowire FET's.
• FIG. 7 illustrates a top view of a layout of nanofins for an array of nanofin transistors, according to various embodiments.
• the figure illustrates two "racetracks" of sidewall spacers 714, and further illustrates the portions of the sidewall spacers removed by an etch.
• the holes used to form the sidewall spacer tracks were formed with a minimum feature size (IF).
• the mask strips 725 have a width of a minimum feature size (IF) and are separated by a minimum feature size (IF).
• the columns of the nanofins have an approximately 2F center-to-center spacing
• the rows of the nanofins have an approximately IF center-to-center spacing. Also, as illustrated in FIG.
• the center-to-center spacing between first and second rows will be slightly less than IF size by an amount corresponding to the thickness of the nanofins (IF - ⁇ T), and the center-to-center spacing between second and third rows will be slightly more than IF by an amount corresponding to the thickness of the nanofins (IF + ⁇ T).
• FIG. 8 illustrates a process to fabricate a nanofin transistor, according to various embodiments of the present subject matter.
• a fin is formed from a crystalline substrate.
• the fins can be etched from a wafer, such as a silicon wafer.
• a first source/drain region is formed in the substrate at the bottom of the fins.
• a surrounding gate insulator is formed around the fin; and at 829, surrounding gate is formed around and separated from the fin by surrounding the gate insulators.
• the resulting structure is backfilled with an insulator at 830.
• Trench(es) are etched and gate line(s) are formed adjacent to and in contact with the surrounding gate, as illustrated at 831.
• Some embodiments form two gate lines in contact with opposite sides of the surrounding gate.
• the gate lines can be oriented to contact the surrounding gate on a long side of the nanofin structure, or can be oriented to contact the surrounding gate on a short side of the nanofin structure. That is, the gate line(s) can be formed in the column or row directions.
• a second source/drain region is formed in a top portion of the fins, and contacts for the second source/drain regions are formed at 833.
• FIG. 9 illustrates a process to form a fin from a crystalline substrate, such as illustrated at 826 in FIG. 8, according to various embodiments of the present subject matter.
• a layer is formed over the crystalline substrate at 934, and holes are etched or otherwise formed in the layer at 935.
• the layer formed over the crystalline substrate is a layer of amorphous silicon, with a layer of silicon nitride sandwiched between the crystalline substrate and the amorphous silicon, and a hole is etched to the layer of silicon nitride.
• sidewall spacers are formed in the hole against a wall of the layer that defines the periphery of the hole.
• the hole is backfilled with the material of the first layer (e.g. a-silicon), and the structure is planarized at 937.
• the planarization removes the oxide on the top surface of the amorphous silicon, leaving a "racetrack" or rectangular pattern of oxide sidewall spacers.
• a fin pattern is formed from the sidewall spacers, such as may be realized using a mask and etch process, for example.
• the resulting fin pattern has a first cross-section thickness in a first direction that corresponds to a minimum feature size, and a second cross- section thickness in a second direction orthogonal to the first that corresponds to the thickness of the oxide sidewalls and is significantly less than the minimum feature size.
• the layer e.g. a-silicon
• the crystalline substrate is etched at 940 using a mask corresponding to the fin pattern of sidewall spacers.
• Various embodiments etch the silicon nitride layer into fin pattern, and then use the silicon nitride layer to mask the crystalline substrate with the fin pattern when the substrate is etched.
• the mask layer e.g. silicon nitride
• the mask layer is removed to expose the top of the etched fins.
• FIG. 10 is a simplified block diagram of a high-level organization of various embodiments of a memory device according to various embodiments of the present subject matter.
• the illustrated memory device 1042 includes a memory array 1043 and read/write control circuitry 1044 to perform operations on the memory array via communication line(s) or channel(s) 1045.
• the illustrated memory device 1042 may be a memory card or a memory module such as a single inline memory module (SIMM) and dual inline memory module (DIMM).
• SIMM single inline memory module
• DIMM dual inline memory module
• the memory array 1043 includes a number of memory cells 1046.
• the memory cells in the array are arranged in rows and columns.
• word lines 1047 connect the memory cells in the rows
• bit lines 1048 connect the memory cells in the columns.
• the read/write control circuitry 1044 includes word line select circuitry 1049 which functions to select a desired row, bit line select circuitry 1050 which functions to select a desired column, and read circuitry 1051, which functions to detect a memory state for a selected memory cell in the memory array 1043.
• FIG. 11 illustrates a diagram for an electronic system 1152 having one or more nanofin transistors, according to various embodiments.
• Electronic system 1152 having one or more nanofin transistors, according to various embodiments.
• 1152 includes a controller 1153, a bus 1154, and an electronic device 1155, where the bus 1154 provides communication channels between the controller
• the controller and/or electronic device include nanofin transistors as previously discussed herein.
• the illustrated electronic system 1152 may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers.
• FIG. 12 depicts a diagram of an embodiment of a system 1256 having a controller 1257 and a memory 1258.
• the controller and/or memory may include nanofin transistors according to various embodiments.
• the illustrated system 1256 also includes an electronic apparatus 1259 and a bus 1260 to provide communication channel(s) between the controller and the electronic apparatus, and between the controller and the memory.
• the bus may include an address, a data bus, and a control bus, each independently configured; or may use common communication channels to provide address, data, and/or control, the use of which is regulated by the controller.
• the electronic apparatus 1259 maybe additional memory configured similar to memory 1258.
• An embodiment may include a peripheral device or devices 1261 coupled to the bus 1260.
• Peripheral devices may include displays, additional storage memory, or other control devices that may operate in conjunction with the controller and/or the memory.
• the controller is a processor. Any of the controller 1257, the memory 1258, the electronic apparatus 1259, and the peripheral devices 1261 may include nanofin transistors according to various embodiments.
• the system 1256 may include, but is not limited to, information handling devices, telecommunication systems, and computers. Applications containing nanofin transistors as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
• the memory may be realized as a memory device containing nanofin transistors according to various embodiments. It will be understood that embodiments are equally applicable to any size and type of memory circuit and are not intended to be limited to a particular type of memory device.
• Memory types include a DRAM, SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM ⁇ , and DDR SDRAM (Double Data Rate SDRAM).
• SGRAM Synchronous Graphics Random Access Memory
• SDRAM Synchronous Dynamic Random Access Memory
• SDRAM ⁇ Secure Digital Random Access Memory
• DDR SDRAM Double Data Rate SDRAM

Landscapes

• Engineering & Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Nanotechnology (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• Crystallography & Structural Chemistry (AREA)
• Mathematical Physics (AREA)
• Manufacturing & Machinery (AREA)
• Thin Film Transistor (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Semiconductor Memories (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Recrystallisation Techniques (AREA)
• Electrodes Of Semiconductors (AREA)
• Non-Volatile Memory (AREA)

Priority Applications (3)

Applications Claiming Priority (10)

Publications (1)

Family

ID=38325217

Family Applications (4)

Family Applications After (3)

Country Status (5)

Cited By (5)

Families Citing this family (23)

Citations (7)

Family Cites Families (26)

• 2007
  • 2007-04-03 JP JP2009504232A patent/JP5229587B2/ja active Active
  • 2007-04-03 JP JP2009504238A patent/JP5229635B2/ja active Active
  • 2007-04-03 EP EP07754621.6A patent/EP2002468B1/en not_active Not-in-force
  • 2007-04-03 SG SG2011038726A patent/SG172643A1/en unknown
  • 2007-04-03 KR KR1020087026970A patent/KR20090007393A/ko not_active Withdrawn
  • 2007-04-03 JP JP2009504239A patent/JP2009532905A/ja not_active Withdrawn
  • 2007-04-03 KR KR1020087027075A patent/KR20090006169A/ko not_active Ceased
  • 2007-04-03 SG SG201102381-9A patent/SG170827A1/en unknown
  • 2007-04-03 WO PCT/US2007/008400 patent/WO2007114927A1/en not_active Ceased
  • 2007-04-03 EP EP07754850A patent/EP2008309A1/en not_active Ceased
  • 2007-04-03 JP JP2009504280A patent/JP5234439B2/ja active Active
  • 2007-04-03 EP EP07754622A patent/EP2002469A1/en not_active Withdrawn
  • 2007-04-03 WO PCT/US2007/008124 patent/WO2007120493A1/en not_active Ceased
  • 2007-04-03 WO PCT/US2007/008084 patent/WO2007136461A2/en not_active Ceased
  • 2007-04-03 KR KR1020147009477A patent/KR20140051463A/ko not_active Ceased
  • 2007-04-03 WO PCT/US2007/008123 patent/WO2007120492A1/en not_active Ceased
  • 2007-04-03 EP EP07809002.4A patent/EP2002470B1/en active Active
• 2008
  • 2008-11-03 KR KR1020087026973A patent/KR101474028B1/ko active Active
  • 2008-11-04 KR KR1020087027077A patent/KR101378256B1/ko active Active

Patent Citations (7)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events