JP5234439B2 - エッチングで作成したナノFinトランジスタ - Google Patents
エッチングで作成したナノFinトランジスタ Download PDFInfo
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- JP5234439B2 JP5234439B2 JP2009504280A JP2009504280A JP5234439B2 JP 5234439 B2 JP5234439 B2 JP 5234439B2 JP 2009504280 A JP2009504280 A JP 2009504280A JP 2009504280 A JP2009504280 A JP 2009504280A JP 5234439 B2 JP5234439 B2 JP 5234439B2
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- 238000005530 etching Methods 0.000 title claims description 25
- 229910052710 silicon Inorganic materials 0.000 claims description 45
- 239000010703 silicon Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 34
- 125000006850 spacer group Chemical group 0.000 claims description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 22
- 239000012212 insulator Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 14
- 239000002019 doping agent Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000013329 compounding Methods 0.000 claims 1
- SDGKUVSVPIIUCF-UHFFFAOYSA-N 2,6-dimethylpiperidine Chemical compound CC1CCCC(C)N1 SDGKUVSVPIIUCF-UHFFFAOYSA-N 0.000 description 48
- 229950005630 nanofin Drugs 0.000 description 46
- 230000015572 biosynthetic process Effects 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- 238000004891 communication Methods 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Description
"Nanowire Transistor With Surrounding Gate" U.S.Application Serial No. 11/397,527(2006年04月04日出願)、 "Grown Nanofin Transistors" U.S.Application Serial No. 11/397,430(2006年04月04日出願)、 "DRAM With Nanofin Transistors" U.S. Application Serial No. 11/397,413(2006年04月04日出願)、 "Tunneling Transistor With Sublithographic Channel" U.S.Application Serial No. 11/397,406(2006年04月04日出願)の優先日の利益を、ここに請求する。これらの出願はこの参照により本開示に含まれる。
本開示は、半導体装置に全般的に関し、特にナノFinトランジスタに関する。
内のそのFinの底部に形成された第一のソース/ドレイン領域と、Finの頂部に形成された第二のソース/ドレイン領域と、を含んでおり、ここで第二のソース/ドレイン領域によって、Fin内に第一のソース/ドレイン領域と第二のソース/ドレイン領域の間を垂直方向に走るチャネル領域が定められている。このトランジスタにはまた、Finの周りに形成されたゲート絶縁体と、Finの周りにそのゲート絶縁体を間に挟んで形成されたサラウンディングゲートと、も含まれる。Finの断面寸法は、最小フィーチャ寸法(minimum feature size)未満となる。
と同様に構成された付加的なメモリであってもよい。或る実施形態では、バス 1260 に接続した(一個もしくは複数個の)周辺機器 1261 を含んでもよい。そうした周辺機器としては、ディスプレイ、付加的な記憶メモリ、または、制御手段および/もしくはメモリと協働できる他の制御機器、などがある。或る実施形態では、制御手段としてプロセッサを用いる。制御手段 1257 、メモリ 1258 、電子装置 1259 、および周辺機器 1261 のうちのどれでもが、種々の実施形態群にかかるナノFinトランジスタを含んでよい。こうしたシステム 1256 としては、情報処理装置、遠隔通信システム、およびコンピュータがあるが、これらに限定はされない。本開示に記載したナノFinトランジスタに関する用途としては、メモリモジュール、装置ドライバ、電力モジュール、通信モデム、プロセッサモジュール、および特定用途モジュールに使うための電子システムが含まれ、ひいては複数レイヤの、複数チップを含むモジュールを含んでもよい。こうした回路が、時計、テレビジョン、携帯電話、PC、自動車、産業用制御システム、飛行機、などのさまざまな電子システムの副部材であってもよい。
Claims (14)
- 結晶質基板からフィンを形成するステップであって、該フィンを形成するステップが、
前記結晶質基板上に材料を堆積するステップと、
前記材料を堆積した後、最小フィーチャ長を有するマスクパターンを形成し、かつ、該マスクパターンを用いて前記材料をエッチングすることで、前記材料中に少なくとも2つの孔を画定するステップであって、前記材料が、前記少なくとも2つの孔の各々を包囲し且つ画定する側壁を提供し、また、前記少なくとも2つの孔の各々が最小フィーチャ長1つ分の幅を有し、かつ、前記少なくとも2つの孔が最小フィーチャ長1つ分だけ互いに隔てられている、ステップと、
前記少なくとも2つの孔を画定した後、前記孔を包囲し且つ画定する前記側壁の各々に側壁スペーサーを形成するステップと、
前記側壁スペーサーを形成した後、前記側壁スペーサーからフィンパターンを形成するステップであって、該ステップは側壁スペーサーのアレイを形成するステップを含み、前記アレイの第一の行とこれに隣接する前記アレイの第二の行との中心間距離が、前記最小フィーチャ長から前記フィンの厚さを減じた距離であり、また、前記第二の行とこれに隣接する前記アレイの第三の行との中心間距離が、前記最小フィーチャ長に前記フィンの前記厚さを加えた距離である、ステップと、
前記フィンパターンを形成した後、前記フィンパターンをマスクとして用いて、前記結晶質基板から前記フィンをエッチングするステップであって、前記フィンの第一の方向についての断面厚さが前記最小フィーチャ長に対応し、かつ、前記フィンの前記第一の方向に直交する第二の方向についての断面厚さが前記最小フィーチャ長よりも薄く、前記第一の方向が前記基板の表面に平行であり、前記第二の方向が前記基板の前記表面に平行である、ステップと、
を含む、フィンを形成するステップと、
第一のソース/ドレイン領域を、前記結晶質基板内の前記フィンの下方に形成するステップと、
サラウンディングゲート絶縁体を、前記フィンの周りに形成するステップと、
前記フィンの周りに、前記サラウンディングゲート絶縁体によって前記フィンから隔てられたサラウンディングゲートを形成するステップと、
第二のソース/ドレイン領域を、前記フィンの最上部分中に形成するステップと、
を含む、トランジスタを形成する方法。 - 珪素ウェハ上に、窒化物層を形成するステップと、
前記窒化物層の上に、非晶質珪素層を形成するステップと、
パターン化およびエッチングを行なって、前記非晶質珪素層中に少なくとも1つの孔を形成するステップと、
前記非晶質珪素層を酸化して、前記非晶質珪素層中の前記孔の側壁に酸化物側壁スペーサーを得るステップと、
前記非晶質珪素層の酸化の後に、前記孔を非晶質珪素で埋め戻すステップと、
前記孔を非晶質珪素で埋め戻した後に、平坦化を施して、前記酸化物側壁スペーサーの上面を露出させるステップと、
前記平坦化の後に、前記酸化物側壁スペーサーをパターン化およびエッチングして、酸化物のフィンパターンを得るステップと、
前記酸化物側壁スペーサーのパターン化およびエッチングの後に、前記非晶質珪素を除去するステップと、
前記非晶質珪素の除去の後に、前記窒化物層をエッチングして、窒化物のフィンパターンを、前記酸化物のフィンパターンの下方に残すステップと、
前記珪素ウェハを、前記窒化物のフィンパターンをマスクとして使ってエッチングし、複数の珪素フィンを得るステップであって、前記珪素フィンの第一の方向についての断面厚さが最小フィーチャ長に対応し、かつ、前記珪素フィンの第一の方向に直交する第二の方向についての断面厚さが前記最小フィーチャ長よりも薄く、前記第一の方向および前記第二の方向が前記珪素ウェハの表面に平行である、ステップと、
ドーパントを注入して拡散させることで、前記珪素ウェハ中の前記エッチングによって得られた前記複数の珪素フィンの下方に、導電線を形成するステップであって、前記ドーパントによって前記複数の珪素フィンのための第一のソース/ドレイン領域を与える、ステップと、
サラウンディングゲート絶縁体を、前記複数の珪素フィンの周りに形成するステップと、
前記複数の珪素フィンの周りに、前記サラウンディングゲート絶縁体によって前記複数の珪素フィンから隔てられたサラウンディングゲートを形成するステップと、
アレイのうちの隣接するトランジスタ同士のための、複数の前記サラウンディングゲートに隣接し且つ接触する複数のゲート線を形成するステップと、
前記複数の珪素フィンのための第二のソース/ドレイン領域を形成するステップと、
を含む、トランジスタのアレイを形成する方法。 - 前記第一のソース/ドレイン領域を前記珪素ウェハ中の前記珪素フィンの下方に形成するステップが、前記珪素ウェハにおける前記珪素フィンに隣接する溝の中にドーパントを注入するステップと、前記ドーパントを前記珪素フィンの下部に拡散させるステップとを含む、請求項2に記載の方法。
- 前記ドーパントを拡散させるステップが、前記ドーパントを前記珪素フィンの底部分中へと拡散させるステップを含む、請求項3記載の方法。
- 前記サラウンディングゲートの高さが前記珪素フィンの高さよりも低くなるように、前記サラウンディングゲートを埋め込むステップ、をさらに含む、請求項2から4のいずれか一項に記載の方法。
- 前記サラウンディングゲートに隣接し且つ接触するゲートコンタクトを形成するステップをさらに含む、請求項2から5のいずれか一項に記載の方法。
- 前記サラウンディングゲートに隣接し且つ接触する少なくとも1つのゲート線を形成するステップをさらに含み、該ステップが、前記サラウンディングゲートの第一の側に隣接し且つ接触する第一のゲート線と、前記サラウンディングゲートの第二の側に隣接し且つ接触する第二のゲート線と、を形成するステップを含み、前記第一の側と前記第二の側が、前記珪素フィンの相対する側にそれぞれ位置している、請求項2から6のいずれか一項に記載の方法。
- 前記サラウンディングゲートに隣接し且つ接触する少なくとも1つのゲート線を形成するステップをさらに含み、前記珪素フィンの占有領域が、短辺と長辺を有する矩形であり、また、
前記サラウンディングゲートに隣接し且つ接触する前記少なくとも1つのゲート線を形成するステップが、前記長辺上で前記サラウンディングゲートに接触するようにゲート線を形成するステップを含む、請求項2から6のいずれか一項に記載の方法。 - 前記サラウンディングゲートに隣接し且つ接触する少なくとも1つのゲート線を形成するステップをさらに含み、前記珪素フィンの占有領域が、短辺と長辺を有する矩形であり、また、
前記サラウンディングゲートに隣接し且つ接触する前記少なくとも1つのゲート線を形成するステップが、前記短辺上で前記サラウンディングゲートに接触するようにゲート線を形成するステップを含む、請求項2から6のいずれか一項に記載の方法。 - 前記サラウンディングゲート絶縁体を形成するステップが、エッチングによって前記珪素ウェハから得られた前記珪素フィンを、熱酸化するステップを含む、請求項2から9のいずれか一項に記載の方法。
- 前記サラウンディングゲート絶縁体が酸化珪素を含む、請求項2から10のいずれか一項に記載の方法。
- 前記サラウンディングゲートがポリシリコンを含む、請求項2から10のいずれか一項に記載の方法。
- 前記サラウンディングゲートが金属を含む、請求項2から10のいずれか一項に記載の方法。
- 前記サラウンディングゲート絶縁体が、熱成長した酸化珪素である、請求項2から10のいずれか一項に記載の方法。
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