WO2007063667A1 - 回路部材、電極接続構造及びそれを備えた表示装置 - Google Patents
回路部材、電極接続構造及びそれを備えた表示装置 Download PDFInfo
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- WO2007063667A1 WO2007063667A1 PCT/JP2006/321669 JP2006321669W WO2007063667A1 WO 2007063667 A1 WO2007063667 A1 WO 2007063667A1 JP 2006321669 W JP2006321669 W JP 2006321669W WO 2007063667 A1 WO2007063667 A1 WO 2007063667A1
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- electrode
- circuit member
- film
- flexible substrate
- barrier film
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
- H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05573—Single external layer
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
Definitions
- Circuit member including the same
- the present invention relates to a circuit member in which a barrier film and an electrode are formed on a flexible substrate, an electrode connection structure for connecting the electrodes, and a display device including the electrode connection structure.
- Display devices such as liquid crystal displays, organic EL displays, and electrophoretic displays have an active matrix substrate, which is a first circuit member in which a plurality of thin film transistors (hereinafter referred to as TFTs) are formed on a glass substrate. Widely used.
- TFTs thin film transistors
- the plurality of TFTs are arranged in a matrix.
- a plurality of source lines and gate lines connected to each TFT are formed in a grid pattern.
- Each source wiring extends in parallel with each other, while each gate wiring is formed to be orthogonal to each source wiring.
- the ends of the source wiring and the gate wiring extend to the frame area outside the substrate, and terminals (also referred to as electrodes in this specification and the like) are formed.
- a second circuit member such as an IC driver is mounted on the frame region.
- An IC driver or the like has a plurality of electrodes corresponding to the terminals on the mounting surface. Each electrode of the IC driver is electrically connected to each wiring terminal.
- ACF anisotropic conductive film
- conductive particles are dispersed in an adhesive insulating material (binder).
- binder conductive particles are dispersed in an insulating epoxy thermosetting adhesive.
- conductive particles for example, those having a polystyrene cross-linked base as a core and nickel-plated on the surface thereof are known (see, for example, Patent Document 1). .
- a plastic substrate is extremely easy to absorb moisture as compared with a glass substrate, so that there is a problem that the substrate is likely to undergo large expansion and contraction and warpage. Therefore, a noria film such as an inorganic film that does not allow moisture to pass through is usually laminated on the surface of the plastic substrate. In other words, when the plastic substrate is applied to the active matrix substrate (first circuit member), various wirings and terminals are formed on the surface of the noria film laminated on the plastic substrate.
- FIG. 27 is an enlarged cross-sectional view showing the connection structure
- FIG. 28 is an enlarged plan view showing a part of the first circuit member in which a crack has occurred.
- the TFT substrate 101 as the first circuit member is formed on the surface of the plastic substrate 102, the NORA film 103 such as an inorganic film laminated on the plastic substrate 102, and the surface of the NORA film 103. And a terminal 104 which is a first electrode.
- the terminals 104 are arranged at predetermined intervals and are close to each other.
- a force TFT (not shown) has a circuit portion such as a wiring or an electrode formed on the noria film 103 on the TFT substrate 101.
- the IC driver 105 as the second circuit member is provided with a plurality of bumps 106 as the second electrodes.
- An anisotropic conductive film 107 is provided around the bump 106 and the terminal 104 between the IC driver 105 and the TFT substrate 101. In this way, the bump 106 is electrically connected to the terminal 104 by mounting the IC driver 105 on the TFT substrate 101 by pressure bonding.
- the fracture stress of the plating film in the conductive particles is set to be relatively small (for example, 73 MPa or less), while the crimping stress is set to be higher than the fracture stress of the plating film. (See, for example, Patent Document 2). By doing so, we are trying to reduce the damage to the terminals and maintain a good electrical connection.
- Patent Document 1 Japanese Patent Laid-Open No. 9-199206
- Patent Document 2 Japanese Patent Laid-Open No. 2001-337340
- the present invention has been made in view of such various points.
- the object of the present invention is to suppress the propagation of cracks in the barrier film to reduce damage to circuits and electrodes, and to The purpose is to improve the adhesion between the materials.
- the surface force of the flexible substrate is removed from at least a part of the periphery of the first electrode.
- a substrate mainly containing a polymer material such as resin or plastic can be used as the flexible substrate.
- a circuit member according to the present invention is loaded on a flexible substrate and a surface of the flexible substrate.
- a circuit member having a layered barrier film, a circuit portion formed on the barrier film, and a first electrode provided on a side of the flexible substrate on which the noria film is laminated.
- the barrier film is removed from the surface of the flexible substrate at least at a part of the periphery of the first electrode.
- the electrode connection structure includes a flexible substrate, a barrier film stacked on a surface of the flexible substrate, a circuit unit formed on the barrier film, and the possiblity.
- a first circuit member having a first electrode provided on a side of the flexible substrate on which the noria film is laminated; and a first circuit member disposed opposite to the first circuit member and facing the first electrode.
- a second circuit member having two electrodes, in a state where pressure is applied in a direction in which the first electrode of the first circuit member and the second electrode of the second circuit member approach each other.
- the barrier film is connected and removed from the surface of the flexible substrate in at least a part of the periphery of the first electrode.
- the second circuit member includes a main body having a circuit connected to the second electrode, and pressure is applied in a direction in which a part of the main body and the first circuit member approach each other.
- the barrier film may be removed from the surface of the flexible substrate in at least a part of the periphery of the region on the first circuit member that contacts the main body. .
- the first electrode is provided on the flexible substrate via the noria film.
- the first electrode may be provided directly on the surface of the flexible substrate.
- an anisotropic conductive film containing conductive particles is interposed between the first electrode and the second electrode.
- a plurality of the first electrodes may be provided in proximity to each other.
- a common transition electrode may be interposed between the first electrode and the second electrode.
- the first electrode is arranged with a plurality of input-side terminals for inputting signals to the second circuit member and at a predetermined interval with respect to the input-side terminals, and receives signals from the second circuit member.
- the barrier film is also removed in a region between the input side terminal and the output side terminal.
- at least a part of the boundary line defining the removal region is formed in an arc shape when viewed from the normal direction of the surface of the flexible substrate. Also good.
- a plurality of the first electrodes are formed at a predetermined interval, and a removal region from which the barrier film is removed is formed between the adjacent first electrodes, and the width of the removal region is It is preferable that the size is not more than the distance between the adjacent first electrodes.
- a plurality of the first electrodes are formed at a predetermined interval, and a removal region from which the barrier film is removed is formed between the adjacent first electrodes, and the removal region includes a plurality of the removal regions. It is formed in a slit shape.
- a plurality of the first electrodes are formed at a predetermined interval, and a removal region from which the barrier film is removed is formed between the adjacent first electrodes, and the removal regions are adjacent to each other. It may be formed in a wavy shape extending meandering between the first electrodes.
- the electrode connection structure includes a flexible substrate, a barrier film stacked on a surface of the flexible substrate, a circuit unit formed on the barrier film, and the flexible substrate.
- a first circuit member having a first electrode provided on a side of the flexible substrate on which the noria film is laminated; and a first circuit member disposed opposite to the first circuit member and facing the first electrode.
- a second circuit member having two electrodes, in a state where pressure is applied in a direction in which the first electrode of the first circuit member and the second electrode of the second circuit member approach each other.
- the barrier film is connected and formed in a thin film in at least a part of the area around the first electrode than in other areas.
- the display device includes a flexible substrate, a barrier film laminated on a surface of the flexible substrate, a circuit unit formed on the barrier film, and the flexible substrate.
- a first circuit member having a first electrode provided on the side of the conductive substrate on which the above-described noria film is laminated, and a second circuit member disposed opposite to the first circuit member and facing the first electrode.
- the second circuit member having an electrode, the first electrode of the first circuit member, and the second electrode of the second circuit member are electrically connected in a state where pressure is applied in a direction approaching each other.
- a display unit that performs display under the control of the circuit unit of the first circuit member, wherein the barrier film is provided on at least a part of the periphery of the first electrode. The surface force of the flexible substrate is removed.
- the second electrode When the first circuit member (circuit member) has a flexible substrate, the second electrode, for example, is electrically applied in a state where pressure is applied in a direction in which the second electrode approaches each other. When connected, the pressure may cause cracks in the barrier film adjacent to the first electrode.
- the barrier film since the barrier film is removed from the surface of the flexible substrate in at least a part of the periphery of the first electrode, the barrier film is formed even if such a crack occurs. The crack propagates and spreads outside the removed area. As a result, damage caused by cracks in the circuit portion is suppressed.
- the adhesion between the flexible substrate of the first circuit member and the second circuit member is enhanced in the region where the noria film is removed.
- the main body portion of the second circuit member may contact the first circuit member in a state where pressure is applied in a direction approaching each other.
- a noria film is provided in a region on the first circuit member that is in contact with the main body, a crack may occur in the noria film near the region.
- the barrier film is removed from the surface of the flexible substrate in at least a part of the periphery of the region on the first circuit member that is in contact with the main body, such a crack is generated. Even if this occurs, it is possible to prevent the crack from propagating outward beyond the region where the noria film has been removed.
- the first electrode is connected to the second electrode via the conductive particles in the anisotropic conductive film. Electrically connected.
- stress concentrates on the portion of the first electrode that is in contact with the conductive particles cracks are likely to occur in the noria film in the vicinity thereof.
- the area around the first electrode is small. In both cases, since the noria film is partially removed, the spread of cracks can be suppressed. That is, the present invention is particularly effective when an anisotropic conductive film is interposed.
- the barrier film is removed in the region between the input-side terminal and the output-side terminal as the first electrode, the propagation of cracks between the input-side terminal and the output-side terminal is prevented. Further, when the boundary of the removal region of the barrier film is formed in an arc shape, the square shape is reduced at the boundary of the removal region, so that cracks are hardly generated. In addition, if the width of the removal region is defined to be equal to or smaller than the interval between the adjacent first electrodes, it is possible to prevent the propagation of cracks while maintaining the barrier performance of the barrier film.
- the surface area of the barrier film can be increased, so that the barrier property is maintained while removing the barrier film. It becomes possible.
- the noria film is formed thinner than the other regions around the first electrode, the barrier performance of the noria film is maintained and the resistance to cracking is increased, and crack propagation is reduced. It becomes possible.
- the barrier film is removed from the surface of the flexible substrate in at least a part of the periphery of the first electrode, a crack is generated in the NORA film adjacent to the first electrode. Even so, the crack force S can be prevented from spreading outside beyond the area where the barrier film is removed. As a result, damage due to cracks in the circuit portion or the like can be suppressed.
- the flexible substrate of the first circuit member and the second circuit Adhesiveness with a member can be improved.
- FIG. 1 is a plan view showing an external appearance of a liquid crystal display device of Embodiment 1.
- FIG. 1 is a plan view showing an external appearance of a liquid crystal display device of Embodiment 1.
- FIG. 2 is an enlarged cross-sectional view showing the electrode connection structure of the first embodiment.
- FIG. 3 is a cross-sectional view showing a plastic substrate.
- FIG. 4 is a cross-sectional view showing a plastic substrate on which a noria film is laminated.
- FIG. 5 is a cross-sectional view showing a terminal formed in a barrier film shape.
- FIG. 6 is a cross-sectional view showing an insulating film covering the terminals.
- FIG. 7 is a cross-sectional view showing a patterned barrier film and insulating film.
- FIG. 8 is a cross-sectional view showing an ACF that covers a terminal.
- FIG. 9 is an enlarged plan view of the mounting area in FIG.
- FIG. 10 is an enlarged plan view showing a part of FIG.
- FIG. 11 is a cross-sectional view taken along line XI-XI in FIG.
- FIG. 12 is an enlarged cross-sectional view showing the electrode connection structure of the second embodiment.
- FIG. 13 is a schematic cross-sectional view showing an enlarged electrode connection structure of Embodiment 3.
- FIG. 14 is a plan view showing the appearance of the liquid crystal display device of Embodiment 3.
- FIG. 15 is an enlarged plan view showing a part of the TFT substrate.
- FIG. 16 is a plan view showing the appearance of a liquid crystal display device according to another embodiment.
- FIG. 17 is an enlarged cross-sectional view showing the electrode connection structure of the fourth embodiment.
- FIG. 18 is an enlarged plan view showing a terminal and its peripheral region.
- FIG. 19 is an enlarged plan view showing a terminal and its peripheral region.
- FIG. 20 is an enlarged plan view showing a terminal and its peripheral region.
- FIG. 21 is a cross-sectional view taken along line XXI—XXI in FIG.
- FIG. 22 is an enlarged plan view showing a terminal and its peripheral region.
- FIG. 23 is an enlarged plan view showing a terminal and its peripheral region.
- FIG. 24 is an enlarged plan view showing a terminal and its peripheral region.
- FIG. 25 is a cross-sectional view taken along the line XXV—XXV in FIG.
- FIG. 26 is an enlarged plan view showing a terminal and its peripheral region.
- FIG. 27 is an enlarged sectional view showing a conventional electrode connection structure.
- FIG. 28 is a plan view showing a crack spreading in a conventional adjacent terminal.
- FIG. 1 is a plan view showing an appearance of a liquid crystal display device 1 as a display device.
- FIG. 2 is an enlarged sectional view showing the electrode connection structure 2.
- 3 to 8 are cross-sectional views for explaining the manufacturing method of the electrode connection structure 2.
- the liquid crystal display device 1 includes a TFT substrate 10 that is a first circuit member, a counter substrate 11 disposed to face the TFT substrate 10, and the TFT substrate 10 and the counter substrate 11. And a liquid crystal layer (not shown) provided between them.
- an IC driver 12 as a second circuit member and an FPC (flexible printed circuit) 13 are mounted on the TFT substrate 10.
- the FPC 13 is for supplying signals to the IC driver 12, and the IC driver 12 is for controlling and driving each TFT.
- the TFT substrate 10 includes a plurality of TFTs arranged in a matrix, a plurality of gate wirings and source wirings connected to the TFTs and arranged orthogonal to each other, and for each TFT. And a pixel electrode that drives the liquid crystal layer.
- the counter substrate 11 has, for example, a common electrode made of ITO (Indium Tin Oxide) and a color filter.
- the TFT substrate 10 is formed to be larger than the counter substrate 11, and the side end region that does not overlap the counter substrate 11 is mounted on the IC driver 12 and the FPC 13. 9
- a display region 8 which is a display unit for performing display is provided.
- a feature of the present invention resides in the connection structure of the TFT substrate 11 and the IC driver 12. This will be described with reference to FIG.
- the TFT substrate 10 includes a plastic substrate 15 which is a flexible substrate, a barrier film 16 laminated on the surface of the plastic substrate 15, and a circuit unit 17 formed on the noor film 16. Yes.
- the circuit unit 17 includes, for example, the above-described gate wiring and source wiring, TFT, and pixel electrode. In FIG. 2, the circuit unit 17 is schematically shown in a simplified manner.
- a substrate mainly containing a polymer material such as resin or plastic can be used as the flexible substrate.
- the plastic substrate 15 is constituted by a resin substrate.
- the noria film 16 is composed of, for example, an inorganic film, and is configured so as not to transmit at least one of moisture and impurities such as ions and gases.
- the plastic substrate 15 generally has high water absorption, but the surface of the plastic substrate 15 is covered with the above-described noria film 16 so that the water absorption of the plastic substrate 15 is reduced.
- the force shown in the example in which the NORA film 16 is laminated on one side of the plastic substrate 15 may be laminated on both sides of the plastic substrate 15. Good.
- a plurality of terminals 18 as first electrodes are formed and arranged close to each other.
- the terminal 18 is provided on the plastic substrate 15 on the side where the noria film 16 is laminated (that is, the side on which the barrier film 16 is laminated and the IC driver 12 is mounted).
- FIG. 9 is an enlarged plan view of the mounting region 9 in FIG.
- FIG. 10 is an enlarged plan view showing a part of FIG.
- FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. In FIG. 9, only a part of the terminal 18 is shown, and the other terminals 18 are not shown.
- the terminal 18 is arranged with a plurality of input side terminals 18a for inputting signals to the IC driver 12 and at a predetermined interval with respect to the input side terminal 18a.
- the power also has a plurality of output terminals 18b for outputting signals.
- Each input side terminal 18a is formed in, for example, a rectangular shape extending in the up-down direction in FIG. 10 (here, the upward direction is the direction from the side edge of the substrate 15 toward the center). 10 are arranged at predetermined intervals in the left-right direction. Each output terminal 18b is arranged in the same manner as the input terminal 18a on the upper side in FIG. 10 of the input terminal 18a. Each output side terminal 18b is arranged corresponding to the upper side of each input side terminal 18a.
- the output-side terminal 18 b is formed, for example, at the end of the gate wiring of the circuit unit 17 drawn out to the mounting region 9. That is, the terminal 18 is connected to the circuit unit 17.
- the input side terminal 18a is connected to an output side terminal (not shown) of the FPC 13.
- the terminal 18 of the present embodiment is formed on the plastic substrate 15 via the barrier film 16.
- the terminal 18 is covered with an insulating film 19 such as a gate insulating film, for example, and a through hole 20 is formed in the insulating film 19 above the terminal 18. As a result, the terminal 18 is exposed upward through the through hole 20 of the insulating film 19.
- the IC driver 12 includes a main body portion 25 having a circuit (not shown) and a bump 21 that is a second electrode connected to the circuit of the main body portion 25. Yes.
- a plurality of the bumps 21 are formed on the mounting surface 12a on the lower surface of the main body 25, and are arranged close to each other.
- Each bump 21 corresponds to each terminal 18. That is, IC driver 12 is TFT
- the bumps 21 are directed to the terminals 18 through the through holes 20 in a state of being arranged facing the mounting area 9 of the substrate 10.
- the IC driver 12 is mounted on the TFT substrate 10 via an anisotropic conductive film (hereinafter abbreviated as ACF) 22.
- the ACF 22 includes a large number of conductive particles 24 dispersed in a binder 23 that is an insulating material having adhesiveness.
- Each terminal 18 of the TFT substrate 10 and each bump 21 of the IC driver 12 are electrically connected to each other in a state where pressure is applied in a direction approaching each other by thermocompression bonding.
- each terminal 18 and each bump 21 are electrically connected via the conductive particles 24.
- each terminal 18 and each bump 21 are electrically connected by being in direct contact with each other.
- the noor film 16 is removed from the surface of the plastic substrate 15 in at least a part of the periphery of the terminal 18.
- the noria film 16 is removed in a region A surrounded by a wavy line in FIG. 9 (that is, around the input / output portions of the IC driver 12 and the FPC 13). As shown in FIG. 10, the noria film 16 is removed in a region between the input side terminals 18a and between the output side terminals 18b. Therefore, the removal region 26 from which the noria film 16 has been removed is also formed in a substantially rectangular shape, and the surface of the substrate 15 is exposed in the removal region 26 as shown in FIG. In addition, the noria film 16 in the region corresponding to the center of the IC driver 12 is left without being removed.
- the terminal 18 can also be formed on the noria film 16 formed in a strip shape, for example, on the plastic substrate 15. In other words, it is possible to surround most of the periphery of the terminal 18 by the removal region 26 in which the barrier film 16 is removed from the surface of the plastic substrate 15.
- the spatter is applied to the surface of the plastic substrate 15 shown in FIG. Using a thin film deposition technology such as VD, for example, an inorganic film such as SiO or SiNx
- the film 16 is laminated with a thickness of about 0.1 m.
- a plurality of terminals 18 as first electrodes are formed on the surface of the noria film 16 by, for example, photolithography.
- the pattern shape of the plurality of terminals 18 is formed so as to correspond to the arrangement shape of the bumps 21 of the IC driver 12.
- the terminal 18 is made of a single layer or a stack of Al, Ti, Mo, ITO, or the like.
- a suitable film thickness for these terminals 18 is about 0.1 to 0.5 m.
- This first electrode formation step is formed in the same step as the formation step of the gate wiring or source wiring connected to TFT.
- an insulating film forming step is performed, and for example, the insulating film 19 having an SiO, SiNx, etc. force is reduced to 0.
- the insulating film forming process is performed in the same process as the process of forming the gate insulating film constituting the TFT. As shown in FIG. 6, after the insulating film 19 covering the terminal 18 is uniformly formed on the noria film 16, the insulating film 19 is removed from the periphery of the terminal 18 by photolithography as shown in FIG. At the same time, a through hole 20 is formed above the terminal 18.
- a noria film removal step is performed to partially remove the noria film 16 from the peripheral force of the terminal 18.
- This noria film removal step is performed overlapping with the insulating film formation step. That is, as shown in FIG. 7, the insulating film 19 and the barrier film 16 are simultaneously removed from the periphery of the terminal 18 by photolithography.
- the noria film 16 is removed in the region A surrounded by the wavy line in FIG.
- the noria film 16 is removed in regions between the input terminals 18a and between the output terminals 18b. That is, the removal region 26 of the noria film 16 is also formed in a substantially rectangular shape.
- the surface of the substrate 15 is exposed in the removal region 26 of the noria film 16.
- the barrier film 16 in the region corresponding to the center of the IC driver 12 is left without being removed.
- the noria film 16 on the resin substrate is removed.
- the removal region 26 of the barrier film 16 is a peripheral portion outside the plastic substrate 15, the inner display region 8 is affected. Don't give.
- the removal region 26 is smaller than the entire area of the noria film 16, there is no adverse effect such as a decrease in moisture resistance on the plastic substrate 15 due to the removal of the barrier film 16.
- the noria film may also remove the surface force of the plastic substrate 15 in at least a part of the periphery of the terminal 18, but it may be removed over a wider periphery of the terminal 18 in order to further suppress the propagation of cracks.
- an ACF sticking step is performed.
- the ACF 22 is pasted on the plastic substrate 15 so as to cover the terminals 18 and the insulating film 19, and is temporarily attached.
- ACF22 for example, an epoxy-based adhesive in which conductive particles are dispersed is used.
- the IC driver 12 as the second circuit member is mounted on the TFT substrate 10 by heating and pressurizing while the terminals 18 and the bumps 21 are aligned and aligned.
- the bump 21 of the ACF IC driver 12 is electrically connected to the terminal 18 through the conductive particle 24 inside the through hole 20.
- the electrode connection structure 2 is manufactured through the above steps.
- thermocompression bonding tool for mounting the IC driver 12
- a tool for thermocompression bonding at a relatively low temperature is preferable.
- the pressure for thermocompression bonding the IC driver 12 is 10-50 MPa, and the temperature is about 180 ° C.
- the barrier film 16 is removed from the surface of the plastic substrate 15 around the terminal 18, even if a crack is generated in the noria film 16 below the terminal 18, the crack is generated. It is possible to prevent the force barrier film from spreading outward beyond the region where the force barrier film has been removed (removal region 26). As a result, damage due to cracks in other adjacent terminals 18 and circuit portions 17 can be suppressed, and the defective product rate can be reduced.
- the above-mentioned nore film 16 has a force capable of preventing the permeation of moisture, and its adhesion to the plastic substrate 15 tends to be weakened.
- the V and the oxide film are partially removed in the removal region 26, and therefore the plastic substrate 15 and the IC driver 12 are bonded to the ACF 22 in that portion. It can be directly bonded by the layer 23 and the adhesion can be improved.
- the propagation of cracks in the NOR film 16 is suppressed to reduce damage to the circuit portion 17 and the adjacent terminal 18, and the adhesion between the plastic substrate 15 and the IC driver 12 is improved. Can be increased.
- ACF 22 is interposed between terminal 18 and bump 21, stress is particularly concentrated on the barrier film 16 below terminal 18 at the contact portion with conductive particles 24, and cracks are generated. Is likely to occur.
- this embodiment even if a crack occurs, the spread can be effectively suppressed.
- FIG. 12 shows Embodiment 2 of the present invention.
- the same portions as those in FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted.
- the barrier film 16 is left in a strip shape between the terminal 18 and the bump 21, whereas in the present embodiment, the barrier film 16 is interposed between the terminal 18 and the bump 21. Is not provided.
- the noria film 16 is also removed under the terminal 18 and the insulating film 19 that are connected only by the removal region 26 around the terminal 18. That is, the terminal 18 is formed directly on the surface of the plastic substrate 15 of the TFT substrate 10.
- the barrier film 16 is uniformly laminated on the plastic substrate 15 after the barrier film 16 is uniformly laminated on the plastic substrate 15, all of the regions where the plurality of terminals 18 are formed are formed.
- a region to be included is defined as a removal region 30, and the barrier film 16 in the removal region 30 is removed from the surface of the plastic substrate 15 by photolithography or the like.
- the terminal 18 is patterned in the removal region 30. Thereafter, an insulating film forming step is performed as in the first embodiment. Subsequently, as in the first embodiment, the ACF attaching process and the mounting process are performed. As a result, the electrode connection structure 2 is manufactured.
- the barrier film 16 itself is not provided below the terminal 18, no crack is generated even if pressure is applied to the terminal 18. Therefore, damage due to cracks in the adjacent terminals 18 can be prevented.
- the first embodiment is preferable because the area of the surface of the plastic substrate 15 covered with the noria film 16 is larger.
- FIG. 13 to 15 show Embodiment 3 of the present invention.
- FIG. 13 is a cross-sectional view schematically showing the liquid crystal display device 1 of the present embodiment
- FIG. 14 shows the liquid crystal display device 1 of the present embodiment.
- FIG. 15 is a plan view schematically showing an appearance
- FIG. 15 is a plan view showing a part of the TFT substrate 10 in an enlarged manner. Note that FIG. 13 is simplified for convenience of explanation, and does not correspond to FIG.
- the TFT substrate 10 that is the first circuit member and the counter substrate 11 that is the second circuit member are constituted by the plastic substrates 15 and 35, respectively.
- a NORIA film 16 is laminated on the plastic substrate 15 of the TFT substrate 10 on the counter substrate 11 side.
- the plastic substrate 35 of the counter substrate 11 is laminated with a noria film 36 on the TFT substrate 10 side.
- a liquid crystal layer 30 is provided between the TFT substrate 10 and the counter substrate 11 and is sealed by a seal member 41.
- circuit portions 17 such as gate wirings and source wirings formed in the display region 8 are formed.
- the TFT substrate 10 is provided with a common electrode pad 31 as a first electrode around the display area 8.
- the first common electrode pad 31 is connected to the wiring portion 33 led out to the mounting region 9.
- a second common electrode pad 32 that is a second electrode is provided on the counter substrate 11 so as to face the first common electrode pad 31.
- a common electrode 34 having an ITO isotropic force is laminated on the barrier film 36 in the display region 8. The second common electrode pad 32 is connected to the common electrode 34.
- a common transition electrode 37 is interposed between the TFT substrate 10 and the counter substrate 11 outside the liquid crystal layer 30.
- the first common electrode pad 31 and the second common electrode pad 32 are electrically connected via the common transition electrode 37 in a state where pressure is applied in a direction approaching each other. In this way, the electric signal supplied to the mounting region 9 side force on the TFT substrate 10 via the wiring portion 33 is supplied to the common electrode 34 of the counter substrate 11 via the first and second common electrode pads 31, 32 and the common transition electrode 37. Supplied to.
- the barrier film 16 of the TFT substrate 10 is removed from the surface of the plastic substrate 15 in the region where the first common electrode pad 31 is provided.
- the barrier film 36 of the counter substrate 11 is removed from the surface of the plastic substrate 35 in the region where the second common electrode pad 32 is provided.
- the first and second common electrode pads 31, 32 are respectively directly on the surfaces of the plastic substrates 15, 35 from which the noria films 16, 36 have been partially removed. Is formed.
- the region where the first and second common electrode pads 31 and 32 are provided is the removal region 26 where the noria films 16 and 36 are removed.
- the first and second common electrode pads 31 and 32 are formed after the step of removing the barrier films 16 and 36. Thereafter, the TFT substrate 10 and the counter substrate 11 are bonded together with the common transition electrode 37 interposed therebetween.
- the noria films 16 and 36 are in areas where the common transition electrodes 37 are disposed. Since the stress increases, cracks are likely to occur, and the cracks propagate to the surroundings. In contrast, in this embodiment, since the barrier films 16 and 36 are removed from the region where cracks are likely to occur, the adjacent circuit portion 17 and the other first and second common electrode pads 31 and 32 are removed. On the other hand, since it is possible to prevent cracks from propagating through the noria films 16 and 36, it is possible to prevent deterioration in display quality.
- the Noria films 16, 36 are partially left in the region overlapping the common transition electrode 37, the Noria films 16, 36 are placed on the plastic substrates 15 and 35 in the surrounding regions. You may make it remove from the surface. As a result, even if a crack occurs in the barrier films 16 and 36 that overlap the first and second common electrode pads 31 and 32, the crack does not spread beyond the removal region 26 to the outside. Can be. As a result, it is possible to suppress damage due to cracks in the adjacent circuit portion 17 and other first and second common electrode pads 31 and 32, and to suppress deterioration in display quality.
- FIG. 17 shows Embodiment 4 of the present invention.
- FIG. 17 is a cross-sectional view schematically showing the liquid crystal display device 1 of the present embodiment.
- the IC driver 12 is preferably mounted so that the plate-like main body 25 is parallel to the TFT substrate 10.
- the main body 25 may be mounted in a state tilted with respect to the TFT substrate 10. Further, when the inclination is large, a part of the main body 25 and the TFT substrate 10 may be insulted in a state where pressure is applied in a direction approaching each other.
- FIG. 21 is a cross-sectional view taken along line XXI—XXI in FIG.
- FIG. 23 is a sectional view taken along line XXIII—XXIII in FIG.
- FIG. 25 is a sectional view taken along line XXV—XXV in FIG.
- the fifth embodiment is obtained by changing the removal region 26 of the noria film 16 into various shapes as described below in the first embodiment.
- the removal region 26 of the barrier film 16 is formed on both the left and right sides of the terminal 18, while the noria film 16 in the region corresponding to the center of the IC driver 12 is not removed and left behind.
- the removal region 26 may be formed so as to extend in the vertical direction and the horizontal direction in the same figure in the region of the barrier film 16 corresponding to the center of the IC driver 12. . That is, the noria film 16 is also removed in the region between the input side terminal 18a and the output side terminal 18b. Thus, the surface of the substrate 15 is exposed in the removal region 26.
- the removal region 26 extending in the left-right direction, it is possible to prevent cracks from propagating between the input side terminal 18a and the output side terminal 18b.
- the removal region 26 may be formed so that at least a part of the boundary line that defines the removal region 26 has an arc shape when viewed from the normal direction of the surface of the substrate 15. That is, as shown in FIG. 19, the removal region 26 is formed so as to extend in the vertical direction from the input side to the output side of the terminal 18, and the upper and lower ends of the removal region 26 protrude outward in the vertical direction. It may be formed in an arc shape. In this way, the square shape is eliminated at the upper and lower ends of the removal region 26, so that cracks can be generated. Next, as shown in FIG. 20, the removal region 26 is formed so as to extend in the upward and downward direction from the input side to the output side of the terminal 18, and as shown in FIG.
- the distance L1 between the left and right directions of each other and the width L2 in the left-right direction of the removal region 26 may be limited to a predetermined relationship.
- the width L2 of the removal region 26 is preferably narrow in order not to deteriorate the barrier performance due to the NOR film 16.
- the minimum width L2 of the removal region 26 is about several zm.
- the width L2 of the removal region 26 is wide. Therefore, it is desirable that the width L2 of the removal region 26 be limited to several m or more and the interval L1 between the terminals 18 or less. By doing so, it is possible to prevent the propagation of cracks while maintaining the barrier performance of the barrier film 16.
- the removal region 26 is formed so as to extend in the upward and downward direction from the input side to the output side of the terminal 18, and as shown in FIG. Further, at least a part of the area around the input side terminal 18a and the output side terminal 18b may be formed to be thinner than other areas. In other words, in the removal region 26, the NOR film 16 may not be completely removed and may remain thin. At this time, the surface of the substrate 15 in the removal region 26 is covered with the noria film 16 thinned to a thickness of about 200 to 300 A, for example. Therefore, the NORIA performance by the NORIA film 16 can be maintained, the resistance to cracks is increased, and the propagation of cracks can be reduced.
- the removal region 26 may be formed so as to extend upward and downward from the input side to the output side of the terminal 18, and the removal region 26 may be formed in a slit shape. Good.
- the removal region 26 is constituted by, for example, two slits formed in the NOR film 16.
- the surface of the substrate 15 is exposed.
- the surface area of the noria film 16 can be increased, so that the noriality can be maintained while removing the noria film 16.
- the noria film 16 since the noria film 16 is removed, the propagation of cracks can be prevented. Two or more slits may be provided. By forming a plurality of slits, propagation of cracks can be further reduced.
- the removal region 26 is formed so as to extend upward and downward from the input side to the output side of the terminal 18, and the removal region 26 is formed between the adjacent terminals 18.
- it may be formed in a wavy shape extending meandering in the vertical direction in FIG. Even in this case, since the surface area of the barrier film 16 can be increased, the propagation of cracks can be prevented while maintaining the barrier performance.
- the force described with respect to the example in which the IC driver 12 or the counter substrate 11 is connected to the TFT substrate 10 that is, the example in which the second circuit member is the IC driver 12 or the counter substrate 11. It is not limited. That is, for example, as shown in FIG. 16, it can be similarly applied to an electrode connection structure in TCP (Tape Carrier Package) connection by TAB or COF. That is, as shown in FIG. 16, a plurality of TCPs having IC drivers 42 are connected to the mounting region 9 of the TFT substrate 10. These TCPs are also provided with a second electrode, and this second electrode is connected to the first electrode (terminal) of the TFT substrate 10. Further, the present invention can be similarly applied to the electrode connection structure in the connection portion of the FPC 13 in FIG.
- TCP Transmission Carrier Package
- the terminal 18 and the bump 21 are connected via the ACF22.
- the present invention is not limited to this, and the ACF22 is not provided in any other way. In other words, the same applies to the case where electrodes are directly bonded to each other), or when conductive paste, NCF (Non Conductive Film), adhesive grease, etc. are interposed instead of ACF22. be able to.
- a liquid crystal display device has been described as an example of a display device.
- the present invention is not limited to this, and for example, an organic EL device, a field emission display (FED), or the like.
- the present invention can also be applied to other display devices.
- the present invention is not limited to this, and a metal substrate, for example, may be applied to the substrate 15. Even a metal substrate is flexible when it is thin, and cracks can occur in the barrier film provided on the surface of the metal substrate, as in the case of a plastic substrate. In other words, when a metal substrate is applied to the substrate 15, the circuit manufacturing process can be performed at a high temperature, so that a higher performance circuit can be manufactured. However, since there are usually many concaves and convexes on the surface of the metal substrate, it is necessary to perform planarization (barrier film formation) before circuit fabrication.
- a metal material such as stainless steel or invar can be used, and the surface of the substrate is preferably subjected to a mirror finish in advance.
- a metal material such as stainless steel or invar
- an inorganic material thin film, an organic material thin film, or a laminated thin film thereof can be used, and a method such as spin coating, bar coating, or spray coating can be used for coating.
- the manufacturing process is performed in the same manner as in the first embodiment.
- the present invention is useful for an electrode connection structure for connecting electrodes of a plurality of circuit members, and a display device having the electrode connection structure, and in particular, a resin substrate constituting a circuit board. This is suitable for suppressing the propagation of cracks in the noria film laminated on the substrate, suppressing the damage to the electrodes and improving the adhesion between the circuit members.
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Abstract
Description
Claims
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US12/063,152 US7957151B2 (en) | 2005-12-01 | 2006-10-30 | Circuit component, electrode connection structure and display device including the same |
CN200680029260A CN100594759C (zh) | 2005-12-01 | 2006-10-30 | 电路部件、电极连接构造以及具备它们的显示装置 |
JP2007547875A JP4820372B2 (ja) | 2005-12-01 | 2006-10-30 | 回路部材、電極接続構造及びそれを備えた表示装置 |
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US (1) | US7957151B2 (ja) |
JP (1) | JP4820372B2 (ja) |
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WO2012172768A1 (ja) * | 2011-06-16 | 2012-12-20 | シャープ株式会社 | 表示装置 |
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EP2020836A1 (en) * | 2007-08-03 | 2009-02-04 | Samsung SDI Co., Ltd. | Circuit board connection structure and plasma display apparatus including the same |
JP2011138090A (ja) * | 2010-01-04 | 2011-07-14 | Seiko Epson Corp | 電子デバイス用基板、電子デバイス及びこれらの製造方法並びに電子機器 |
WO2012172768A1 (ja) * | 2011-06-16 | 2012-12-20 | シャープ株式会社 | 表示装置 |
KR20140080240A (ko) * | 2012-12-20 | 2014-06-30 | 엘지디스플레이 주식회사 | Fpcb와의 전기적 접속이 원활한 표시소자 |
KR101980761B1 (ko) * | 2012-12-20 | 2019-05-21 | 엘지디스플레이 주식회사 | Fpcb와의 전기적 접속이 원활한 표시소자 |
JP2020170148A (ja) * | 2013-06-17 | 2020-10-15 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 表示装置 |
US11264408B2 (en) | 2013-06-17 | 2022-03-01 | Samsung Display Co., Ltd. | Array substrate and organic light-emitting display including the same |
JP7079803B2 (ja) | 2013-06-17 | 2022-06-02 | 三星ディスプレイ株式會社 | 表示装置 |
US11916087B2 (en) | 2013-06-17 | 2024-02-27 | Samsung Display Co., Ltd. | Array substrate and organic light-emitting display including the same |
JP2015148728A (ja) * | 2014-02-06 | 2015-08-20 | 株式会社ジャパンディスプレイ | 表示装置及びその製造方法 |
JP2019038105A (ja) * | 2017-08-22 | 2019-03-14 | 株式会社 大昌電子 | 静電駆動アクチュエータ組み込みプリント配線板装置およびその製造方法 |
JP7195082B2 (ja) | 2017-08-22 | 2022-12-23 | 株式会社 大昌電子 | 静電駆動アクチュエータ組み込みプリント配線板装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4820372B2 (ja) | 2011-11-24 |
CN101238759A (zh) | 2008-08-06 |
US20090141438A1 (en) | 2009-06-04 |
CN100594759C (zh) | 2010-03-17 |
US7957151B2 (en) | 2011-06-07 |
JPWO2007063667A1 (ja) | 2009-05-07 |
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