Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/62—Capacitors having potential barriers
  • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D18/00—Thyristors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B99/00—Subject matter not provided for in other groups of this subclass
  • H10B99/20—Subject matter not provided for in other groups of this subclass comprising memory cells having thyristors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D18/00—Thyristors
  • H10D18/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/80—PNPN diodes, e.g. Shockley diodes or break-over diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Definitions

• This invention relates to recessed thyristor-based memory cell design for an integrated circuit.
• a traditional dynamic random access memory (DRAM) cell comprises a capacitor for storing charge representative of a logic '0' or '1' state, and an access transistor for accessing such charge and sending it via a bit line to a sensing circuit.
• DRAM dynamic random access memory
• Such a cell design is beneficial in that it can be made relatively dense, and hence many such cells can be placed on a given integrated circuit, amounting in large amounts of memory.
• DRAM cells are not optimal. As just noted, such cells require two elements per cell — the capacitors and the access transistor. While many different DRAM cell designs exist with the goal of reducing the area such cells take up on the surface of an integrated circuit, the reality is that accommodating two elements per cell comprises a significant sizing issue.
• thyristors As the storage element in a memory cell, it has been proposed to use thyristors as the storage element in a memory cell.
• a thyristor essentially comprises two diodes in series, or what is sometimes referred to as a PNPN structure, which reflects that the device is formed by doping of alternating polarities (P and N).
• thyristor-based cells can be used to selectively store charge, and hence such cells are useable as memory cells. For example, charge can be stored by causing the junctions within the structure to become reversed biased, and such selective storage can be facilitated by gating the thyristor.
• charge can be stored by causing the junctions within the structure to become reversed biased, and such selective storage can be facilitated by gating the thyristor.
• thyristor-based memory cell designs are non optimal.
• Such cell designs therefore suffer from the same drawback as traditional DRAM cells in that they require two devices — an access transistor, and the gated thyristor.
• thyristor-based cells not having an access transistor previous structures still generally take up inordinate amounts of area on the surface of the integrated circuit, for example, because the thyristor is built planar (i.e., horizontally) in the substrate of the integrated circuit.
• thyristor-based cells not having access transistors have been advocated as replacements for traditional SRAM cells, and it is not believed that such cells have been designed as DRAM cells, which are preferable to SRAM cells in many applications.
• Still other thyristor designs require the device's substrate to be isolated from the bulk substrate, for example, by using a buried oxide (Box) or by using a SOI (silicon-on-insulator) substrate. Using such specialized substrates adds complexity and cost to the manufacture of the thyristor-based cell.
• the memory cell art would be benefited from an improved thyristor cell design similar in functionality to a DRAM cell, and such a cell design would be small, would not require additional devices such as access transistors, and would be easily and cheaply manufactured. Embodiments of such a cell design are disclosed herein.
• the disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell.
• a thyristor Vertically disposed around this recessed gate is a thyristor, whose anode (source; p-type region) is connected to the bit line and cathode (drain; n- type region) is connected to the word line.
• the disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device.
• the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell.
• the disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell, while not required in all useful embodiments, assists in improving the data retention of the cell and extends the time needed between cell refresh.
• Figure 1 illustrates a schematic of the disclosed recessed thyristor-based cell.
• Figure 2 illustrates an embodiment of the disclosed recessed thyristor- based cell in cross section.
• Figure 3 illustrates the current-voltage characteristics of the thyristor in the disclosed cell.
• Figure 4 illustrates an array of the disclosed recessed thyristor-based cells, including array driving and sensing circuitry.
• Figure 5 illustrates exemplary voltage conditions for writing a logic '0' or '1' to the disclosed cell, for reading the disclosed cell, and for holding a voltage in the disclosed cell.
• Figures 6A-6D illustrate an exemplary process for fabricating the disclosed recessed thyristor-based cell.
• Figures 7A-7C illustrate an exemplary process for fabricating the disclosed recessed thyristor-based cell using epitaxially-grown silicon to form regions of the thyristor.
• Figures 8A-8B illustrate an exemplary process for fabricating the disclosed recessed thyristor-based cell using junction isolation underneath the cell.
• Figure 9 illustrates an exemplary process for fabricating the disclosed recessed thyristor-based cell using a buried oxide layer or an SOI substrate underneath the cell.
• Figure 10 illustrates an exemplary process for fabricating the disclosed recessed thyristor-based cell using isolation undercuts partially underneath the cell.
• the improved thyristor-based memory cell 10 is shown schematically in Figure 1.
• the cell 10 comprises a thyristor 20, which as noted earlier is a PNPN structure and hence is represented as two serially-connected diodes for ease of illustration.
• the anode or source of the thyristor 20 (the outer P-region) is coupled to bit line 14.
• the cathode or drain of the thyristor 20 (the outer N-region) is coupled to a word line 12.
• the thyristor 20 is gated by an enable gate 16.
• the cell 10 is simple in design. It requires only a single gate (16), and thus comprises a one-transistor cell, somewhat akin to the access transistor of a traditional DRAM cell, but without a discrete storage capacitor. Moreover, and as will be seen in subsequent Figures, the thyristor 20 portion of the cell is realizable in compact fashion in a traditional semiconductor substrate, e.g., a p-doped substrate.
• the cell 10 does not require substrate isolation below the cell, although, as will be discussed with reference to Figures 8-10, such isolation if used can further improve the performance of the cell and can increase the time needed between refreshes of the cell.
• the cell 10 is preferably recessed into the substrate 25, as shown in one embodiment in Figure 2.
• the enable gate 16 meets with a conductive plug 22 formed in a trench into P-substrate 25.
• a gate oxide 27 separates the plug 22 from the substrate 25 to allow the thyristor 20 to be gated.
• the thyristor 20 is not planar, but instead is formed vertically formed around the trench in the shape of a "U.” This non-planar configuration further decreases the amount of area that the cell 10 occupies on the substrate 25.
• Figure 3 shows the principle upon which the thyristor-based cell 10 operates with reference to a current-voltage curve. As this principle is well known, it is only briefly discussed.
• Vthy voltage across the thyristor
• Vblock a certain threshold
• minority carriers are injected into base (i.e., substrate 25) of the thyristor, and the thyristor enters a period of negative differential resistance, after which the voltage Vthy falls and the current through the thyristor (Ithy) sharply increases.
• Vthy exceeds Vblock
• the cell can be said to be programmed to a logic '1' state, and will draw an appreciable current. If Vthy does not exceed Vblock, then the thyristor is not triggered, and the current remains relatively low, i.e., a logic '0' state.
• the cell 10 will retain its charge for a short period of time, perhaps on the order of milliseconds. This occurs due to the depletion region that forms at the PN junctions of the cell.
• the PN junctions will, because of the stored minority-injected charge, be brought into reverse bias, accentuating the depletion regions and their capacitance.
• This depletion region capacitance stores the minority-injected charge, at least until these minority carrier recombine in the substrate 25. Due to such recombination effects, the thyristor, when used as a cell, may need to be refreshed not unlike a standard DRAM cell.
• an operating voltage can be placed across the thyristor, and its current monitored to determiner whether the cell had been programmed to a logic '1' (high current) or a logic '0' (low current) state.
• Vgate small gate voltage
• Figure 4 shows how the disclosed cells 10 can be situated in a memory array 50
• Figure 5 illustrates the various voltages that can be used to write a logic '1' or O', to read the cell, and to hold data in the cell.
• the array 50 comprises, in one embodiment, bit lines 14 running orthogonally to the enable gates 16 and the word lines 12, but this is merely arbitrary.
• drivers 30, 32, and 34 are used to respectively drive desired voltages to the bit lines, enable gates, and word lines.
• the bit line driver 30 comprises a sense amplifier which is active when detecting the current/voltage on an active bit line.
• Such driving and sensing circuits are well known in the art of memory chip design, and could comprise any number of suitable circuits.
• Figure 5 illustrates exemplary voltages that can be used to write, read, and hold the programmed data in the cells 10, and thus comprise the voltages which the drivers 30, 32, 34 will generate under control of an appropriate and typical control circuit (not shown).
• the enable gate 16 when writing to the cell, the enable gate 16 is preferably held to ground, but otherwise is held at a negative potential (e.g., -1.0V), an accumulation condition in the P-channel portion of the thyristor 20.
• a negative potential e.g., -1.0V
• Vcc 1.5V
• the sense amps 30 detect as a logic '1.
• the data in the cells can be held by holding the word lines and bit lines at Vcc (e.g., 1.5V).
• Figure 6A shows two adjacent cells 10 in cross section at an intermediate stage of manufacture. At this stage, several standard processing steps have been performed, and are therefore only briefly summarized.
• a trench 40 has been etched in the P substrate 25.
• material is deposited for the conductive plug 22, which as noted above will ultimately connect to the enable gate 16.
• conductive plug 22 can comprise doped polysilicon, but could comprise other conductive materials used also for substrate plugs, such as tungsten, titanium, suicides, salicides, etc.
• the surface of the substrate 25 can be planar ized, such as by Chemical-Mechanical Planarization (CMP) or other known planarization techniques.
• CMP Chemical-Mechanical Planarization
• trench isolation structures 24 are formed around each cell to prevent cross talk between adjacent cells.
• the formation of trench isolation comprises forming a trench 41 in the silicon, filling the trench with a dielectric (e.g., an oxide or nitride), and planarizing the resulting structure.
• a dielectric e.g., an oxide or nitride
• the formation of trench isolation structures 24 can also precede the formation of the recessed conductive plug 22, or can be partially concurrent with the formation of the plug, for example, by forming the plug trenches 40 and isolation trenches 41 simultaneously. In any event, the fabrication steps as so far disclosed can occur in many different manners using well known processes.
• the N regions of the thyristor 20 are formed. Forming such regions can comprise a blanket ion implantation in the array of a suitable N-type dopant (e.g., phosphorous or arsenic). As one skilled in the art will appreciate, implantation into the conductive plug 22 and isolation structures 24 will not affect those structures.
• a suitable N-type dopant e.g., phosphorous or arsenic
• a hard mask 43 is deposited, patterned (e.g., with photoresist; not shown), and etched to cover the cathode (i.e., bit line) portions of the thyristor 20.
• the hard mask 43 can comprise any material suitable as an ion implantation mask, such as nitride. Alignment of the hard mask 43 is eased by the lateral dimensions of the top of the conductive plug 22, and hence this masking step can be performed without strict tolerance.
• the P regions can be formed using a blanket ion implantation in the array of a suitable P-type dopant (e.g., boron), with the hard mask protecting the N-regions at the cathodes.
• a suitable P-type dopant e.g., boron
• the P doping in this example occurs in a formerly doped N region.
• the N regions under the newly-implanted P regions are driven downward into the substrate by the "emitter push effect," which is well known and hence not further discussed.
• the newly-implanted P anode region can be implanted at a shallow depth without need to rely on the emitter push effect.
• the hard mask 43 is removed, and standard processing can be used to form the enable gates 16, the word lines 12, and the bit lines 14 into dielectric layers 26 (e.g., oxides), as shown in Figure 6D.
• the exposed tops of the anode and cathode regions of the thyristor 20 can optionally be suicided 31, as shown in Figure 6D.
• Such silicidation 31 creates a Schottky barrier, i.e., a potential barrier created at the interface between a metal suicide and a doped semiconductor region.
• the electrical performance of this barrier can be tailored. Because the charge injected into the source and drain depends on this potential barrier, silicidation offers additional options in designing the thyristor characteristics.
• Figures 7A-7C disclose a process for fabricating the recessed cell 10 in which the thyristor is formed in part using epitaxially grown silicon.
• a pad material 50 such as a nitride
• a trench 40 is drilled through the pad 50 and the substrate.
• the trench can then be filled with gate oxide 27 and a conductive plug 22 as described earlier.
• the pad 50 is removed.
• the N regions of the thyristor 20 are formed on the surface of the substrate 25, as shown in Figure 7C. This could be accomplished by ion implantation, or the N regions could be epitaxially grown.
• a hard mask 52 is formed over the cathode (i.e., bit line) portions of the thyristor 20. This allows the P anode (i.e., word line) to be epitaxially grown on the exposed N region, at which point the thyristor 20 is fully formed.
• the hard mask 52 is removed, and processing continues to form the word lines, enable gates, and bit lines as discussed above.
• suitable epitaxial growth processes are well known in the art, and hence are not further discussed.
• isolation under the recessed thyristor-based cell 10 can improve its performance, and particularly can improve its data retention and lengthen the time needed between refreshes. Accordingly, subsequent embodiments disclose ways in which such isolation can be effectuated.
• the P-doped base of the thyristor (25) is formed within an N substrate 62.
• the N-substrate 62 be biased to a high voltage (e.g., to the power supply voltage, Vcc) to ensure that the diode formed between the thyristor base 25 and the N substrate 62 will not be forward biased and hence will be isolated.
• a contact to the N-substrate 62 can be used to provide the appropriate bias, although not shown in the cross section.
• a P substrate 66 is used, but isolation is formed underneath the base by forming an N well 64, and within that well 64, the P base 25 is formed.
• the N well 64 would preferably be biased to a high voltage to provide isolation with respect to the P substrate 66 (typically grounded) and the P base 25 of the thyristor 20, although again the contact to establish such a bias is not shown.
• FIG. 9 Another means for improved isolation of the thyristor is shown in Figure 9, in which the cell 10 is formed using a buried oxide layer (Box 70).
• Box 70 be rich in a P dopant, such as boron, so that P dopants from the base 25 do not diffuse to the Box layer 70 and negatively affect thyristor 20 performance.
• P dopant such as boron
• the Box layer 70 is akin to use of the bulk insulator of an SOI (silicon on insulator) substrate, which would have similar performance to the embodiment shown in Figure 9, and which comprises yet another embodiment of the disclosed cell.
• Figure 10 illustrates another embodiment of the recessed thyristor-based cell 10 having improved isolation under the cell.
• the isolation structures 75 include undercuts 76, which as their name suggests undercut the thyristor 20 in significant part and assists in its isolation.
• the undercuts 76 can be formed by first creating an anisotropic trench (e.g., trench 41 of Figure 6A), and then subjecting the trench to a wet etch after the trench has been formed.
• TMAH Tetra-Methyl Ammonium Hydroxide
• the trench and undercut 76 can be filled using a low-pressure oxide vapor deposition process, as is well known, to form the undercutting isolation structures 75 as shown in Figure 10.
• the recessed thyristor-based cell 10 results in a cell design that is compact, easy to manufacture, and easy to form into an array of cells.
• the disclosed cells can exhibit improved cell densities when compared to traditional DRAM cells.
• the disclosed cell 10 would have particular applicability in embedded DRAM applications, in which volatile cells (requiring refresh) are incorporated into otherwise standard semiconductor chips, such as microprocessors or microcontrollers.
• thyristor 20 as used in the disclosed cell 10 is disclosed as being a PNPN structure, one skilled in the art will realize that a NPNP structure could be used as well. In such a structure, electrons instead of holes will comprise the majority carriers, but the cell will work equally well assuming that the potentials presented to the cell nodes are of opposite polarity. The ability to use thyristors of differing polarities provides design flexibility, particularly when considering use of the disclosed cell 10 in an embedded application.
• anode and “cathode” refer merely to the end node terminals of the thyristor, and accordingly that it is irrelevant which of these terminals actually sinks or sources current. Thus, these terms should be understood as interchangeably throughout this disclosure and the claims.

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• Engineering & Computer Science (AREA)
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• General Physics & Mathematics (AREA)
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• Semiconductor Memories (AREA)
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