Classifications

• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
  • H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/54—Apparatus specially adapted for continuous coating
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02041—Cleaning
  • H01L21/02057—Cleaning during device manufacture
  • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
  • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
  • H01L21/28562—Selective deposition
• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
  • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
  • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
  • H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76846—Layer combinations
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
  • H01L21/76855—After-treatment introducing at least one additional element into the layer
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
  • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
  • H01L21/76864—Thermal treatment

Definitions

• the present invention relates to a substrate processing apparatus, a substrate processing method, a program, and a recording in which the program is recorded, for performing a substrate processing for forming an alloy film such as a metal silicide film on a Si-containing surface such as a Si substrate or a metal silicide layer. It relates to the medium.
• CMOS transistors have connection structures such as a wiring layer and a substrate and a wiring layer and a wiring layer.
• connection structures such as a wiring layer and a substrate and a wiring layer and a wiring layer.
• CMOS transistors have connection structures such as a wiring layer and a substrate and a wiring layer and a wiring layer.
• a contact hole 20 connected to the Zn impurity diffusion layer (diffusion layer) 10 of the Si substrate (Si wafer) 20 and a via hole 30 connecting the upper and lower wiring layers.
• Such contacts 20 and via holes 30 are filled with metals such as tungsten and copper, and the Si substrate and wiring layer are electrically connected.
• a noria film such as a TiN film or a TiZTiN multilayer film is formed on the contact 20 and the via hole 30 to form the noria layers 22 and 32.
• the aspect ratio which is the ratio between the diameter and the depth of contact holes, is becoming extremely large.
• the CVD (chemical vapor deposition) method with good step coverage is used to form barrier layers such as the TiN film described above.
• a material layer such as TiSi (titanium silicide) is interposed between the barrier layer 22 and the diffusion layer 10 and the It is desirable to lower the Schottky barrier based on the work function difference by adjusting the work function at the interface with the diffusion layer 10.
• CVD-Ti is also used to form such a material layer, for example, the TiSi film 12.
• TiSi film 12 TiCl is used as the source gas and the reducing gas is used.
• a Ti film is formed at a temperature of about 650 ° C.
• the TiSi film 12 was formed in a self-aligned manner.
• a metal film forming process such as barrier layer formation
• a base surface (underlying the metal film) prior to the metal film forming process For example, a natural oxide film existing on the bottom surface of the contact hole) is removed to remove foreign substances such as etching residues introduced during the formation of the contact hole.
• Patent Document 1 Japanese Patent Laid-Open No. 2002-124485
• Patent Document 2 Japanese Patent Laid-Open No. 2001-244214
• Non-patent document 1 T. Teraji and S. Hara, ontroi of interface states atmetal / 6H-Si (000 l) interfaces ", Phys. Rev. B70, 035312 (2004).
• the depth of the impurity diffusion layer 10 becomes shallower and the aspect ratio of the contact hole 20 tends to become larger.
• the bottom of the contact hole is sufficiently removed.
• the shallow diffusion layer may be damaged by ion bombardment, or the shoulder of the contact hole opening may be scraped off and the insulating material will adhere to the bottom of the contact hole again. Sometimes it does.
• a backing technology that covers the diffusion layer with a metal silicide film such as CoSi or NiSi is used to compensate for the high resistance of the shallow diffusion layer before the contact hole is formed.
• the backing layer made of these metal silicide films contains Si, so when exposed to the atmosphere, a natural oxide film grows on the surface of the backing layer.
• the alloy film eg, Ti-Co film, Ti-Ni film, etc.
• the alloy film formed by the alloying reaction between the metal deposited on the backing layer and the backing layer be alloyed uniformly. .
• the present invention has been made in view of such problems, and an object of the present invention is to make the interface between the substrate and the silicon-containing surface exposed in the substrate to be processed (eg, Si substrate) flatter. It is an object of the present invention to provide a substrate processing apparatus and the like that can form a (flat) and uniform alloy film and thereby can form an outer structure with a lower resistance.
• a plurality of processing chambers for performing predetermined processing on a substrate to be processed a common transfer chamber connected in common to these processing chambers, ,
• a substrate processing apparatus having a vacuum processing apparatus provided with a transfer mechanism for transferring the substrate to be processed provided in the common transfer chamber, wherein the plurality of processing chambers are exposed to silicon in the substrate to be processed
• a foreign matter removal treatment chamber for removing foreign matter on the contained surface, and a metal for forming a metal film on the silicon-containing surface from which the foreign matter has been removed by supplying a metal-containing source gas to the substrate to be treated.
• a substrate processing process comprising: a film forming process chamber; and an alloying process chamber for forming an alloy film by heat-treating the substrate to be processed to cause a reaction between the metal film and the silicon-containing surface.
• the foreign matter removal processing chamber supplies an excitation gas onto the substrate to be processed, and causes a chemical reaction between the foreign matter on the silicon-containing surface and the gas component of the excitation gas.
• the alloy film is, for example, a metal silicide film, and the alloying chamber forms a metal silicide film by causing a reaction between the metal film and the silicon-containing surface by, for example, heat-treating the substrate to be processed. This is a silicide formation processing chamber.
• the metal film deposition processing chamber performs the metal film deposition process within a temperature range (for example, less than 580 ° C.) without forming a silicide phase of the metal film. It is preferable that the processing chamber perform the heat treatment of the metal film in a temperature range (for example, 580 ° C. or more) at which a silicide phase of the metal film is formed.
• the foreign matter removal treatment step an excitation gas is supplied onto the substrate to be processed, and the foreign matter on the silicon-containing surface is chemically reacted with the gas component of the excitation gas.
• a product generation processing step for generating a composition and a product removal processing step for sublimating and removing the product on the silicon-containing surface by heat-treating the substrate to be processed are continuously performed.
• the alloy film is, for example, a metal silicide film, and the alloying step includes, for example, heat-treating the substrate to be processed to cause a reaction between the metal film and the silicon-containing surface. This is a silicidation process step for forming the film.
• the metal film forming process and the silicide forming process can be continuously performed after the foreign substance removing process in the substrate processing apparatus. It is possible to prevent a natural oxide film from being newly formed on the silicon-containing portion of the substrate to be processed before the metal film forming process. In this way, the foreign matter on the silicon-containing surface exposed on the substrate to be processed can be reliably removed, and the uniform alloying (eg silicidation) of the metal film is hindered by the foreign matter on the silicon-containing surface. Therefore, a metal silicide film with a flat (flat) interface with the substrate can be formed on the silicon-containing surface. As a result, a contact structure with lower resistance can be formed.
• the metal film forming process includes a step of supplying the metal-containing source gas on the substrate to be processed to cause an adsorption reaction of the metal film on the silicon-containing surface, and a reducing gas.
• the metal film is formed by repeating the step of supplying and reducing the metal film adsorbed on the silicon-containing surface a plurality of times.
• the foreign matter removal process continuously allows no foreign matter on the silicon-containing surface of the substrate to be processed. For example, since an ALD-Ti film deposition process can be performed, a flatter and more uniform film can be formed by depositing a Ti film while controlling the atomic arrangement by this ALD-Ti film deposition process.
• the substrate to be processed is heat-treated to cause a silicidation reaction between the Ti film and the underlying silicon
• the film thickness uniformity of the Ti silicide film with respect to the silicon-containing surface can be controlled at the atomic level.
• the ALD-Ti film deposition process allows the Ti film thickness to be freely controlled at the atomic level, which in turn allows the Ti silicide film (titanium silicide film) thickness to be freely controlled.
• a plurality of processing chambers for performing predetermined processing on a substrate to be processed a common transfer chamber connected in common to these processing chambers, ,
• a substrate processing apparatus having a vacuum processing apparatus provided with a transport mechanism for transporting the target substrate provided in the common transport chamber, wherein the plurality of processing chambers are disposed on the target substrate.
• a product generation process for generating a product by supplying an excitation gas to the substrate and causing a chemical reaction between a foreign substance on the silicon-containing surface exposed to the substrate to be processed and a gas component of the excitation gas.
• the second metal film deposition process can be continuously performed in the substrate processing apparatus without exposing the substrate to be processed to the atmosphere.
• the adhesion of the second metal film can be further improved and the strength can be further improved.
• a plurality of processing chambers for performing a predetermined process on a substrate to be processed a common transfer chamber connected in common to these processing chambers, ,
• a substrate processing apparatus having a vacuum processing apparatus provided with a transport mechanism for transporting the target substrate provided in the common transport chamber, wherein the plurality of processing chambers are disposed on the target substrate.
• a product generation process for generating a product by supplying an excitation gas to the substrate and causing a chemical reaction between a foreign substance on the silicon-containing surface exposed to the substrate to be processed and a gas component of the excitation gas.
• a substrate processing apparatus is provided.
• a plurality of processing chambers for performing a predetermined process on a substrate to be processed a common transfer chamber commonly connected to these processing chambers, ,
• a substrate processing apparatus having a vacuum processing apparatus provided with a transport mechanism for transporting the target substrate provided in the common transport chamber, wherein the plurality of processing chambers are disposed on the target substrate.
• a product generation process for generating a product by supplying an excitation gas to the substrate and causing a chemical reaction between a foreign substance on the silicon-containing surface exposed to the substrate to be processed and a gas component of the excitation gas.
• a plurality of processing chambers for performing a predetermined process on a substrate to be processed a common transfer chamber connected in common to these processing chambers, ,
• a substrate processing apparatus having a vacuum processing apparatus provided with a transport mechanism for transporting the target substrate provided in the common transport chamber, wherein the plurality of processing chambers are disposed on the target substrate.
• a product generation process for generating a product by supplying an excitation gas to the substrate and causing a chemical reaction between a foreign substance on the silicon-containing surface exposed to the substrate to be processed and a gas component of the excitation gas.
• a Ti film deposition chamber and a C49 phase Ti silicide film are formed by heat-treating the substrate to be treated to cause a silicidation reaction between the Ti film and the silicon-containing surface.
• a Ti treatment film containing the Ti film and the silicon There is provided a substrate processing apparatus characterized by including a C54 phase silicide formation processing chamber for forming a C54 phase Ti silicide film by causing a silica reaction with the surface.
• a substrate processing method for a substrate processing apparatus for forming a metal silicide film on a silicon-containing surface of a substrate to be processed A product generation process for generating a product by supplying an excitation gas onto the substrate and causing a chemical reaction between the foreign substance on the silicon-containing surface exposed to the substrate to be processed and the gas component of the excitation gas.
• a metal silicide film eg, titanium silicide film having a crystal structure (desired specific resistance) of a desired silicide phase (eg, C49 phase, C54 phase).
• a desired silicide phase eg, C49 phase, C54 phase.
• a program for executing a substrate processing method of a substrate processing apparatus for forming a metal silicide film on a silicon-containing surface of a substrate to be processed is stored.
• this recording medium an excitation gas is supplied to the substrate to be processed, and a foreign substance on the silicon-containing surface exposed to the substrate to be processed and a gas component of the excitation gas are transferred to the computer.
• a metal-containing source gas is supplied onto the substrate to be processed, and a metal film is formed on the silicon-containing surface from which the foreign matter has been removed.
• Shirisa of forming a metal silicide film There is provided a computer-readable recording medium on which a program for continuously executing an id forming step is executed in the substrate processing apparatus.
• foreign matter removal processing product generation processing, product removal processing
• metal film formation processing metal film formation processing
• silicide formation processing are continuously performed, so that the substrate is processed. Since the metal film and silicide can be formed in a state in which the foreign matter on the exposed silicon-containing surface is reliably removed, the interface with the base is more flat and uniform on the silicon-containing surface. A metal silicide film can be formed.
• the substrate processing apparatus may include a plurality of the vacuum processing apparatuses, and each of the vacuum processing apparatuses may be connected to each other through a path unit.
• the alloys in this specification include silicides (silicides) formed by reacting a deposited metal (eg, Ti) and an underlying layer (eg, silicon), and deposited metals (eg, Ti) and their Also included are alloys (eg, Ti—Co, Ti—Ni, etc.) formed by reacting with the underlying metal (eg, metal silicide film).
• the foreign matter in this specification includes, for example, contamination such as etching residue, particles, and natural oxide film.
• the silicon-containing surface of the substrate to be processed is bonded to the substrate. It is possible to form a uniform metal silicide film with a flatter (flat) interface, which makes it possible to form a contact structure with even lower resistance.
• FIG. 1 is a cross-sectional view showing a configuration example of a substrate processing apparatus according to a first embodiment of the present invention.
• FIG. 2 is a schematic diagram showing a specific example of the film structure of the Si wafer in the same embodiment.
• FIG. 3A is a process diagram for describing wafer processing according to the embodiment.
• FIG. 3B is a process diagram for describing wafer processing according to the embodiment.
• FIG. 3D is a process diagram for describing wafer processing according to the embodiment.
• FIG. 4B is an enlarged schematic view of the film structure of the bottom part (A part) of the contact hole in each step shown in FIG. 3B.
• FIG. 4C is a schematic diagram enlarging the film structure of the bottom part (A part) of the contact hole in each step shown in FIG. 3C.
• FIG. 5A is an enlarged schematic view of the film structure at the bottom (A part) of a contact hole in a comparative example.
• FIG. 7 is a diagram showing an example of a gas supply mode in a CVD-Ti film forming process as a specific example of the Ti film forming process.
• FIG. 8 is a diagram showing an example of a gas supply mode in the ALD-Ti film forming process as a specific example of the Ti film forming process.
• FIG. 9 is a diagram showing another example of the gas supply mode in the ALD-Ti film forming process as a specific example of the Ti film forming process.
• FIG.10 Gas supply mode in ALD-Ti film deposition process as a specific example of Ti film deposition process It is a figure which shows other example of these.
• FIG. 11 A diagram showing an example of a gas supply mode in the SFD-Ti film forming process as a specific example of the Ti film forming process.
• FIG. 12 A graph showing the relationship between the set temperature of the Ti film when heat-treating the Ti film on the Si surface of the Si wafer, the specific resistance of the Ti silicide, and the uniformity of this specific resistance within the wafer surface.
• FIG. 14 is a cross-sectional view showing a configuration example of a COR processing chamber that works on the same embodiment.
• FIG. 16 is a cross-sectional view showing a configuration example of a Ti film deposition processing chamber according to the embodiment.
• FIG. 20 is a block diagram showing a configuration example of an EC (apparatus control unit) in the same embodiment.
• FIG. 21 is a view showing a scanning electron microscope (SEM) photograph of a cross-section of a Ti film formed by a wafer process emphasizing this embodiment.
• SEM scanning electron microscope
• FIG. 22 is a view showing a scanning electron microscope (SEM) photograph of a cross section of a C49 phase Ti silicide film (Ti Si film) formed by wafer processing according to the present embodiment.
• FIG. 2 is a view showing a scanning electron microscope (SEM) photograph 2;
• FIG. 29 is a diagram showing a configuration example of a processing chamber in the substrate processing apparatus shown in FIG. 28.
• FIG. 30 is a schematic diagram showing a wiring structure of a semiconductor device.
• the growth time of the natural oxide film with a thickness of 3 angstroms is approximately 10 minutes, whereas the Si wafer is subjected to COR treatment.
• the growth time of the 3 ⁇ thick natural oxide film is approximately 2 hours or more. Therefore, in the cleaning process using the COR process and the PHT process, a new watermark is not generated, and the growth of the natural oxide film over time after the cleaning process is suppressed. Can be improved.
• the reaction proceeds in a dry environment. Specifically, water is not used for the reaction in the COR process. Even if water molecules are generated by the COR process, the COR process is performed in a vacuum, so the water molecules are generated in a gas state. Therefore, since water molecules do not adhere to the Si wafer in the liquid state, no water mark or the like is generated on the surface of the Si wafer. In addition, since the PHT treatment is performed at high temperatures, no watermarks are generated on the surface of the Si wafer, and no OH groups are placed on the exposed Si surface of the Si wafer. Therefore, since the surface of the Si wafer is not passivated and becomes hydrophilic, the surface of the Si wafer does not absorb moisture, thus preventing a decrease in wiring reliability of the semiconductor device. Can do.
• the amount of product (complex) produced relaxes after a predetermined time. Specifically, after a certain period of time has passed, even if the watermark continues to be exposed to a mixture of ammonia gas and hydrogen fluoride gas, the amount of product produced does not increase.
• the amount of product produced is determined by the gas mixture parameters such as the gas pressure and volumetric flow ratio. Therefore, the amount of watermark removal can be controlled easily.
• the foreign substance removal process without using plasma is performed as a pre-process, the surface of the diffusion layer of the Si substrate is not damaged by the plasma, so the uniformity of the TiSi crystal of the Ti silicide film A contact structure with lower resistance can be formed.
• the film formation rate in the temperature range of 580 ° C. or higher is higher than the film formation rate in the temperature range near 500 ° C. to 550 ° C. I understand. This is because a silicidation reaction between the Ti film and its underlying layer (Si) occurs in the temperature range above 580 ° C, and more stable silicide phases (eg, C49 and C54 phases of TiSi) are formed. Inferred for
• a silicide phase (eg TiSi C49 phase, C54 phase) is formed.
• the Ti film forming process by setting the process temperature (here, the temperature of the Si wafer) within a temperature range of less than 580 ° C. For example, it is more preferable to set the temperature to 565 ° C. As a result, a Ti film can be deposited without causing a silicidation reaction with the substrate (Si).
• the film formation process is performed to form a Ti film by supplying the plasma and generating plasma at the same time. Then, if necessary, NH gas supply, Ar gas supply, H gas supply, plasma generation, etc. are performed in order to improve adhesion when forming a TiN film in the TiN film formation process described later. At the same time
• a nitridation process is performed to nitride the Ti film surface.
• the process temperature (Si wafer temperature) is set to a temperature range lower than 650 ° C. and lower than 580 ° C.
• the silicide phase of the Ti film eg, C49 phase and C54 phase of TiSi
• a Ti film is formed by repeating an adsorption process that causes an adsorption reaction (a reaction between Ti and Si) and a reduction process that reduces the Ti film adsorbed on the silicon-containing surface by supplying a reducing gas. It is also possible to perform a Ti film deposition process, such as an ALD-Ti film deposition process using atomic layer deposition (ALD). In this case as well, the process temperature (Si wafer temperature) is set to a temperature range below 580 ° C.
• the Ti film is formed repeatedly by separating the Ti film adsorption process and the reduction process, thereby reducing impurities in the film. This stabilizes the silicidation reaction. This makes it possible to form a uniform Ti film with a flatter interface with the base (Si).
• a foreign substance such as a natural oxide film is adhered to the Si surface of the Si wafer by the foreign substance removal process by the COR process and the PHT process.
• the Ti film can be deposited while the atomic arrangement is controlled by the Ti film deposition process, so a flatter and more uniform film can be formed.
• a Ti silicide film is formed by heat treatment to cause a silicidation reaction, so that the film thickness uniformity of the Ti silicide film with respect to the underlying layer (Si) can be controlled at the atomic level.
• the ALD-Ti film deposition process allows the Ti film thickness to be freely controlled at the atomic level, so that the Ti silicide film thickness can also be freely controlled.
• FIG. 8 A specific example of such an ALD-Ti film forming process is shown in FIG. In the process shown in Fig. 8, first, TiCl gas is supplied for a short time to cause an adsorption reaction, and then Ar gas is supplied and H gas is supplied.
• a film forming process is performed in which a Ti film is formed by repeating the process of supplying and reducing plasma by generating a plasma multiple times. Also in this case, after that, supply of NH gas, if necessary
• Fig. 9 shows another example of the ALD-Ti film deposition process.
• TiCl gas supply, H gas supply, Ar gas supply, and plasma generation are performed at the same time.
• a nitriding step is performed.
• the Ti film is formed by plasma-enhanced SFD (Sequential Flow) at a temperature lower than 580 ° C, set to 400 ° C to 450 ° C.
• Deposition —Ti film forming process may be executed.
• the SFD-Ti film deposition process is shown in Fig. 11, for example. First, supply TiCl gas, Ar gas, H gas, and plasma generation.
• a film forming step for forming a film is performed. Also in this case, after that, if necessary, supply of NH gas and
• a nitriding process is performed in which Ar gas supply, H gas supply and plasma generation occur simultaneously.
• the Ti silicide formation process according to the first embodiment it is preferable to set the process temperature within the temperature range in which the silicon reaction between the Ti film 166 and its base (Si) occurs.
• the temperature range in which the silicidation reaction between the Ti film 166 and its base (Si) occurs is the temperature range in which the Ti silicide crystal structure is formed by causing the silicidation reaction of the Ti film, Specifically, a more stable silicide phase of Ti film (eg, TiSi metastable C49 phase, stable C54 phase) is formed
• Figure 12 shows the relationship between the set temperature of the wafer when the Ti film on the Si surface of the Si wafer is heat-treated, the specific resistance of Ti silicide (eg, TiSi), and the uniformity of this specific resistance within the wafer surface.
• Ti silicide eg, TiSi
• the graph of the in-plane uniformity of resistivity shown in Fig. 12 shows the in-plane distribution of the crystal structure of Ti silicide. For example, in the vicinity of 630 ° C, the C49 phase and the C54 phase are mixed together, and the in-plane uniformity of the resistivity will be high. Therefore, an in-plane distribution is likely to occur. [0097] According to the graph shown in Fig.
• a stable silicide can be obtained by setting the process temperature (here, the temperature of the Si wafer) in a temperature range of 640 ° C to 650 ° C (preferably 650 ° C) and performing Ti silicide formation.
• a Ti silicide film with a lower resistance and a C54 phase crystal structure is formed.
• a Ti silicide film with the desired crystal structure can be formed by changing the process temperature setting during the heat treatment.
• the process temperature is set to a temperature range of 640 ° C to 650 ° C.
• a C54 phase Ti silicide film may be formed at once, but it may also be formed by a two-stage annealing process that performs heat treatment in two stages. That is, first, the C49 phase Ti silicide film is formed by performing heat treatment with the process temperature set in the temperature range of 590 ° C to 610 ° C (eg 600 ° C) (first annealing treatment).
• a C54 phase Ti silicide film may be formed by performing a phase transition by performing a heat treatment at a process temperature of 640 ° C to 650 ° C (eg, 650 ° C). This makes it possible to form a C54 phase Ti silicide film more stably.
• the substrate processing apparatus 100 includes a foreign matter removal process for removing foreign matters such as a natural oxide film on a Si wafer without using water components and without using a plasma, and the Si surface of the Si wafer subjected to the foreign matter removal process.
• a first metal film for example, a Ti film
• the first metal silicide film for example, a Ti silicide film
• a metal silicide film forming process eg, Ti silicide film forming process
• a second metal film forming process TiN film forming process
• a second metal film eg, TiN film
• the processing chambers 104A to 104F are configured as a foreign substance removal processing chamber, a first metal silicide film formation processing chamber, and a second metal film deposition processing chamber, respectively.
• the foreign substance removal process is a two-stage process consisting of a product generation process (for example, COR process) and a product removal process (for example, PHT process). It may consist of two processing chambers.
• the first metal silicide film forming process includes a first metal film forming process (for example, a Ti film forming process) for forming a first metal film (for example, a Ti film), and the first metal film forming process.
• a first metal film forming process for example, a Ti film forming process
• the first metal film deposition process chamber You may comprise two process chambers of a formation process chamber.
• the configuration of each of the processing chambers 104A to 104F is determined according to the processing content executed by the substrate processing apparatus 100.
• a Si wafer W having contact holes formed therein is introduced into the substrate processing apparatus 100, and the COR processing and the PHT processing as the foreign matter removal processing as described above are continuously performed on the Si wafer W.
• Figure 13 shows an example of the configuration of the processing chamber in the substrate processing apparatus 100 when the Ti film formation process, Ti silicide formation process, and TiN film formation process are executed successively.
• the processing chambers 104A, 104B, and 104C connected to the first common transfer chamber 102 are respectively formed as a Ti film deposition processing chamber, a TiN film deposition processing chamber, and a Ti silicide formation processing chamber.
• the processing chambers 104E and 104F connected to the second common transfer chamber 120 are configured as a COR processing chamber and a PHT processing chamber, respectively. Processing in each of the processing chambers 104A to 104C, 104E, and 104F is executed based on a process processing program 364 stored in program data storage means 360 provided in an EC (equipment control unit) 300 of the control unit 200 described later. Is done.
• the COR processing chamber is constituted by an excited gas reaction processing chamber 400 as shown in FIG.
• This excitation gas reaction processing chamber 400 has a substantially cylindrical processing chamber 411 that is hermetically configured to accommodate the Si wafer W, and a susceptor 412 for horizontally supporting the wafer W is included therein. Is arranged.
• the susceptor 412 is provided with three wafer support pins (not shown) for supporting the wafer W so as to be lifted and lowered relative to the surface of the susceptor 412.
• the wafer support pin and its lifting mechanism are configured in the same way as shown in the plasma CVD processing chamber (Ti film deposition processing chamber) 600 (see Fig. 16), which will be described later.
• a shower head 420 is provided on the top wall 411 a of the processing chamber 411.
• the shower head 420 has a two-layer structure of an upper layer portion 421 and a lower layer portion 422.
• the lower layer portion 421 and the upper layer portion 422 have a first buffer space 423 and a second buffer space 424, respectively. .
• the upper surface of the upper layer part 421 is closed with a lid member 425, and NH gas is introduced into the lid member 425.
• the NH gas inlet 426 is connected to the first buffer space 423, where HF gas is introduced.
• the part 427 is connected to the second buffer space 424 via a gas introduction path 427a. Then, NH gas discharge holes 428 for discharging NH gas downward from the first buffer space 423, and
• HF gas discharge holes 429 for discharging HF gas downward from the second buffer space 424 are formed.
• the NH gas supply section 426 has an NH gas supply source 432 force S through an NH gas line 430. Connected to this NH gas supply source 432 through NH gas line 430
• the HF gas inlet 427 has an HF gas line.
• An exhaust pipe 436 is connected to the bottom wall of the processing chamber 411, and an exhaust device 437 including a vacuum pump is connected to the exhaust pipe 436. Then, by operating the exhaust device 437, the inside of the processing chamber 411 can be decompressed to a predetermined degree of vacuum.
• a gate valve G is provided on the side wall of the processing chamber 411, and the Si wafer W is transferred to the adjacent second common transfer chamber 120 with the gate valve G opened. It is like this.
• the processing chamber 411 is evacuated by the exhaust device 437 to a predetermined reduced pressure state, the gate valve G is opened, 2 Si wafer W is inserted into the processing chamber 411 from the first common transfer chamber 102 in a vacuum state by the transfer mechanism 124 and placed on the susceptor 412. Then, close the gate valve G.
• the temperature of the Si wafer W is kept at a predetermined temperature.
• the gate valve G is opened, and the Si wafer W is unloaded to the second common transfer chamber 120 by the second transfer mechanism 124. After that, the Si wafer W is loaded into the PHT processing chamber and heat treated, so that the above reaction components decompose and volatilize, and a natural oxide film is formed. Is removed.
• the processing conditions in this excited gas reaction processing chamber 400 are, for example, a pressure of 0.67 to 133.3 Pa, a wafer temperature of 10 to 30 ° C, a gas flow rate of NH: 10 to 80 mLZmin, HF: 10
• the PHT treatment chamber is composed of a heat treatment chamber 500 as shown in Fig. 15, for example.
• This heat treatment chamber 500 has a substantially cylindrical processing chamber 511 that is hermetically configured to accommodate the wafer W, and a heating plate 512 for placing and heating the Si wafer W in the processing chamber 511. Is provided.
• N gas as an inert gas from the N gas supply source 518 through a gas line 517
• H gas from H gas supply source 634 is combined with Ar gas from second Ar gas supply source 636.
• H gas and Ar gas are supplied to the gas inlet 622, and the gas discharge holes are 627 and 628, respectively.
• the supply of Ar gas is stopped, the inside of the processing chamber 611 is rapidly evacuated by the exhaust device 648, and the gate valve G is opened. Then, the Si wafer W is loaded into the processing chamber 611 from the first common transfer chamber 102 in a vacuum state via the loading / unloading port 652, and the Si wafer W is placed on the susceptor 612.
• the flow is carried out for 15 seconds, for example.
• the frequency of the high frequency power source 644 is preferably 300 to 2000 W, for example, 800 W.
• TiCl gas was treated in the processing chamber 611 while maintaining the same gas flow rate, pressure, and high-frequency power.
• a thick Ti film is deposited.
• the heating temperature of the Si wafer W when forming the Ti film is within a range where no silica reaction occurs between the Ti film and the underlying Si surface, for example, below 580 ° C. This is the best setting. In this way, a thin Ti film is formed on the Si surface while suppressing the silicidation reaction.
• Gas is allowed to flow for a predetermined time at a flow rate of preferably 0 '5 to 3 LZmin, for example 1.5 LZmin.
• the high frequency power is supplied from the high frequency power supply 644 to the shower head 620 while maintaining the supply of gas, Performed with a plasma of gas.
• power supply to the high-frequency power source 644 force shower head 620 is stopped, the gas flow rate and vacuum are gradually reduced, and the Ti film forming process is completed.
• the Si wafer W is carried into the Ti silicide formation chamber and heat-treated, causing a silicidation reaction between the Ti film and the Si surface, and a Ti silicide film is formed on the Si surface.
• the Ti film formation process and the Ti silicide formation process may be performed continuously by switching gases and turning on and off plasma generation in one Ti silicide film formation process chamber. In this case, efficient processing is possible and a Ti silicide formation chamber is not required.
• TiCl gas supply source 732 that supplies TiCl gas, which is a Ti compound gas, N gas
• Source 734 equipped with a second N gas supply source 735 for supplying N gas.
• a TiCl gas supply line 737 is connected to the gas supply source 732.
• the first N gas supply line 738 is connected to the 4 4 2 gas supply source 733, and the NH gas supply source 7
• each gas supply line is provided with a mass flow controller 742 and two valves 74 1 sandwiching the mass flow controller 742.
• the first gas inlet 621 of the showerhead 620 has a T extending from a TiCl gas supply source 732
• An iCl gas supply line 737 is connected to the TiCl gas supply line 737.
• a first N gas supply line 738 extending therethrough is connected.
• the second gas inlet 622 has an NH gas supply line extending from an NH gas supply source 734.
• the NH gas supply line 739 is connected to a second N gas supply source 73.
• a second N gas supply line 740 extending from 5 is connected.
• TiCl gas from the TiCl gas supply source 732 is mixed with the first N gas.
• the first gas guide population of 621 reaches the inside of the shower head 620 and is discharged from the discharge hole 627 into the processing chamber 611 through the gas passages 623 and 625.
• NH gas which is a nitriding gas from NH gas supply source 734, is the second N gas supply source 7
• the gas is discharged from the discharge hole 628 into the processing chamber 611 through the gas passages 624 and 626.
• the processing chamber 611 is preheated by the heater 615.
• a TiN film is precoated on the inner wall of the processing chamber 611, the inner wall of the exhaust chamber 646, and the surface with the processing chamber inside such as the shower head 620 by heating with the heater 615.
• the temperature change of Si and W can be made substantially constant.
• the film is de-C1 and the residual chlorine in the film can be reduced and the film can be stabilized.
• the inside of the processing chamber 611 is abruptly evacuated by the exhaust device 648 to bring it into a drawn state, the gate valve G is opened, and the first common transfer chamber 102 in the vacuum state is loaded by the first transfer mechanism 118 Wafer W is loaded into processing chamber 611 via outlet 652, and Si wafer W is placed on susceptor 612.
• the final flow rate of these gases is preferably N gas from the first N gas source 733 and the second N gas source 735.
• Each of 0'05 ⁇ 3LZmin, NH gas is preferably 0.005 ⁇ 0.3LZmin,
• the internal pressure is about 40-670Pa. Hold this state for a predetermined time, and preheat the wafer W at 300 to 500 ° C, for example. This preheating is performed for 30 seconds, for example. this In this case, the NH gas flow rate is heated at a partial pressure lower than that of N gas.
• Pre-flow is performed with TiCl gas preferably at a flow rate of 0.01 to 0.08 LZmin. This pre
• the flow is carried out for 15 seconds, for example.
• the first N gas supply source 733 and the second N gas supply source 735 receive purge gas and
• N gas is introduced into the processing chamber 611 and the processing chamber 611 is purged for 6 seconds, for example.
• Preflow is performed with the gas flow rate preferably set to 0.01 to 0.08 LZmin.
• the flow rate of N gas is reduced to, for example, 0.17LZmin, and the gas flow rate is stabilized.
• the N gas flow rate from the N gas supply source 735 is increased to, for example, lLZmin.
• the purge gas is introduced into the processing chamber 611 and the processing chamber 611 is purged. Thereafter, NH gas is transferred to the N gas from the second N gas supply source 735 and introduced into the processing chamber 611.
• the second step is annealing and nitriding of the TiN film with N gas and NH gas.
• This second step is carried out, for example, for 5 seconds.
• TiCl gas pre-flow to the second step are one cycle, multiple cycles,
• the gas is switched at this time by switching the nozzle. In this way, a TiN film with a predetermined thickness is formed.
• the heating temperature of the Si wafer W when forming the TiN film is preferably 300 to 500 ° C, for example about 450 ° C.
• Ti is produced by alternating gas flow in which the first step and the second step are alternately repeated.
• the TiN film formed in the first step can be efficiently removed by the annealing in the second step, and the residual chlorine in the film can be remarkably lowered. Even so, it is possible to form a high-quality TiN film with little residual chlorine and low specific resistance.
• the thickness of the TiN film is 3 to 50 nm, preferably 5 to 20 nm, a TiN film with low contact resistance and excellent barrier properties can be obtained.
• the unprocessed Si wafer W accommodated in the central introduction port 112B is transported to the orienter 114 as shown by the transport path X12 by the transport-side transport mechanism 116, where Si wafer, W After the alignment, the Si wafer W after the alignment is again stored in the other load lock chamber 108A as shown by the transfer path X13 by the transfer-side transfer mechanism 116 and kept waiting. The above operation is repeated every time the processing of the Si wafer W progresses.
• the transfer process of the Si wafer W in the first common transfer chamber 102 will be described.
• the processed Si wafer W accommodated in the processing chamber 104B is picked up by the first transfer mechanism 118, and is placed in the empty path section 122 as shown in the transfer path Yl1.
• control unit 200 shown in Fig. 19 multiple end devices are not directly connected to EC300, but the I / O units connected to the multiple end devices are modularized.
• This dredge module is connected to EC300 via MC and switching hub 220, so the communication system can be simplified.
• the switching hub 220 Since the control signal transmitted by the CPU 310 of the EC300 includes the address of the collar connected to the desired end device and the address of the module including the collar, the switching hub 220 Refers to the address of the module in the control signal, and the GHOST of the MC references the address of the module in the control signal, so that the switching hub 220 and MC need to inquire the CPU 310 about the destination of the control signal. As a result, smooth transmission of control signals can be realized.
• a foreign matter such as a natural oxide film adhering to the Si wafer is removed without using the plasma (for example, COR processing and P).
• a Ti film can be formed continuously without exposing the Si wafer to the atmosphere, and then Ti silicide can be formed continuously. A very flat and uniform Ti silicide film can be formed.
• the substrate processing apparatus 100 performed foreign matter removal processing by COR processing and PHT processing on the sample Si wafer surface.
• the ALD-Ti film formation process shown in Fig. 8 was continuously performed at a process temperature of 565 ° C to form a Ti film.
• Ar gas is supplied and H gas is supplied.
• a Ti film was formed by repeating the process of reducing by supplying 42 and supplying plasma.
• FIG. 21 shows a scanning electron microscope (SEM) photograph of the cross section of the sample at this time.
• the Ti film exposed on the Si wafer has a very flat, uniform, thin film with a very thin interface with the base (Si).
• a TiSi film is formed on the lower side of the Ti film. For example, TiSi or TiSi is formed, and TiSi, which is a more stable silicide phase, is formed.
• the Ti film thickness is 19. Onm, and the TiSi film thickness is 16.7 nm. Therefore, the total thickness of the Ti film and TiSi film is 35.7 nm.
• Ti silicide formation was continuously performed at a process temperature of 600 ° C to form a C49 phase Ti silicide film (TiSi film) by siliciding the Ti film.
• a Ti-film is formed at the same time as the Ti film is formed by performing CVD-Ti film processing at a process temperature of 650 ° C, which simultaneously supplies gas, Ar gas, and plasma. did.
• a SEM photograph of the cross section of the sample at this time is shown in FIG.
• the interface between the Ti silicide film formed by the wafer processing (substrate processing method) according to the first embodiment and the base (Si) is as follows. As shown in Fig. 22, it is very flat and uniform, and it can be seen that the state of the interface between the Ti silicide film and its base (Si) has been greatly improved.
• FIG. 25 shows an SEM photograph of the surface of the Ti silicide film. According to the wafer processing that is important for the first embodiment, a uniform Ti film with a very flat surface could be formed as shown in Fig. 25.
• the conventional CVD-Ti film deposition process supplies TiCl gas and H gas.
• the state of the interface and surface of the Ti silicide film is greatly improved as compared with the conventional case, and the resistance of the Ti silicide film can be further reduced.
• FIG. 28 is a schematic configuration diagram showing an example of a substrate processing apparatus according to the second embodiment.
• this substrate processing apparatus 101 includes one common transfer chamber 102 formed in a substantially polygonal shape (eg, hexagonal shape) and a plurality of (eg, four) processing devices configured to be evacuated.
• a vacuum processing apparatus including chambers 104A to 104D.
• the configuration of the vacuum processing apparatus in the substrate processing apparatus 101 shown in FIG. 28 is substantially the same as the configuration of the first vacuum processing apparatus in the substrate processing apparatus 100 shown in FIG.
• the substrate processing apparatus 101 is an example in which one vacuum processing apparatus is connected to the carry-in transfer chamber 110 via two load lock chambers 108A and 108B.
• the present invention can also be applied to the substrate processing apparatus 101 having such a configuration.
• the processing chambers 104A to 104D at least one of the two processing chambers is configured as a foreign matter removal processing chamber, and the other two processing chambers are configured as a Ti film forming processing chamber and a Ti silicide forming processing chamber, respectively.
• the foreign substance removal process may be executed in a series of steps such as a product generation process (COR process) and a product removal process (eg, PHT process).
• COR process product generation process
• PHT process product removal process
• two of the processing chambers 104A to 104D are configured as a product generation processing chamber and a product removal processing chamber, respectively.
• FIG. 29 shows a configuration example of the processing chamber in the substrate processing apparatus 101. Shown in Figure 29 In the configuration example, the processing chambers 104A, 104B, 104C, and 104D connected to the common transfer chamber 102 are each configured as a COR processing chamber, a PHT processing chamber, a Ti film deposition processing chamber, and a Ti silicide formation processing chamber. It is.
• a wafer W transfer process in the substrate processing apparatus 101 configured as shown in FIG. 29 will be described. Since the order of processing in the processing chambers 104A to 104D for the wafer W is performed in the order described above, the transfer path of the wafer W is as shown by a solid arrow in FIG.
• the transfer process of the wafer W in the transfer-side transfer chamber 110 shown in FIG. 29 is the same as the case shown in FIG. 13, and thus detailed description thereof is omitted.
• the transport paths X31 to X33 shown in FIG. 29 correspond to the transport paths XI1 to X13 shown in FIG.
• the processing mechanism 104D is accommodated in the processing chamber 104D, and the processed Ueno and W are picked up and placed in the empty load lock chamber 108B as indicated by the transfer path Y31.
• the processed wafer W is stored in the processing chamber 104C by the transfer mechanism 118, and is taken into the empty processing chamber 104D for processing as shown in the transfer path Y32.
• Chamber 10 Start processing in 4D.
• the unprocessed wafer W waiting in the load lock chamber 108A is picked up by the transfer mechanism 118, and is transferred into the empty processing chamber 104A as indicated by the transfer path Y35.
• the processing in the processing chamber 104A is started.
• the gate valve necessary for loading / unloading wafer W is opened / closed. The above operation is repeated every time the processing of wafer W is completed in each of the processing chambers 104A to 104D.
• each of the processing chambers 104A to 104D is not limited to that shown in FIG.
• any of the processing chambers 104A to 104D may be configured as a COR processing chamber, a PHT processing chamber, a Ti film deposition processing chamber, or a Ti silicide formation processing chamber. Therefore, the transport sequence of Si wafers is not necessarily limited to the processing chambers 104A to 104D as long as they are transported in the order of the COR processing chamber, the PHT processing chamber, the Ti film deposition processing chamber, and the Ti silicide formation processing chamber. The order of 104 A to 104D is not necessarily required.
• another processing chamber may be added and connected to the common transfer chamber 102, and the processing chamber may be configured as a TiN film deposition processing chamber. According to this, the Si wafer on which the Ti silicide formation process has been completed can be transferred to the TiN film formation processing chamber and continuously executed even if the TiN film formation process is performed.
• the present invention described in detail with reference to the first or second embodiment may be applied to a system constituted by a plurality of devices or an apparatus having one device power.
• a medium such as a storage medium storing a software program that implements the functions of the above-described embodiments is supplied to the system or device,
• the computer (or CPU or MPU) of the device reads and executes a program stored in a storage medium or other medium. Therefore, it goes without saying that the present invention is achieved.
• the program from which the medium power such as a storage medium is read is written in the memory provided in the function expansion board inserted into the computer or the function expansion unit connected to the computer, and then the program instruction is issued.
• the case where the CPU of the function expansion board or function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing is also included in the present invention.
• the present invention relates to a substrate processing apparatus for performing a substrate processing for forming a metal silicide film on a Si-containing surface such as the surface of a Si wafer or a metal silicide layer, a substrate processing method, a program, and a recording recording a program. Applicable to media.

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