WO2007039992A1 - 2層フレキシブル基板 - Google Patents
2層フレキシブル基板 Download PDFInfo
- Publication number
- WO2007039992A1 WO2007039992A1 PCT/JP2006/316388 JP2006316388W WO2007039992A1 WO 2007039992 A1 WO2007039992 A1 WO 2007039992A1 JP 2006316388 W JP2006316388 W JP 2006316388W WO 2007039992 A1 WO2007039992 A1 WO 2007039992A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- copper
- layer
- flexible substrate
- insulator film
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
- B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/28—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42
- B32B27/281—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42 comprising polyimides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2307/00—Properties of the layers or laminate
- B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
- B32B2307/206—Insulating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/032—Organic insulating material consisting of one material
- H05K1/0346—Organic insulating material consisting of one material containing N
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24355—Continuous and nonuniform or irregular surface on layer or component [e.g., roofing, etc.]
Definitions
- the present invention relates to a two-layer flexible substrate, and more specifically to a two-layer flexible substrate in which a copper layer is formed on an insulator film.
- a two-layer flexible substrate has attracted attention.
- a two-layer flexible board has a copper conductor layer directly on an insulator film without using an adhesive.
- the thickness of the board itself can be reduced, and the thickness of the copper conductor layer to be deposited can be reduced. It has the advantage that it can be adjusted to any thickness.
- it is common to form a base metal layer on an insulator film and then apply copper electroplating on the base metal layer.
- a large number of pinholes are generated in the base metal layer obtained in this way, and an exposed portion of the insulating film is generated.
- the exposed portion by the pinhole can be filled.
- Patent Document 1 a base metal layer is formed on an insulator film by a dry plating method, and then a primary electrolytic copper plating film is formed on the base metal layer.
- a method for producing a two-layer flexible substrate is described in which an Al force solution treatment is performed, and then an electroless copper plating film layer is deposited, and finally a secondary electric copper plating film layer is formed.
- this method complicates the process.
- Patent Document 1 Japanese Patent Laid-Open No. 10-193505
- An object of the present invention is to provide a two-layer flexible substrate that is excellent in etching characteristics and adhesion to a resist and has no surface defects.
- the etching characteristics of the two-layer flexible substrate and the adhesion to the resist were determined by defining the surface roughness (Ra) of the copper layer and the crystal grain size of the cross section.
- the present inventors have found that a two-layer substrate having excellent adhesion to a resist and no surface defects is obtained.
- the two-layer flexible substrate has excellent etching characteristics and adhesion to the resist. It becomes.
- this surface roughness eliminates surface defects that do not affect fine line formation and improves yield.
- FIG. 1 is a diagram illustrating an equation for obtaining an etching rate.
- the two-layer flexible substrate of the present invention is obtained by forming a copper layer on an insulator film.
- a base metal layer is formed on an insulator film, and then a copper layer having a predetermined thickness is electroplated. It is preferable to form it by this.
- the insulator film used in the present invention includes a polyimide resin, a polyester resin, a thermosetting resin such as a phenol resin, a thermoplastic resin such as a polyethylene resin, a condensation polymer such as a polyamide, Examples thereof include a film having a mixture force of one kind or two or more kinds of resins.
- the polyimide film include various polyimide films, such as Kapton (manufactured by Toray Dubon) and Iupilex (manufactured by Ube Industries).
- a film having a thickness of 10 to 50 ⁇ m is preferable.
- a base metal layer made of a single element such as Ni, Cr, Co, Ti, Cu, Mo, Si, or V or a mixed system is deposited, sputtered, or attached. It can be formed by a known method.
- the thickness of the base metal layer is preferably 10 to 500 nm.
- the two-layer flexible substrate of the present invention is obtained by forming a copper plating layer on the insulating film on which the base metal layer described so far has been formed by conventional electric plating.
- a normal acidic copper plating solution can be used as the plating solution, and an aqueous solution obtained by mixing chlorine, a nonionic surfactant, and a sulfur organic compound as an additive with a copper sulfate aqueous solution. It is preferable to form a copper layer having a thickness of 3 to 30 m which is preferably used.
- the nonionic surfactant is preferably a polyether compound such as polyethylene glycol or polypropylene glycol.
- the sulfur organic compound is preferably a compound having the structural formula of the following general formula (1) or (2).
- RR 2 and R 3 are alkylene groups having 1 to 8 carbon atoms, R 4 is hydrogen,
- H- X is selected from the group consisting of hydrogen, sulfonic acid group, phosphonic acid group, sulfonic acid or alkali metal base of phosphonic acid or ammonium base, Y Is a group of forces that are also alkali metal basic forces of sulfonic acid group, HH phosphonic acid group, sulfonic acid or phosphonic acid, and is C, Z is hydrogen, or alkali metal, and n is 2 or 3. is there. ) N
- Examples of the sulfur-based organic compound represented by the general formula (1) include SC and N such as the following, and are preferably used.
- examples of the sulfur-based organic compound represented by the general formula (2) include the following, and are preferably used.
- the surface roughness (Ra) of the copper layer is from 0.10 to 0.25 ⁇ m, and preferably from 0.12 to 0.24 ⁇ m.
- the surface roughness (Ra) is in the range of 0.10 to 0.25 m, so the surface roughness is compatible with fine lines.
- the surface roughness of the copper layer generally obtained by ordinary plating is generally rougher than a force of 0.25 / zm, which is less than 0.1 m.
- a glossy product of less than 0 .: m it can be obtained by further adding a nitrogen-containing compound to the additive of the above-mentioned sticking solution.
- those exceeding 0.25 m can be obtained with an aqueous copper sulfate solution (without additives).
- plating is performed by a method of gradually increasing the current density using an aqueous solution obtained by adding chlorine, a nonionic surfactant, and a sulfur-based organic compound to an aqueous copper sulfate solution as a matting solution.
- the above range can be adopted. Specifically, for example, using the above-described dip solution containing 0.1-: LOOOppm each of a non-ionic surfactant and a sulfur-based organic compound, the current density is continuously in the range of 0.1 to 50 AZdm 2. Or gradually increase in 2-10 steps The method of going is preferable.
- the plating temperature is preferably 20 to 70 ° C. By performing plating in this way, the crystal grain size of copper becomes smaller and closer to the insulator film, and gradually increases.
- the average crystal grain size of copper at 1 ⁇ m from the insulator film of the copper layer is 0.8 m or less, and is 0.2 to 0.7 / zm. / ⁇ .
- the average crystal grain size of copper in the copper layer becomes smaller as it is closer to the insulator film surface as described above. Therefore, if the average crystal grain size of copper at 1 m from the insulator film is 0.8 ⁇ m or less, it will be less if it is closer to the insulator film than 1 ⁇ m.
- the etching characteristics in the vicinity of the insulator film are important, and the average crystal grain size of copper from the insulator film of the copper layer to 1 ⁇ m is 0.8 m or less. By doing so, fine patterning becomes possible.
- the smaller the particle size the better the etching characteristics. That is, by reducing the crystal grain size in the vicinity of the insulator film, etching becomes easier, side etching is suppressed, and etching characteristics are improved.
- the crystal grain size of copper in the vicinity of the insulator film exceeds 0.8 m when produced by the usual method of glossing with copper sulfate, but as described above, the type of additive is different. It can be reduced by changing the current density and plating temperature, and it will be less than 0.
- the average crystal grain size of copper at 1 ⁇ m from the insulator film can be determined, for example, by observing with SIM after FIB cutting and observing and measuring the crystal grain size.
- the two-layer flexible substrate of the present invention forms a base metal layer by a general method, and even if a pinhole is generated in the base metal layer, no pinhole is generated on the surface of the copper conductor layer. There are no surface defects.
- the detailed mechanism is not known about this, even if pinholes occur in the underlying metal layer, the average crystal grain size of copper at 1 ⁇ m from the insulator film of the copper layer is 0.8 m or less. This is presumably because the pinhole can be filled with copper.
- the polyimide film having the base metal layer was electroplated under the following plating conditions to produce a copper film of about 8 m.
- Table 1 shows the additives and their amounts.
- Liquid volume Approximately 800ml
- the surface roughness (Ra) m) (arithmetic average roughness) of the obtained copper polyimide two-layer substrate was measured according to JIS B 06 01, and the average crystal of copper at 1 ⁇ m from the polyimide film The particle size was determined, and the number of defects, etching characteristics, and adhesion to the resist were evaluated.
- the average crystal grain size was observed by SIM after cutting the cross section from FIB, and the average value of the crystal grain size of the 1 ⁇ m high part (10 m width) from the polyimide was determined. The results are shown in Table 1.
- the number of defects was determined by visual observation of the number of defects on the copper layer surface ldm 2 (the number of minute protrusions or indentations). The results are shown in Table 1.
- the etching characteristics were evaluated by the etching rate.
- the etching rate was calculated based on the formula shown below by forming a 20 m pitch line.
- Evaluation was based on electroless gold plating resistance.
- a commercially available solder resist was applied on the substrates obtained in Examples 1-2 and Comparative Examples 1-2.
- An evaluation substrate was prepared by curing after exposure and development. This evaluation substrate was plated using a commercially available electroless Ni plating solution and electroless gold plating solution.
- a peel test using cello tape was performed on the evaluation board after the soldering to evaluate the resist peeling. In the case of using the substrate of Example 2, the resist showed no peeling at all, whereas in the case of using the substrates of Comparative Examples 1 and 2, peeling was slightly observed.
- the copper polyimide bilayer substrate of the present invention is excellent in etching characteristics and adhesion to a resist, and has no surface defects.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Laminated Bodies (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/992,209 US8568856B2 (en) | 2005-10-05 | 2006-08-22 | Two-layer flexible substrate |
JP2007538659A JP4771552B2 (ja) | 2005-10-05 | 2006-08-22 | 2層フレキシブル基板 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005-292183 | 2005-10-05 | ||
JP2005292183 | 2005-10-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007039992A1 true WO2007039992A1 (ja) | 2007-04-12 |
Family
ID=37906036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/316388 WO2007039992A1 (ja) | 2005-10-05 | 2006-08-22 | 2層フレキシブル基板 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8568856B2 (ja) |
JP (1) | JP4771552B2 (ja) |
KR (1) | KR100999207B1 (ja) |
CN (1) | CN100588309C (ja) |
TW (1) | TWI343767B (ja) |
WO (1) | WO2007039992A1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2008126522A1 (ja) * | 2007-03-15 | 2010-07-22 | 日鉱金属株式会社 | 銅電解液及びそれを用いて得られた2層フレキシブル基板 |
US20100279069A1 (en) * | 2007-12-27 | 2010-11-04 | Nippon Mining And Metals Co., Ltd. | Method of Producing Two-Layered Copper-Clad Laminate, and Two-Layered Copper-Clad Laminate |
KR20140048803A (ko) * | 2012-10-16 | 2014-04-24 | 스미토모 긴조쿠 고잔 가부시키가이샤 | 2층 플렉시블 기판, 및 2층 플렉시블 기판을 기재로 한 프린트 배선판 |
WO2016017773A1 (ja) * | 2014-07-31 | 2016-02-04 | 住友金属鉱山株式会社 | タッチパネル用導電性基板、タッチパネル用導電性基板の製造方法 |
WO2021200614A1 (ja) * | 2020-04-01 | 2021-10-07 | 住友電気工業株式会社 | フレキシブルプリント配線板及びその製造方法 |
WO2022030644A1 (ja) * | 2020-08-07 | 2022-02-10 | 東洋鋼鈑株式会社 | 銅張積層体及びその製造方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5544872B2 (ja) * | 2009-12-25 | 2014-07-09 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
KR20200073051A (ko) * | 2018-12-13 | 2020-06-23 | 엘지이노텍 주식회사 | 인쇄회로기판 |
JP2021034591A (ja) * | 2019-08-26 | 2021-03-01 | キオクシア株式会社 | 半導体装置およびその製造方法 |
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JPH0645729A (ja) * | 1992-07-24 | 1994-02-18 | Mitsubishi Electric Corp | プリント配線板の製造方法 |
JP2000034594A (ja) * | 1998-07-15 | 2000-02-02 | Japan Energy Corp | 銅めっき方法及び銅めっき液 |
JP2002299777A (ja) * | 2001-03-30 | 2002-10-11 | Sumitomo Bakelite Co Ltd | フレキシブルプリント回路用基板及びその製造方法 |
JP2003324258A (ja) * | 2002-05-01 | 2003-11-14 | Nippon Mektron Ltd | プリント配線板用銅張板 |
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JP2005113183A (ja) * | 2003-10-06 | 2005-04-28 | Fujikura Ltd | 電解銅箔およびその製造方法、並びに銅張り積層板 |
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TWI263461B (en) * | 2003-12-26 | 2006-10-01 | Ind Tech Res Inst | Enhanced flexible copper foil structure and fabrication method thereof |
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2006
- 2006-08-22 US US11/992,209 patent/US8568856B2/en active Active
- 2006-08-22 WO PCT/JP2006/316388 patent/WO2007039992A1/ja active Application Filing
- 2006-08-22 KR KR1020087010338A patent/KR100999207B1/ko active IP Right Grant
- 2006-08-22 JP JP2007538659A patent/JP4771552B2/ja active Active
- 2006-08-22 CN CN200680036650A patent/CN100588309C/zh active Active
- 2006-09-12 TW TW095133584A patent/TWI343767B/zh active
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JPH0645729A (ja) * | 1992-07-24 | 1994-02-18 | Mitsubishi Electric Corp | プリント配線板の製造方法 |
JP2000034594A (ja) * | 1998-07-15 | 2000-02-02 | Japan Energy Corp | 銅めっき方法及び銅めっき液 |
JP2002299777A (ja) * | 2001-03-30 | 2002-10-11 | Sumitomo Bakelite Co Ltd | フレキシブルプリント回路用基板及びその製造方法 |
JP2003324258A (ja) * | 2002-05-01 | 2003-11-14 | Nippon Mektron Ltd | プリント配線板用銅張板 |
JP2004031370A (ja) * | 2002-06-07 | 2004-01-29 | Matsushita Electric Ind Co Ltd | フレキシブルプリント回路基板及びその製造方法 |
JP2005113183A (ja) * | 2003-10-06 | 2005-04-28 | Fujikura Ltd | 電解銅箔およびその製造方法、並びに銅張り積層板 |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
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JPWO2008126522A1 (ja) * | 2007-03-15 | 2010-07-22 | 日鉱金属株式会社 | 銅電解液及びそれを用いて得られた2層フレキシブル基板 |
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WO2021200614A1 (ja) * | 2020-04-01 | 2021-10-07 | 住友電気工業株式会社 | フレキシブルプリント配線板及びその製造方法 |
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US11871514B2 (en) | 2020-04-01 | 2024-01-09 | Sumitomo Electric Industries, Ltd. | Flexible printed circuit board and method for producing the same |
JP7446331B2 (ja) | 2020-04-01 | 2024-03-08 | 住友電気工業株式会社 | フレキシブルプリント配線板及びその製造方法 |
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Also Published As
Publication number | Publication date |
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US8568856B2 (en) | 2013-10-29 |
US20090092789A1 (en) | 2009-04-09 |
JP4771552B2 (ja) | 2011-09-14 |
KR100999207B1 (ko) | 2010-12-07 |
TW200715919A (en) | 2007-04-16 |
CN100588309C (zh) | 2010-02-03 |
KR20080061387A (ko) | 2008-07-02 |
JPWO2007039992A1 (ja) | 2009-04-16 |
TWI343767B (en) | 2011-06-11 |
CN101278604A (zh) | 2008-10-01 |
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