WO2006122505A1 - Conditionnement de circuit intégré et procédé de fabrication idoine - Google Patents

Conditionnement de circuit intégré et procédé de fabrication idoine Download PDF

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Publication number
WO2006122505A1
WO2006122505A1 PCT/CN2006/001024 CN2006001024W WO2006122505A1 WO 2006122505 A1 WO2006122505 A1 WO 2006122505A1 CN 2006001024 W CN2006001024 W CN 2006001024W WO 2006122505 A1 WO2006122505 A1 WO 2006122505A1
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WO
WIPO (PCT)
Prior art keywords
heat
substrate
integrated circuit
semiconductor core
protective layer
Prior art date
Application number
PCT/CN2006/001024
Other languages
English (en)
French (fr)
Inventor
Jen-Shyan Chen
Original Assignee
Jen-Shyan Chen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jen-Shyan Chen filed Critical Jen-Shyan Chen
Priority to JP2008511537A priority Critical patent/JP2008541464A/ja
Priority to EP06741912A priority patent/EP1923913A4/en
Publication of WO2006122505A1 publication Critical patent/WO2006122505A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to an integrated circuit packaging and a process thereof, and in particular, an integrated circuit package of the present invention includes a heat dissipation module.
  • Heat dissipation has always been an indispensable factor in the design of electronic systems. The purpose is to reduce the chances of electronic components failing or damaging due to overheating, and to improve the reliability of the entire system.
  • FIG. 1A and FIG. 1B both illustrate an integrated circuit package of a conventional integrated heat sink. As shown in FIG. 1A and FIG.
  • the heat generated by the chip 10 in the integrated circuit package 1 needs to pass through a heat conducting layer 14 to reach the heat dissipation module 2 via conduction.
  • the heat generated by the chip needs to be conducted through the multi-layer material, instead of directly contacting the heat-dissipating module to dissipate heat, so the heat energy cannot be quickly dissipated, and thus the heat concentration problem caused by the hot spot cannot be effectively solved.
  • the heat dissipation efficiency of the chip cannot be accurately controlled, resulting in a decrease in the performance of the integrated circuit due to overheating.
  • the present invention provides an integrated circuit package, which integrates the heat dissipation module into the integrated circuit package, reduces the thermal resistance (Tlieraml resistance) within the package level, achieves a partial anti-heating effect, and effectively reduces the temperature of the chip.
  • the integrated circuit package according to the present invention can overcome the above problem of heat dissipation, quickly and efficiently conduct heat generated by the chip, and solve the problem of hot spots.
  • SUMMARY OF THE INVENTION In order to achieve the above object and solve the problems discussed above, the present invention provides an integrated circuit packaging and a process thereof.
  • An integrated circuit package according to a first preferred embodiment of the present invention includes a substrate
  • the substrate has a first surface, an inner circuit formed on the first surface, a second surface opposite to the first surface, and an outer circuit formed on the second surface .
  • the external circuit is electrically connected to the internal circuit.
  • the semiconductor core has an active surface, a plurality of bond pads formed on the active surface, and a back surface opposite the active surface.
  • the semiconductor core is mounted on the first surface of the substrate such that the plurality of soldering features contact the internal circuit.
  • the heat dissipation module includes a heat conduction device having a flat end face. The heat conducting device contacts and engages the back side of the semiconductor core with its own flat end face.
  • the protective layer covers an exposed portion of the substrate, an exposed portion of the semiconductor core, and an exposed portion of the end surface of the heat conducting device that is in contact with the semiconductor die
  • a method of fabricating an integrated circuit package in accordance with a first preferred embodiment of the present invention A substrate, a semiconductor core, and a heat dissipation module are provided.
  • the substrate has a first surface, an internal circuit formed on the first surface, a second surface opposite the first surface, and an external circuit formed on the second surface.
  • the outer circuit forms an electrical connection with the inner circuit.
  • the semiconductor core has an active surface, a plurality of pads formed on the active surface, and a back surface opposite the active surface.
  • the heat dissipating module includes a heat conducting device having a flat end face at one end of itself. The method is, firstly, fixing the semiconductor die on the first surface of the substrate such that the plurality of solder joints contact internal circuits on the substrate.
  • An integrated circuit package includes a substrate, a protection a layer, a semiconductor core, and a heat dissipation module.
  • the substrate has a first surface, an internal circuit formed on the first surface, a second surface opposite the first surface, and an external circuit formed on the second surface.
  • the outer circuit forms an electrical connection with the inner circuit.
  • the protective layer is formed on the first surface of the substrate.
  • the protective layer has an opening that is configured and exposed within the opening.
  • the semiconductor core has an active surface, a plurality of pads formed on the active surface, and a back surface opposite the active surface.
  • the semiconductor die is fixed in the opening of the protective layer such that the plurality of pads contact the internal circuit, and a gap exists between the semiconductor core and the protective layer.
  • the heat dissipating module includes a heat conducting device having a flat end face at one end thereof. The heat conducting device is placed into the opening with the end and contacts with its flat end face and engages the back side of the semiconductor core.
  • the substrate has a first surface, an internal circuit formed on the first surface, a second surface opposite the first surface, and an external circuit formed on the second surface.
  • the outer circuit forms an electrical connection with the inner circuit.
  • the semiconductor core has an active surface, a plurality of pads formed on the active surface, and a back surface opposite the active surface.
  • the method is, first, forming a protective layer.
  • the protective layer substantially covers the first surface of the substrate and has an opening that is disposed and exposed within the opening.
  • the semiconductor core is fixed in the opening of the protective layer such that the plurality of pads contact the internal circuit on the substrate, and a gap exists between the semiconductor core and the protective layer.
  • An end of a heat dissipation module is disposed into the opening.
  • the heat dissipating module includes a heat conducting device having a flat end face at one end thereof.
  • the thermally conductive device is contacted with its flat end face and bonded to the back side of the semiconductor core to complete the integrated circuit package. Since the integrated circuit package provided by the present invention directly bonds the heat dissipating module to the semiconductor core, the heat conducting device can conduct the heat generated by the semiconductor die and conduct it through the fins to the surrounding air. Not only solve the hot spot problem, but also greatly improve the heat dissipation efficiency.
  • the integrated circuit package can further integrate other heat dissipation technologies to achieve good heat dissipation. Therefore, the integrated circuit package according to the present invention is more suitable for the application of a high power semiconductor core than the prior art.
  • FIG. 1A illustrates an integrated circuit package of a conventional integrated heat sink
  • FIG. 1B illustrates another conventional integrated circuit package with integrated heat sink
  • FIG. 2 illustrates an external view of an integrated circuit package according to the present invention
  • 3 is a cross-sectional view taken along line AA of FIG. 2, showing an integrated circuit package in accordance with a first preferred embodiment of the present invention
  • FIGS. 4A to 4D are diagrams showing an integrated circuit package in accordance with a first preferred embodiment of the present invention
  • Figure 5 is a cross-sectional view taken along line AA of Figure 2, showing an integrated circuit package in accordance with a second preferred embodiment of the present invention
  • Figures 6A through 6E show integration in accordance with a second preferred embodiment of the present invention Circuit packaging process
  • Figure 7 shows the heat conduction and heat dissipation mechanism in the heat dissipation module.
  • a main object of the present invention is to provide an integrated circuit packaging. Please refer to FIG. 2.
  • FIG. 2 is a perspective view of an integrated circuit package according to the present invention. As shown in FIG. 2, the integrated circuit package 1 includes a heat-dissipating module 12 and a casing 18.
  • FIG. 3 is a cross-sectional view taken along line AA of FIG. 2, showing an integrated circuit package in accordance with a first preferred embodiment of the present invention.
  • the integrated circuit package 1 further includes a semiconductor core 10, a substrate 16 and a protection layer 14 .
  • the semiconductor core is a high power integrated circuit.
  • the substrate 16 has a first surface, an inner circuit formed on the first surface, a second surface opposite the first surface, and an outer circuit formed on the second surface (Outer) Circuit)13.
  • the outer circuit 13 is electrically connected to the inner circuit.
  • the semiconductor core 10 has an active surface, a plurality of bond pads 17 formed on the active surface, and a back surface opposite the active surface.
  • the semiconductor core 10 is fixed by a Flip-chip process On the first surface of the counter 16 , the plurality of pads 17 are caused to contact the inner circuit to form an electrical connection.
  • the heat dissipation module 12 includes a heat conduction device 122 and a plurality of heat-dissipating fins 124.
  • the heat conducting device 122 can be a heat pipe, a hot column or a cylinder formed of a material having a high thermal conductivity.
  • the heat conducting device 122 has a flat end surface, and the heat dissipating fins 124 are disposed around the heat conducting device 122 to help dissipate heat.
  • the heat conducting device 122 contacts and engages the back surface of the semiconductor core 10 with its own flat end face.
  • the protective layer 14 covers the exposed portion of the substrate 16, the exposed portion of the semiconductor core 10, and the exposed portion of the end surface of the heat conducting device 122 that is in contact with the semiconductor core.
  • the housing 18 is adapted to receive the heat dissipation module 12, the protective layer 14, and the substrate 16.
  • the outer casing 18 has two openings and a top surface. As shown in FIG. 3, the outer casing 18 has a "combination portion 15" on the inner side of the opening for engaging the substrate 16. In practical applications, other heat dissipating devices may be added on the top surface, or a fan may be added to the integration.
  • Side of Circuit Package 1 A method of fabricating an integrated circuit package in accordance with a first preferred embodiment of the present invention will now be described in detail.
  • Figures 4A through 4D show a first preferred embodiment in accordance with the present invention.
  • a substrate 16 and a semiconductor die 10 are provided.
  • the substrate 16 has a first surface, an inner circuit formed on the first surface, and a first surface opposite to the first surface a second surface and an external circuit 13 formed on the second surface.
  • the external circuit 13 is electrically connected to the internal circuit.
  • the semiconductor core 10 has an active surface, and a plurality of active surfaces are formed on the active surface.
  • the heat dissipating module 12 includes a heat conducting device 122 having a flat end surface at one end thereof. Referring to FIG. 4A, FIG.
  • the semiconductor core 10 is fixed on the first surface of the substrate 16 by a flip chip process, so that the plurality of pads 17 contact the internal circuit on the reverse 16.
  • a protection is formed.
  • the end of the heat conducting device 122 is disposed to Within the opening 19, the heat conducting device 122 is brought into contact with and bonded to the back surface of the semiconductor die 10 with its flat end face.
  • 12 further includes a plurality of heat dissipation fins 124 disposed around a heat conducting device 122 to help dissipate heat.
  • FIG. 5 is a cross-sectional view taken along line AA of FIG. 2, showing an integrated circuit package in accordance with a second preferred embodiment of the present invention.
  • the integrated circuit package 1 further includes a semiconductor core 10, a substrate 16, and a protective layer 14.
  • the semiconductor die can be a high power integrated circuit.
  • the substrate 16 has a first surface, an internal circuit formed on the first surface, a second surface opposite the first surface, and an external circuit 13 formed on the second surface.
  • the outer circuit 13 is electrically connected to the inner circuit.
  • the protective layer 14 is formed on the first surface of the substrate 16.
  • the protective layer 14 has an opening that is approximately the size of the end face of the heat dissipation module 12, and the inner circuit is disposed and exposed to the opening.
  • the semiconductor core 10 has an active surface, a plurality of pads 17 formed on the active surface, and a back surface opposite the active surface.
  • the semiconductor core 10 is fixed in the opening of the protective layer 14 by a flip chip process, so that the plurality of pads 17 contact the internal circuit of the first surface of the substrate 16.
  • a gap 11 exists between the semiconductor core 10 and the protective layer 14.
  • the heat dissipation module 12 includes a heat conduction device 122 and a plurality of heat dissipation fins 124.
  • the heat conducting device 122 has a flat end face at one end of itself.
  • the heat conducting device 122 is placed into the opening with the end and contacts and engages the back side of the semiconductor core 10 with its flat end surface.
  • the heat dissipation fins 124 are disposed around a heat conducting device 122 to help dissipate heat.
  • the housing 18 is adapted to receive the heat dissipation module 12, the protective layer 14, and the substrate 16.
  • FIGS. 6A-6E illustrate a process of an integrated circuit package in accordance with a second preferred embodiment of the present invention.
  • a substrate 16 and a semiconductor core 10 are provided.
  • the substrate 16 has a first surface, An inner circuit formed on the first surface, a second surface opposite the first surface, and an outer circuit 13 formed on the second surface.
  • the outer circuit 13 is electrically connected to the inner circuit.
  • the semiconductor core 10 has an active surface, a plurality of pads 17 formed on the active surface, and a back surface opposite the active surface. Referring to FIG. 6A, as shown in FIG.
  • a protective layer 14 is first formed on the substrate 16.
  • the protective layer 14 substantially covers the first surface of the substrate 16 and has an opening 19 which is approximately the same size as the end surface of the heat dissipation module 12.
  • the inner circuit is configured and exposed within the opening 19.
  • the semiconductor die 10 is fixed in the opening 19 of the protective layer 14 by a flip chip process such that the plurality of pads 17 contact the internal circuitry on the substrate 16. Since the area of the opening 19 is larger than the area of the back surface of the semiconductor core 10, a gap 11 exists between the semiconductor core 10 and the protective layer 14.
  • a thermal adhesive is filled in the gap 11 to help dissipate heat. As shown in FIG.
  • the heat dissipation module 12 includes a heat conduction device 122 and a plurality of heat dissipation fins 124.
  • the heat conducting device 122 has a flat end face at one end of itself.
  • the heat dissipating fins 124 are disposed around the heat conducting device 122 to help dissipate heat.
  • the heat conducting device 122 is contacted with its flat end face and joined to the back surface of the semiconductor core 10.
  • FIG. 7 illustrates a heat conduction and heat dissipation mechanism in the heat dissipation module.
  • the heat dissipation module 12 includes the heat conduction device 122 and a plurality of heat dissipation fins 124 .
  • the heat conducting device 122 may be a thermal conductive column or a heat pipe made of copper.
  • the heat transfer device 122 includes a working fluid 126 and a capillary structure 128 therein.
  • the heat dissipation fins 124 are disposed around a heat conducting device 122 to help dissipate heat.
  • the working fluid 126 in the heat conducting device 122 that is closer to the semiconductor core 10 is evaporated from a liquid into a gas.
  • the vaporized working fluid 126 can transfer heat to the other end of the heat conducting device 122.
  • the working fluid 126 is again condensed into a liquid.
  • the capillary structure 128 is used to transfer the working fluid 126 that is recondensed to a liquid back to the end of the heat conducting device 122 that is closer to the semiconductor core 10.
  • the heat dissipation module can immediately dissipate the heat generated by the semiconductor die into the surrounding air by using the heat dissipation fin and the thermal conductive adhesive. Greatly improve heat dissipation efficiency. By improving the heat dissipation efficiency of the semiconductor core, the problem of the performance degradation of the integrated circuit due to overheating is solved. Therefore, compared with the prior art, the integrated circuit package of the integrated heat dissipation module according to the present invention is more suitable for application in an electronic device requiring a high power and high efficiency semiconductor core.
  • the features and spirit of the present invention are intended to be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. Description of the reference numerals
  • Heat sink fin 16 substrate
  • protective layer 18 outer casing

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

集成电路封装及其制造方法
技术领域本发明涉及一种集成电路封装 (Integrated circuit packaging)及 其工艺， 并且特别地， 本发明的集成电路封装包含一散热模块。 背景技术散热一直是电子系统设计时不可或缺的考虑因素， 目的是降 低电子组件因过热而发生故障或毁损的机会， 而提升整个系统的可靠度。 以现在的集成电路 (IC)而言， 尤其是计算机的中央处理系统 (CPU),散热 技术多是采用一些高热传导性的金属作为散热基本材料， 结合散热鳍片， 再 加上一颗强而有力的风扇， 来满足现今集成电路的散热需求。 目前的散热技术， 大多将散热模块多安装于已经封装好的集成电路外 壳。 请参阅图 1A以及图 1B, 图 1A以及图 1B皆绘示现有的整合散热装置 的集成电路封装。 如图 1A以及图 1B所示， 集成电路封装 1内的芯片 10所 产生的热， 需通过一导热层 14, 经由传导才到达散热模块 2。 芯片所产生的 热能需经由多层材料而传导， 而非直接接触散热模块来消散热能， 因此热能 无法快速被引导散开， 因而无法有效解决热点 (Hot spot)所造成的热集中问 题。芯片的散热效率也无法被准确地控制，造成集成电路因过热而效能下降。 随着行动信息的概念兴起， 轻薄短小且兼顾高运算效能的可携式产品渐 渐成为主流。 散热技术面临了小型、 整合化而且兼具高散热量以及高能量密 度的挑战。 以现今的散热技术已经渐渐地无法负荷未来的散热需求， 尤其是 芯片局部热集中， 或俗称热点的问题， 势必需要一些新的散热技术来解决这 些问题。 因此， 本发明提供一种集成电路封装， 将散热模块整合于集成电路封装 内， 于封装阶层内即降低热阻 (Tlieraml resistance), 达到部分解热效果， 有效 降低芯片的温度。 根据本发明的集成电路封装可以克服上述散热的问题， 快 速并且有效地传导芯片产生的热能， 解决热点的问题。 发明内容为了达成上述目的并且解决以上所讨论的问题， 本发明提供 一种集成电路封装 (Integrated circuit packaging)及其工艺。 根据本发明的第一优选具体实施例的集成电路封装包含一基板
(Substmte)、 一半导体棵芯 (Semiconductor die)、 一散热模块 (Heat-dissipating module)以及一保护层 (Protection layer)。 该基板具有一第一表面、一形成于该 第一表面上的内电路 (Inner circuit) 一与该第一表面相对的第二表面以及一 形成于该第二表面上的外电路 (Outer circuit)。 该外电路与该内电路形成电连 接。 该半导体棵芯具有一有源面、 多个形成于该有源面上的焊垫 (Bond pad) 以及一与该有源面相对的背面。 该半导体棵芯固定于该基板的第一表面上， 致使该多个焊藝接触该内电路。 该散热模块包含一导热装置 (Heat conduction device), 该导热装置具有一平整的端面。 该导热装置以其本身的平整的端面 接触并且接合该半导体棵芯的背面。 该保护层包覆该基板的外露部分、 该半 导体棵芯的外露部分以及该导热装置与该半导体裸芯相接的端面的外露部
根据本发明的第一优选具体实施例的制造一集成电路封装的方法。 提供 一基板、 一半导体棵芯以及一散热模块。 该基板具有一第一表面、 一形成于 该第一表面上的内电路、 '一与该第一表面相对的第二表面以及一形成于该第 二表面上的外电路。 该外电路与该内电路形成电连接。 该半导体棵芯具有一 有源面、 多个形成于该有源面上的焊垫以及一与该有源面相对的背面。 该散 热模块包含一导热装置，该导热装置于其本身的一末端处具有一平整的端面。 该方法为， 首先， 固定该半导体裸芯于该基板的第一表面上， 以致该多 个焊藝接触该基板上的内电路。 形成一保护层， 该保护层大致包覆该基板的 外露部分， 并且该保护层具有一开口（Opening)用以容纳该导热装置的端面。 安置该导热装置的平整端至该开口内， 将该导热装置以其本身的平整的端面 与该半导体棵芯的背面接触并且接合以完成该集成电路封装。 根据本发明的第二优选具体实施例的集成电路封装包含一基板、 一保护 层、 一半导体棵芯以及一散热模块。 该基板具有一第一表面、 一形成于该第 一表面上的内电路、 一与该第一表面相对的第二表面以及一形成于该第二表 面上的外电路。 该外电路与该内电路形成电连接。 该保护层形成于该基板的 第一表面上。 该保护层具有一开口， 该内电路配苴并且暴露于该开口内。 该 半导体棵芯具有一有源面、 多个形成于该有源面上的焊垫以及一与该有源面 相对的背面。 该半导体裸芯固定于该保护层的开口内， 致使该多个焊垫接触 该内电路， 并且一间隙存在于该半导体棵芯与该保护层之间。 该散热模块包 含一导热装置， 该导热装置于其本身的一末端处具有一平整的端面。 该导热 装置以该末端安置入该开口内， 并且以其本身的平整的端面接触并且接合该 半导体棵芯的背面。 根据本发明的第二优选具体实施例的制造一集成电路封装的方法。 提供 一基板以及一半导体棵芯。 该基板具有一第一表面、 一形成于该第一表面上 的内电路、 一与该第一表面相对的第二表面以及一形成于该第二表面上的外 电路。 该外电路与该内电路形成电连接。 该半导体棵芯具有一有源面、 多个 形成于该有源面上的焊垫以及一与该有源面相对的背面。 该方法为， 首先， 成形一保护层。 该保护层大致覆盖该基板的第一表面 并且具有一开口， 该内电路配置并且暴露于该开口内。 固定该半导体棵芯于 该保护层的开口内， 以致该多个焊垫接触该基板上的内电路， 并且一间隙存 在于该半导体棵芯与该保护层之间。 安置一散热模块的一末端至该开口内。 该散热模块包含一导热装置， 该导热装置于其本身的一末端处具有一平整的 端面。 将该导热装置以其的平整的端面接触并且接合该半导体棵芯的背面以 完成该集成电路封装。 由于本发明所提供的集成电路封装将散热模块与半导体棵芯直接接合 在一起， 该导热装置可将该半导体裸芯所产生的热能立即传导发散， 并透过 鳍片至周围的空气中。 不但解决热点的问题， 更大幅提升散热效率。 该集成 电路封装更可以进一步整合其它散热技术以达成良好的散热效果。 因此， 相 较于现有技术， 根据本发明的集成电路封装更适合高功率的半导体棵芯的应 用。 关于本发明的优点与精神可以藉由以下的发明详述及附图得到进一步 的了解。 附图说明 图 1A绘示现有的整合散热装置的集成电路封装； 图 1B绘示 另一种现有的整合散热装置的集成电路封装； 图 2绘示根据本发明的集成电 路封装的外观视图； 图 3为沿图 2中 A-A线的剖面图， 显示根据本发明的第 一优选具体实施例的集成电路封装；图 4A至图 4D显示根据本发明的第一优 选具体实施例的集成电路封装的工艺； 图 5为沿图 2中 A-A线的剖面图， 显 示根据本发明的第二优选具体实施例的集成电路封装；图 6A至图 6E显示根 据本发明的第二优选具体实施例的集成电路封装的工艺； 图 7绘示散热模块 中的导热及散热机制。 实施方式 本发明的一主要目的在于提供一种集成电路封装 (Integrated circuit packaging)。 请参阅图 2, 图 2绘示根据本发明的集成电路封装的外观视图。 如图 2 所示， 该集成电路封装 1包含一散热模块 (Heat- dissipating module)12以及一 外壳 (Casing)18。 请参阅图 3 , 图 3为沿图 2中 A-A线的剖面图， 显示根据本发明的第一 优选具体实施例的集成电路封装。 如图 3所示， 根据本发明的第一优选具体 实施例， 该集成电路封装 1进一步包含一半导体棵芯 (Semiconductor die)10、 一基板 (Substrate)l 6以及一保护层 (Protection layer)14。 于此实施例中， 该半 导体棵芯为一高功率集成电路。 该基板 16 具有一第一表面、 一形成于该第一表面上的内电路 (Inner circuit)、 一与该第一表面相对的第二表面以及一形成于该第二表面上的外电 路 (Outer circuit)13。 该外电路 13与该内电路形成电连接。 该半导体棵芯 10 具有一有源面、 多个形成于该有源面上的焊垫 (Bond pad)17以及一与该有源 面相对的背面。 该半导体棵芯 10藉由一倒装芯片工艺 (Flip-chip process)固定 于该 1反 16的第一表面上， 致使该多个焊垫 17接触该内电路形成电连接。 该散热模块 12包含一导热装置 (Heat conduction device) 122以及多个散热 鳍片（Heat-dissipating fin)124。 该导热装置 122可为一热导管 (Heat pipe), ― 热导柱 (Hot column)或由一高导热系数的材料所成形的柱体。 该导热装置 122 具有一平整的端面， 该等散热鳍片 124设置于该导热装置 122的一周围， 用 以帮助消散热能。 该导热装置 122以其本身的平整的端面接触并且接合该半 导体棵芯 10的背面。该保护层 14包覆该基板 16的外露部分、该半导体棵芯 10的外露部分以及该导热装置 122与该半导体棵芯相接的端面的外露部分。 该外壳 18配合能容纳该散热模块 12、该保护层 14以及该基板 16。于一实施 例中， 该外壳 18具有二开口以及一顶表面。 如图 3所示， 该外壳 18于该开 口内侧具有一" ^合部位 15用以接合该基板 16。 于实际应用中， 可外加其它 散热装置于该顶表面上， 或外加一风扇于该集成电路封装 1的侧面。 以下将详述根据本发明的第一优选具体实施例的集成电路封装的制造方 法。 请参阅图 4A至图 4D, 图 4A至图 4D显示根据本发明的第一优选具体 实施例的集成电路封装的工艺。 首先，提供一基板 16以及一半导体裸芯 10。该基板 16具有一第一表面、 一形成于该第一表面上的内电路、 一与该第一表面相对的第二表面以及一形 成于该第二表面上的外电路 13。 该外电路 13与该内电路形成电连接。 该半 导体棵芯 10具有一有源面、 多个形成于该有源面上的焊垫 17以及一与该有 源面相对的背面。 该散热模块 12包含一导热装置 122, 该导热装置 122于其 本身的一末端处具有一平整的端面。 请参阅图 4A，如图 4A所示，藉由一倒装芯片工艺固定该半导体棵芯 10 于该基板 16的第一表面上， 以致该多个焊垫 17接触该 反 16上的内电路。 接着， 如图 4B所示， 形成一保护层 14, 该保护层大致包覆该基板 10的外露 部分， 并且该保护层 14具有一开口 19用以容纳该导热装置 122的端面。 如 图 4C所示， 安置该导热装置 122的末端至该开口 19内， 将该导热装置 122 以其本身的平整的端面与该半导体裸芯 10的背面接触并且接合。该散热模块 12进一步包含多个散热鰭片 124, 该等散热鰭片 124设置于该导热装置 122 的一周围， 用以帮助消散热能。 最后， 如图 4D所示， 藉由一外壳 18, 容纳 该散热模块 12、该保护层 14以及该基板 16于其中以完成该集成电路封装 1。 请参阅图 5, 图 5为沿图 2中 A-A线的剖面图， 显示根据本发明的第二 优选具体实施例的集成电路封装。 如图 5所示， 根据本发明的第二优选具体 实施例， 该集成电路封装 1进一步包含一半导体棵芯 10、 一基板 16以及一 保护层 14。 于此实施例中， 该半导体裸芯可为一高功率集成电路。 该基板 16具有一第一表面、一形成于该第一表面上的内电路、一与该第 一表面相对的第二表面以及一形成于该第二表面上的外电路 13。该外电路 13 与该内电路形成电连接。 该保护层 14形成于该基板 16的第一表面上。 该保 护层 14具有一开口， 该开口大小大致相当于该散热模块 12的端面大小， 该 内电路配置并且暴露于该开口内。该半导体棵芯 10具有一有源面、多个形成 于该有源面上的焊垫 17以及一与该有源面相对的背面。 该半导体棵芯 10藉 由一倒装芯片工艺固定于该保护层 14的开口内， 致使该多个焊垫 17接触该 基板 16的第一表面的内电路。 当该散热模块 12的端面的面积大于该半导体 棵芯 10的背面的面积时， 一间隙 11存在于该半导体棵芯 10与该保护层 14 之间。 一导热胶 (Thermal adhesive)充填于该半导体棵芯 10与该保护层 14间 的间隙 11 , 用以帮助消散热能。 该散热模块 12包含一导热装置 122以及多 个散热鰭片 124。 该导热装置 122于其本身的一末端处具有一平整的端面。 该导热装置 122以该末端安置入该开口内， 并且以其本身的平整的端面接触 并且接合该半导体棵芯 10的背面。该等散热鳍片 124设置于该导热装置 122 的一周围， 用以帮助消散热能。 该外壳 18配合能容纳该散热模块 12、 该保 护层 14以及该基板 16。
以下将详述根据本发明的第二优选具体实施例的集成电路封装的制造方 法。请参阅图 6A至图 6E, 图 6A至图 6E显示根据本发明的第二优选具体实 施例的集成电路封装的工艺。 首先，提供一基板 16以及一半导体棵芯 10。该基板 16具有一第一表面、 一形成于该第一表面上的内电路、 一与该第一表面相对的第二表面以及一形 成于该第二表面上的外电路 13。 该外电路 13与该内电路形成电连接。 该半 导体棵芯 10具有一有源面、 多个形成于该有源面上的焊垫 17以及一与该有 源面相对的背面。 请参阅图 6A, 如图 6A所示， 首先于该基板 16上成形一保护层 14。 该 保护层 14大致覆盖该基板 16的第一表面并且具有一开口 19, 该开口 19大 小大致相当于该散热模块 12 的端面大小。 该内电路配置并且暴露于该开口 19内。如图 6B所示，藉由一倒装芯片工艺固定该半导体裸芯 10于该保护层 14的开口 19内， 以致该多个焊垫 17接触该基板 16上的内电路。 由于该开 口 19的面积大于该半导体棵芯 10的背面的面积，一间隙 11存在于该半导体 棵芯 10与该保护层 14之间。 请参阅图 6C, 如图 6C所示， 充填一导热胶于 该间隙 11用以帮助消散热能。 如图 6D所示， 安置一散热模块 12的一末端 至该开口 19内。该散热模块 12包含一导热装置 122以及多个散热鰭片 124。 该导热装置 122于其本身的一末端处具有一平整的端面。 该等散热鳍片 124 设置于该导热装置 122的一周围， 用以帮助消散热能。 将该导热装置 122以 其的平整的端面接触并且接合该半导体棵芯 10的背面。最后，如图 6E所示， 藉由一外壳 18容纳该散热模块 12、 该保护层 14以及该基板 16于其中以完 ¾该集成电路封装 1。 该外壳具有一顶表面用以传导热能， 可与其它散热装 置配合， 以加强散热效果。 请参阅图 7, 图 7绘示散热模块中的导热及散热机制。 如图 7所示， 该 散热模块 12包含该导热装置 122、 多个散热鳍片 124。 于实际应用中， 该导 热装置 122可能为一以铜制成的热导柱或热导管。 该导热装置 122内包含一 工作流体 126以及一毛细组织 128。该等散热鳍片 124设置于该导热装置 122 的一周围， 用以帮助消散热能。 当该半导体棵芯 10产生热时， 会使该导热装 置 122中较靠近该半导体棵芯 10的该工作流体 126由液体蒸发为气体。气化 后的该工作流体 126可将热传至该导热装置 122的另一端。 经该等散热鳍片 124散热冷却后， 该工作流体 126会再度凝结为液体。 该毛细组织 128用以 将再度凝结为液体的该工作流体 126传送回该导热装置 122中较靠近该半导 体棵芯 10的一端。 藉由如图 7所示的循环方式， 可达到导热及散热效果。 由于本发明所提供的集成电路封装系将散热模块与半导体裸芯整合在一 起， 该散热模块可藉由散热鳍片与导热胶将该半导体裸芯所产生的热能立即 发散至周围的空气中，大幅提升散热效率。借着改善半导体棵芯的散热效率， 解决了因过热而造成集成电路效能下降的问题。 因此， 相较于现有技术， 根 据本发明的整合散热模块的集成电路封装更适合应用于需要高功率高效率的 半导体棵芯的电子装置中。 藉由以上优选具体实施例的详述，. 希望能更加清楚描述本发明的特征与 精神， 而并非以上述所揭露的优选具体实施例来对本发明的范畴加以限制。 相反地， 其目的是希望能涵盖各种改变及具相等性的安排于本发明所欲申请 的专利范围的范畴内。 附图标记说明
1 : 集成电路封装 122 导热装置
10: 半导体棵芯 126 工作流体
12、 2: 散热模块 128 毛细组织
124: 散热鳍片 16: 基板
13 外电路 17: 焊垫
14 保护层 18: 外壳
19 开口 11 : 间隙
15 卡合部位

Claims

权利要求书
1. 一种集成电路封装 (Integrated circuit packaging), 包含：
一基板 (Substrate),该基板具有一第一表面、一形成于该第一表面上的内 电路 (Inner circuit), 一与该第一表面相对的第二表面以及一形成于该第二表 面上的外电路 (Outer circuit), 该外电路与该内电路形成电连接；
一半导体棵芯 (Semiconductor die), 该半导体棵芯具有一有源面、 多个形 成于该有源面上的焊垫 (Bond pad)以及一与该有源面相对的背面， 该半导体 棵芯固定于该基板的第一表面上， 致使该多个焊藝接触该内电路；
一散热模块 (Heat-dissipating module), 该散热模块包含一导热装置 (Heat conduction device), 该导热装置具有一平整的端面， 该导热装置以其本身的 平整的端面接触并且接合该半导体裸芯的背面； 以及
一保护层 (Protection layer), 该保护层包覆该基板的外露部分、 该半导体 裸芯的外露部分以及该导热装置与该半导体棵芯相接的端面的外露部分。
2. 如权利要求 1所述的集成电路封装， 进一步包含一外壳 (Casing), 该 外壳配合能容纳该散热模块、 该保护层以及该基板。
3. 如权利要求 2所述的集成电路封装， 其中该外壳具有一开口， 并且于 该开口内侧具有一^ ^合部位用以接合该基板。
4. 如权利要求 1所述的集成电路封装，其中该散热模块进一步包含至少 一散热鰭片（Heat-dissipating fm), 该至少一散热鳍片设置于该导热装置的一 周围。
5. 如权利要求 1所述的集成电路封装,其中该导热装置为一热导管 (Heat pipe)、 一热导柱 (Hot column)或由一高导热系数的材料所成形的柱体。
6. 如权利要求 1所述的集成电路封装，其中该半导体棵芯为一高功率集 成电路。
7. 如权利要求 1所述的集成电路封装，其中半导体棵芯藉由一倒装芯片 工艺 (Flip-chip process)固定于该基板的第一表面上。
8. 一种制造一集成电路封装 (Integrated circuit packaging)的方法， 该方法 包含下列步骤：
提供一基板 (Substrate),该基板具有一第一表面、一形成于该第一表面上 的内电路 (Inner circuit) ^ 一与该第一表面相对的第二表面以及一形成于该第 二表面上的外电路 (Outer circuit), 该外电路与该内电路形成电连接；
提供一半导体棵芯 (Semiconductor die), 该半导体棵芯具有一有源面、 多 个形成于该有源面上的焊垫 (Bond pad), 并且固定该半导体棵芯于该基板的 第一表面上， 以致该多个焊塾接触该内电路， 其中该半导体芯片并且具有一 与该有源面相对的背面；
提供一散热模块 (Heat-dissipating module), 该散热模块包含一导热装置 (Heat conduction device), 该导热装置于其本身的一末端处具有一平整的端 面；
形成一保护层 (Protection layer) , 该保护层大致包覆该基板的外露部分， 并且该保护层具有一开口（Opening)用以容纳该导热装置的端面； 以及
安置该导热装置的末端至该开口内， 将该导热装置以其本身的平整的端 面与该半导体棵芯的背面接触并且接合以完成该集成电路封装。
9.如权利要求 8所述的方法， 进一步包含一步骤：
藉由一外壳 (Casing), 容纳该散热模块、 该保护层以及该基板于其中。
10.如权利要求 9所述的方法， 其中该外壳具有一开口， 并且于该开口 内侧具有一" ^合部位用以接合该基板。
11.如权利要求 8所述的方法， 其中该散热模块进一步包含至少一散热 鳍片（Heat-dissipating fin), 该至少一散热鰭片设置于该导热装置的一周围。
12.如权利要求 8所述的方法， 其中该导热装置为一热导管 (Heat pipe)、 一热导柱 (Heat column)或由一高导热系数的材料所成形的柱体。
13. 如权利要求 8所述的方法，其中该半导体裸芯为一高功率集成电路。
14. 如权利要求 8 所述的方法， 其中半导体棵芯藉由一倒装芯片工艺 (Flip-chip process)固定于该基板的第一表面上。
15. 一种集成电路去于装(1111：68 1；6(1 circuit packaging), 包含：
一基板 (Substrate),该基板具有一第一表面、一形成于该第一表面上的内 电路 (Inner circuit), 一与该第一表面相对的第二表面以及一形成于该第二表 面上的外电路 (Outer circuit), 该外电路与该内电路形成电连接；
一保护层 (Protection layer), 该保护层位于该基板的第一表面上， 该保护 层具有一开口（Opening), 该内电路配置并且暴露于该开口内；
一半导体棵芯 (Semiconductor die)， 该半导体裸芯具有一有源面、 多个形 成于该有源面上的焊垫 (Bond pad)以及一与该有源面相对的背面， 该半导体 芯片固定于该保护层的开口内， 以致该多个焊垫接触该内电路， 并且一间隙 (Gap)存在于该半导体棵芯与该保护层之间； 以及
一散热模块 (Heat-dissipating module), 该散热模块包含一导热装置 (Heat conduction device), 该导热装置于其本身的一末端处具有一平整的端面， 该 导热装置以该末端安置入该开口内， 并且以其本身的平整的端面接触并且接 合该半导体棵芯的背面。
16. 如权利要求 15 所述的集成电路封装， 其中一导热胶 (Thermal adhesive)充填于该半导体棵芯与该保护层间的间隙。
17. 如权利要求 15所述的集成电路封装， 进一步包含一外壳 (Casing), 该外壳配合能容纳该散热模块、 该保护层以及该基板。
18. 如权利要求 17所述的集成电路封装， 其中该外壳具有一开口， 并且 于该开口内侧具有一^ ^合部位用以接合该基板。
19. 如权利要求 15所述的集成电路封装，其中该散热模块进一步包含至 少一散热鰭片（Heat-dissipating fin), 该至少一散热鰭片设置于导热装置的一 周围。
20. 如权利要求 15 所述的集成电路封装， 其中该导热装置为一热导管 (Heat pipe), 一热导柱 (Heat column)或由一高导热系数的材料所成形的柱体。
21. 如权利要求 15所述的集成电路封装，其中该半导体棵芯为一高功率 集成电路。
22. 如权利要求 15所述的集成电路封装，其中半导体芯片藉由一倒装芯 片工艺 (Flip-chip process)固定于该基板的第一表面上。
23. 一种制造一集成电路封装 (Integrated circuit packaging)的方法， 该方 法包含下列步骤：
提供一基板 (Substrate),该基板具有一第一表面、一形成于该第一表面上 的内电路 (Inner circuit), 一与该第一表面相对的第二表面以及一形成于该第 二表面上的外电路 (Outer circuit)， 该外电路与该内电路形成电连接；
成形一保护层 (Protection layer) , 该保护层大致覆盖该基板的第一表面并 且具有一开口（Opening), 该内电路配置并且暴露于该开口内；
提供一半导体棵芯 (semiconductor die), 该半导体棵芯具有一有源面、 多 个形成于该有源面上的焊垫 (Bond pad), 并且固定该半导体棵芯于该保护层 的开口内， 以致该多个焊垫接触该内电路， 并且一间隙 (Gap)存在于该半导体 棵芯与该保护层之间，其中该半导体棵芯并且具有一与该有源面相对的背面； 提供一散热模块 (Heat-dissipating module), 该散热模块包含一导热装置 (Heat conduction device), 该导热装置于其本身的一末端处具有一平整的端 面， 安置该导热装置的末端至该开口内； 以及
将该导热装置以其位在末端处的平整的端面接触并且接合该半导体棵 芯的背面以完成该集成电路封装。
24. 如权利要求 23所述的方法， 进一步包含一步骤：
充填一导热胶 (Thermal adhesive)于该半导体棵芯与该保护层间的间隙。
25. 如权利要求 23所述的方法， 进一步包含一步骤：
藉由一外壳 (Casing), 容纳该散热模块、 该保护层以及该基板于其中。
26. 如权利要求 25所述的方法， 其中该外壳具有一开口， 并且于该开口 内侧具有一^ ^合部位用以接合该基板。
27. 如权利要求 23 所述的方法， 其中该散热模块包含至少一散热鰭片 (Heat-dissipating fin), 该至少一散热鰭片设置于该导热装置的一周围。
28. 如权利要求 20所述的方法，其中该导热装置为一热导管 (Heat pipe)、 一热导柱 (Heat column)或由一高导热系数的材料所成形的柱体。
29. 如权利要求 23 所述的方法， 其中该半导体棵芯为一高功率集成电 路。
30. 如权利要求 23 所述的方法， 其中半导体棵芯藉由一倒装芯片工艺
(Flip-chip process)固定于该基板的第一表面上。
PCT/CN2006/001024 2005-05-18 2006-05-18 Conditionnement de circuit intégré et procédé de fabrication idoine WO2006122505A1 (fr)

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