JP2010147060A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2010147060A JP2010147060A JP2008319473A JP2008319473A JP2010147060A JP 2010147060 A JP2010147060 A JP 2010147060A JP 2008319473 A JP2008319473 A JP 2008319473A JP 2008319473 A JP2008319473 A JP 2008319473A JP 2010147060 A JP2010147060 A JP 2010147060A
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
【解決手段】本発明の半導体装置100は、回路基板2上に搭載された半導体チップ1の裏面から半導体チップ1の周方向に形成され、半導体チップ1と回路基板2との電気接続部を避けて設けられた伝熱体9を備えている。
【選択図】図2
Description
1a、1b 外部接続用パッド
2 回路基板
3a ボンディングワイヤ
3b バンプ
4 封止樹脂(封止部)
5 外部電極端子
6 絶縁層
7 接着剤
8 配線パターン(配線層)
9、9’ 伝熱体
10 アンダーフィル
11 開口
12 配線層
13 電源層
14 GND層
15 メタル層
100 半導体装置
101 半導体装置
200 半導体装置
300 半導体装置
400 半導体装置
500 半導体装置
600 半導体装置
600’ 半導体装置
700 半導体装置
800 半導体装置
900 半導体装置
Claims (10)
- 少なくとも1つの配線層を有する回路基板と、
前記回路基板上に搭載され、前記回路基板と電気的に接続された半導体チップと、
少なくとも前記半導体チップを封止樹脂によって被覆する封止部とを備えた半導体装置において、
前記半導体チップの裏面から半導体チップの周方向に形成され、半導体チップと回路基板との電気接続部を避けて設けられた伝熱体を備えることを特徴とする半導体装置。 - 前記伝熱体は、前記封止部によって被覆されていることを特徴とする請求項1に記載の半導体装置。
- 前記伝熱体を回路基板上に接着する接着層を備えており、
前記接着層が、熱伝導性を有することを特徴とする請求項1または2に記載の半導体装置。 - 前記伝熱体は、前記半導体チップと回路基板との電気接続部以外の領域に、開口が形成されており、
前記開口内に、前記封止樹脂が充填されていることを特徴とする請求項1、2、または3に記載の半導体装置。 - 前記伝熱体が、前記配線層に、電気的に接続されていることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。
- 前記伝熱体は、互いに電気的に独立した複数の領域に分割されていることを特徴とする請求項1〜5のいずれか1項に記載の半導体装置。
- 前記配線層は、前記各領域の伝熱体に対応して複数設けられており、
前記伝熱体の各領域は、互いに異なる配線層に電気的に接続されていることを特徴とする請求項6に記載の半導体装置。 - 前記伝熱体と接続された配線層が、GND層であることを特徴とする請求項5または7に記載の半導体装置。
- 前記回路基板の内部には信号配線として使用されていないメタル層を有することを特徴とする請求項1〜8のいずれか1項に記載の半導体装置。
- 前記メタル層が前記伝熱体と接続されていることを特徴とする請求項9に記載の半導体装置。
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JP2008319473A JP2010147060A (ja) | 2008-12-16 | 2008-12-16 | 半導体装置 |
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JP2008319473A JP2010147060A (ja) | 2008-12-16 | 2008-12-16 | 半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014090135A (ja) * | 2012-10-31 | 2014-05-15 | Namics Corp | 半導体装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008071934A (ja) * | 2006-09-14 | 2008-03-27 | Fujitsu Ltd | 半導体装置およびその製造方法 |
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- 2008-12-16 JP JP2008319473A patent/JP2010147060A/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008071934A (ja) * | 2006-09-14 | 2008-03-27 | Fujitsu Ltd | 半導体装置およびその製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014090135A (ja) * | 2012-10-31 | 2014-05-15 | Namics Corp | 半導体装置 |
CN104603935A (zh) * | 2012-10-31 | 2015-05-06 | 纳美仕有限公司 | 半导体装置 |
KR20150073950A (ko) * | 2012-10-31 | 2015-07-01 | 나믹스 코포레이션 | 반도체 장치 |
KR102094267B1 (ko) | 2012-10-31 | 2020-03-30 | 나믹스 코포레이션 | 반도체 장치 |
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