CN1357917A - 具整体封装包覆散热结构的覆晶结合模组 - Google Patents

具整体封装包覆散热结构的覆晶结合模组 Download PDF

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CN1357917A
CN1357917A CN 00134696 CN00134696A CN1357917A CN 1357917 A CN1357917 A CN 1357917A CN 00134696 CN00134696 CN 00134696 CN 00134696 A CN00134696 A CN 00134696A CN 1357917 A CN1357917 A CN 1357917A
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module
conjunction
brilliant
radiator structure
covers
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谢文乐
庄永成
黄宁
陈慧萍
蒋华文
张衷铭
涂丰昌
黄富裕
张轩睿
胡嘉杰
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HUATAI ELECTRONICS CO Ltd
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HUATAI ELECTRONICS CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种具整体封装包覆散热结构的覆晶结合模组。为提供一种简化生产过程、散热及固定效果好的封装集成电路板,提出本发明,它包括覆晶结合模组及散热结构;散热结构为以环氧树脂对整个覆晶结合模组整体包覆构成的包覆层。

Description

具整体封装包覆散热结构的覆晶结合模组
本发明属于封装集成电路板，特别是一种具整体封装包覆散热结构的覆晶结合模组。
在目前新一代的封装技术中以覆晶结合为主流，且多由其覆晶接技术组合应用延伸出各种高阶封装方式。然而如图1所示，覆晶结合封装的散热结构，其覆晶结合模组1’的基板11’下方系为若干锡球(Sold-er ball)111’，在基板1’上方为覆晶封装(填胶13’、凸块121’、晶片12’)，其散热结构系在晶片12’上方与底部涂散热胶/黏合胶14’及底缘接触面涂散胶/黏合胶15’的上盖型散热片16’黏合。
如图2所示，另一种习用的覆晶结合封装的散热结构，基板21’下方系为若干锡球(Sold-er ball)211’，其覆晶结合模组2’的基板21’上方为覆晶封装(填胶23’、凸块221’、晶片22’)，其散热结构系在晶片22’四周围设有高起的散热框271’，并在该散热框271’顶面盖设平板形散热板27’，为提高热源传递效率，在该平板形散热板27’与晶片22’接触面之间、平板形热板27’与散热框271’之间及散热框271’与基板21’之间分别涂以散热胶/黏合胶24’、25’及26’，以固定平板形散热板27’。
如图3所示，又另一种覆晶结合封装的散热结构，基板31’下方系为若干锡球(Sold-er ball)311’，其覆晶结合模组3’的基板31’上方为覆晶封装(填胶33’、凸块321’、晶片32’)，其散热结构系在晶片32’顶面覆盖散热板35’，为固定散热板35’及使晶片32’的热量得以传导出去，在散热板35’与晶片32’接触面涂以散热胶34’予以固定。
上述各种习知的覆晶结合模组1’、2’、3’的散热结构虽得以达到散热的功效，但此些散热结构的建立无法沿用原基台加工，导致整个模组必须移到另一生产线作业，使生产过程较繁复；且由于散热板的热传递主要须藉由晶片与散热片间的散热胶传导，其散热片与晶片其他部位并无接触，使得晶片的热量无法快速传出至散热片，影响散热功效；又由于其散热片与晶片之间夹着散热胶固定、甚至散热片与散热片之间亦使用散热胶来黏合，导致散热结构系由数种不同热膨胀系数的材料构成，在晶片高热的温度睛各材料的伸缩长度不同，造成结合上的严重问题。
本发明的目的是提供一种简化生产过程、散热及固定效果好的具整体封装包覆散热结构的覆晶结合模组。
本发明包括覆晶结合模组及散热结构；散热结构为以环氧树脂对整个覆晶结合模组整体包覆构成的包覆层。
其中：
整体包覆于覆晶结合模组的环氧树脂含有铜(Cu)、金(Au)、铝(Al)及银(Ag)等高导热/导电粒子成份。
覆晶结合模组系由带有锡球的基板及底部设有凸块的晶片结合构成，晶片以覆晶封装方式结合于基板上方，并于两者之间填设完全覆盖凸块的填胶。
覆晶结合模组系由带有锡球的导线架及底部设有凸块的晶片结合构成，晶片以覆晶封装方式结合于导线架上方，并于两者之间填设完全覆盖凸块的填胶。
由于本发明包括覆晶结合模组及散热结构；散热结构为以环氧树脂对整个覆晶结合模组整体包覆构成的包覆层。以环氧树脂整体直接封装覆晶结合模组构成散热结构，作业时可直接续用原基台加工(Molding)，不必移出原基台，省去移换作业线的过程及时间；并可直接将整个覆晶结合模组包覆，增加晶片模组热传导，有效提高固定性及散热性；并可避免因不同材料受高热后不同膨胀系数所造成不同伸缩而导致结合及应力上的问题，不仅简化生产过程，而且散热及固定效果好，从而达到本发明的目的。
图1、为习知具有散热结构封装集成电路板结构示意剖视图。
图2、为习知具有散热结构封装集成电路板结构示意剖视图。
图3、为习知具有散热结构封装集成电路板结构示意剖视图。
图4、为本发明结构示意剖视图。
下面结合附图对本发明进一步详细阐述。
如图4所示，本发明包括覆晶结合模组1及覆盖整个覆晶结合模组1构成的散热结构41。
覆晶结合模组1系由带有锡球111的基板11及底部设有凸块211的晶片21结合构成，晶片21以覆晶封装方式结合于基板11上方，并于两者之间填设完全覆盖凸块211的填胶31。
散热结构41为由添加铜(Cu)、金(Au)、铝(Al)及银(Ag)等高导热/导电粒子成份的环氧树脂对整个覆晶模组1整体包覆构成的包覆层。藉由环氧树脂与晶片21直接接触以缩短热传导路径，提高散热效果。
亦可以导线架取代基板。
本发明以环氧树脂直接封装覆晶结合模组，作业时可直接续用原基台加工(Molding)，不必移出原基台，省去移换作业线的过程及时间；并可直接将整个覆晶结合模组包覆，增加晶片模组热传导，有效提高固定性及散热性；并可避免因不同材料受高热后不同膨胀系数所造成不同伸缩而导致结合及应力上的问题。

Claims (4)

1、一种具整体封装包覆散热结构的覆晶结合模组，它包括覆晶结合模组及散热结构；其特征在于所述的散热结构为以环氧树脂对整个覆晶结合模组整体包覆构成的包覆层。
2、根据权利要求1所述的具整体封装包覆散热结构的覆晶结合模组，其特征在于所述的整体包覆于覆晶结合模组的环氧树脂含有铜(Cu)、金(Au)、铝(Al)及银(Ag)等高导热/导电粒子成份。
3、根据权利要求1或2所述的具整体封装包覆散热结构的覆晶结合模组，其特征在于所述的覆晶结合模组系由带有锡球的基板及底部设有凸块的晶片结合构成，晶片以覆晶封装方式结合于基板上方，并于两者之间填设完全覆盖凸块的填胶。
4、根据权利要求1或2所述的具整体封装包覆散热结构的覆晶结合模组，其特征在于所述的覆晶结合模组系由带有锡球的导线架及底部设有凸块的晶片结合构成，晶片以覆晶封装方式结合于导线架上方，并于两者之间填设完全覆盖凸块的填胶。
CN 00134696 2000-12-06 2000-12-06 具整体封装包覆散热结构的覆晶结合模组 Pending CN1357917A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100447989C (zh) * 2005-05-18 2008-12-31 新灯源科技有限公司 集成电路封装及其制造方法
CN101465345B (zh) * 2007-12-19 2013-01-09 富士迈半导体精密工业（上海）有限公司 光源装置的制造方法
CN108346630A (zh) * 2017-01-25 2018-07-31 矽品精密工业股份有限公司 散热型封装结构
CN111063661A (zh) * 2019-12-16 2020-04-24 东莞记忆存储科技有限公司 倒装芯片封装方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100447989C (zh) * 2005-05-18 2008-12-31 新灯源科技有限公司 集成电路封装及其制造方法
CN101465345B (zh) * 2007-12-19 2013-01-09 富士迈半导体精密工业（上海）有限公司 光源装置的制造方法
CN108346630A (zh) * 2017-01-25 2018-07-31 矽品精密工业股份有限公司 散热型封装结构
CN111063661A (zh) * 2019-12-16 2020-04-24 东莞记忆存储科技有限公司 倒装芯片封装方法

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