CN101887886A - 一种多芯片封装及制造方法 - Google Patents

一种多芯片封装及制造方法 Download PDF

Info

Publication number
CN101887886A
CN101887886A CN2010101299313A CN201010129931A CN101887886A CN 101887886 A CN101887886 A CN 101887886A CN 2010101299313 A CN2010101299313 A CN 2010101299313A CN 201010129931 A CN201010129931 A CN 201010129931A CN 101887886 A CN101887886 A CN 101887886A
Authority
CN
China
Prior art keywords
chip
dish
packaging body
lead frame
mounts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010101299313A
Other languages
English (en)
Inventor
蒋航
杨先庆
邢正人
任远程
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Monolithic Power Systems Co Ltd
Original Assignee
Chengdu Monolithic Power Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Monolithic Power Systems Co Ltd filed Critical Chengdu Monolithic Power Systems Co Ltd
Publication of CN101887886A publication Critical patent/CN101887886A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明公开了一种散热型的多芯片封装。在该封装体中，引线框架的一部分被弯曲使得部分表面暴露于封装体外。在该暴露面的反面贴装有功率芯片。这样，功率芯片的热量能容易地向外散发。

Description

一种多芯片封装及制造方法
技术领域
本发明涉及集成电路封装，具体涉及利于散热的多芯片封装。
背景技术
在反激式变换器的离线应用场合，开关器件和控制电路倾向于制作在同一个封装体内以减小系统尺寸和提高性能。然而，开关器件产生较多的热量。为了使控制电路进行可靠的工作，开关器件产生的热量必须及时散发出去。也就是说，含功率器件和普通器件的封装体必须有良好的散热性。
图1示出了传统的小外形封装（SOP）应用。在封装体10内，功率芯片11和普通芯片12固定在引线框架16上。芯片之间以及芯片和引线框架16之间通过焊盘17上制作的引线15进行连接和信号传递。芯片、引线框架16和引线15的外面用封装材料13包封，而引脚14的一部分露出引线框架16外形成外露引脚141。该封装体10内功率器件产生的热量主要通过两条途径向外散发。一个是通过封装材料13散发。另一个是通过引脚14及其外露引脚141向外散发。封装材料13的散热通常并不理想，因为封装材料13一般都不是良好的热传导体，没有金属的导热性好。此外，外露引脚141的截面积太小，散热能力也不高。在这种封装方式中，由于热量不能有效地向外散发，功率芯片11将形成高温结影响系统工作的可靠性。另外，外露引脚141上的高温还会影响外露引脚141与印刷电路板的连接强度。因此，对于含功率器件的多芯片封装体而言，需要提供一种具有更好散热性能的封装方式。
发明内容
本发明公开了一种多芯片封装体，它包含功率芯片、普通芯片、功率芯片贴装盘和普通芯片贴装盘，其中功率芯片贴装到功率芯片贴装盘，普通芯片贴装到普通芯片贴装盘。所述功率芯片比所述普通芯片消耗更多的能量。功率芯片贴装盘、普通芯片贴装盘、功率芯片和普通芯片被封装材料包封，将功率芯片贴装盘的背面暴露于封装材料的表面形成散热面。其中功率芯片贴装盘和普通芯片贴装盘位于封装体内不同的深度。
在一个实施例中，功率芯片包含开关器件集成电路。普通芯片包含控制器件集成电路，控制功率芯片的运行。
该封装体中的引线框架可包括基体部分、暴露部分和倾斜部分，其中基体部分包含普通芯片贴装盘和引脚，暴露部包含功率芯片贴装盘，功率芯片贴装盘的一表面暴露在封装材料表面。
倾斜部分用于连接基体部分和暴露部分。其中基体部分平面和暴露部分平面相互平行且距离大于零。引线框架材料可采用铜。
在一种实施方式中，引线框架的外露引脚伸展方向和功率芯片贴装盘的散热面朝向相反。这样，散热面可以方便地和热沉等散热体接触。在另一种实施方式中，外露引脚伸展方向也可以和功率芯片贴装盘的散热面朝向相同。这样，散热面也可以和印刷电路板接触，通过印刷电路板上的覆铜等导热层实现散热。
本发明也保护了一种引线框架，包括基体部分和暴露部分，其中基体部分包括至少一个芯片贴装盘，被封装材料包封；暴露部分也包括至少一个芯片贴装盘，一面贴装芯片并位于所述封装材料内，另一面暴露于封装材料表面。
本发明还保护一种多芯片封装制造方法，它包括制造引线框架，其中功率芯片贴装盘和普通芯片贴装盘位于不同深度；将芯片贴装到芯片贴装盘；制作引线；将引线框架、芯片和引线用封装材料包封以及切筋成形。在一种实施方式中，引线框架采用压模成型技术将功率芯片贴装盘和普通芯片贴装盘制作于不同深度。
本发明采用上述封装结构和/或方法，使含功率器件的多芯片封装体具有更好的散热性能，其运行可靠性更高。
附图说明
图1示出了现有技术的SOP封装结构。
图2示出了本发明的一种散热型封装的截面图。
图3示出了图2中封装体的立体图。
图4为本发明的封装前多个芯片放置于引线框架上的俯视图实施例。
图5示出了本发明的一个散热型封装的应用实施例，该实施例中使用了散热器。
图6示出了另一种通过印刷电路板散热的应用实施例。
图7示出了普通芯片可位于封装体内的不同深度。
图8示出了本发明的一个引线框架实施例，该引线框架被弯曲使功率芯片贴装盘位于封装体表面。
图9示出了本发明的散热型封装的一个制造流程图实施例。
图10为本发明的一个引线框架压模制造方法的示意图。
具体实施方式
图2为本发明的一个散热型封装体20实施例的截面示意图。图3示出了其对应的立体图。封装体20包括一个引线框架26（其外露引脚241位于封装体20外）、至少一个普通芯片22和至少一个功率芯片21。其中功率芯片21比普通芯片22产生更多的热量。这里的“芯片”是指在半导体基底上制作有集成电路的微型电子器件，亦称“裸片”。在一个实施方式中，普通芯片22含控制器件，用于控制功率芯片21的工作状态，其中功率芯片21可包含功率开关等功率器件。引线框架26包含功率芯片贴装盘211、普通芯片贴装盘221、引脚24和连接结构等。
引线框架26的功率芯片贴装盘211的一表面贴装有功率芯片21，另一表面203暴露在封装体20的表面。这样，功率芯片21被拉到靠近封装体20的表面，而普通芯片22则保留在封装体20的内部。这里的功率芯片21指消耗相对较多功耗的集成电路裸芯片，普通芯片22指消耗相对较少功耗的集成电路裸芯片。功率芯片贴装盘211暴露于封装体20外的散热面203可从图3看到。
在一个实施方式中，引线框架26的材料为具有良好热传导性的金属，例如铜。在本发明中，封装体20内的芯片不位于同一深度，其中功率芯片21位于封装体20表面，并使功率芯片贴装盘211的背面裸露在封装体20表面形成散热面203，而普遍芯片22则位于封装体20内部，比如封装体20的中心平面附近。这里的“背面”指芯片贴装盘的贴装芯片一面的相反面。相应地，引线框架26的功率芯片贴装盘211部分和引线框架26的其它部分位于不同水平面上，参见图2的截面图。这里的功率芯片21可为电压变换器，它产生的热量可容易地通过具有良好热传导性的功率芯片贴装盘211向外散发。而能耗较小的普通芯片22和普通芯片贴装盘221被封装材料23包封在封装体20内部。这样，普通芯片22附近温度较低，确保了普通芯片22内部的控制器件具有良好的机械可靠性和电可靠性。
此外，在一种实施方式中，芯片上的一部分焊盘27通过互连如引线25和引线框架26连接，实现芯片和外部电路进行联系。芯片上的另一部分焊盘27通过引线25在功率芯片21和普通芯片22之间进行连接，实现普通芯片22和功率芯片21之间的信号传递。在另一种实施方式中，封装体20内的芯片之间也可以分别通过互连如引线25在芯片焊盘27和引线框架26进行连接，再由引线框架26自身的连接实现。功率芯片21、普通芯片22、引线框架26的一部分和引线25一起被封装材料23包封，露出功率芯片贴装盘211的背面203和引脚24的外露引脚241部分，之后封装材料23被成型，形成封装体20。在一个实施例里，功率芯片21可以为两个或更多，功率芯片21可贴装在同一功率芯片贴装盘211上，也可贴装在不同的功率芯片贴装盘211上。普通芯片22也可以为多个，贴装在同一个或不同的普通芯片贴装盘221上。
图4所示为包封前芯片贴装在引线框架26上的俯视图实施例。引线框架26如斜线填充的部分所示。该引线框架26包括功率芯片贴装盘211、普通芯片贴装盘221、引脚24和其余的支撑连接结构461。支撑连接结构461也可包括封装过程中用于支撑引线框架26的熔柄462。功率芯片21贴装在功率芯片贴装盘211上。功率芯片21表面制作有焊盘27。普通芯片22贴装在普通芯片贴装盘221上。普通芯片22表面也制作有焊盘27。一部分焊盘27通过互连如引线25和引线框架26的引脚24连接，实现芯片和外部电路的电连接。另一部分焊盘27通过互连如引线25在不同的芯片间进行电互连。在本发明中，功率芯片贴装盘211和引线框架26的其它部分位于不同的深度上。从该俯视图角度看，功率芯片贴装盘211的位置比引线框架26的其它部分更低，使功率芯片贴装盘211的背面露出封装材料23表面。虚线框45所示部分为封装材料包封区域，封装材料23将普通芯片贴装盘221、功率芯片21、普通芯片22和引线25完全包封；封装材料23将功率芯片贴装盘211部分包封，留出贴装芯片面的背面露出在封装材料23外面。
图5所示为本发明的散热型封装体20的一个应用实施例。在这个实施例中，功率芯片贴装盘211的散热面203和一个散热器51接触以利更好地散热。在这个实施方式中，外露引脚241的伸展方向和散热面203朝向相反。外露引脚241可为表面贴装式的，也可为直插或针脚式的。在图示的应用中，该系统包含散热型封装体20，散热器51和印刷电路板52。印刷电路板52的上表面522和封装体20接触。外露引脚241插入印刷电路板的过孔520，与印刷电路板52的下表面521连接。在这个实施例中，封装体20的外露引脚241在图示中向下弯曲，和散热面203的朝向相反以利散热器51和散热面203的接触。在一种实施方式中，散热面203和散热器51之间还可放置一层导热膜，使得接触更加完全，导热更加有效。封装体20也可以采用表面贴装型引脚，引脚与散热面方向亦相反，印刷电路板与引脚接触的表面印刷有导线。封装体20还可以采用球栅阵列引脚，将导体球种植在封装体20上与散热面203相反的表面。除了散热器，其它的散热板也可以使用在该应用系统中。
图6示出了本发明的另一个散热型封装体应用实施例。该实施例中散热面203和印刷电路板上制作的导热层接触。这样，功率芯片21通过散热面203和印刷电路板62上的导热层散发热量，在一种实施方式中，该导热层采用覆铜实现。该实施例中外露引脚241伸展方向和散热面203朝向一致。在一种实施方式中，见图6，封装体采用表面贴装型的小外形封装（SOP）。从图中可见，外露引脚241和散热面203朝向一致，使得封装体的散热面203和印刷电路板62的上表面611的导热层接触。电路可以印制在印刷电路板62的任一面或两面。外露引脚241可采用贴装式、针脚式或球栅阵列式。在这个实施例中，印刷电路板和散热面203之间也可放置导热膜以提高导热性能。
前面举例了普通芯片22位于封装体的中心平面的实施例，在不同的实施例中，普通芯片22也可位于封装体20的其它深度内，如图7所示。
图8示出了本发明的引线框架实施例，该引线框架中的至少一个芯片贴装盘和其它部分位于不同的深度内。图8为图4中沿A-A线的局部剖面图。该引线框架包括3个部分，分别为裸露部分801、倾斜部分802和基体部分803。裸露部分801一般为一个或多个功率芯片贴装盘。倾斜部分802一般作为连接部分连接基体部分803和裸露部分801，并与基体部分803和裸露部分801呈一个角度，其中裸露部分801平面和基体部分803平面相互平行。基体部分803为引线框架的其余部分，包括普通芯片贴装盘、引脚等。此外，如图所示，引线25连接功率芯片21上的焊盘27和基体部分803上的焊盘。裸露部分801可包含多个功率芯片贴装盘，每个功率芯片贴装盘也可贴装一至多个功率芯片。
图9所示为本发明的一个散热型封装体的制作工艺流程图实施例。在步骤901，制作引线框架，其中用于放置功率芯片的芯片贴装盘和放置普通芯片的芯片贴装盘位于不同的水平面并相互平行。如图中实施例所示，引线框架包含芯片贴装盘、引脚和连接柄。引线框架还可包括工艺中暂时起支撑作用的熔柄。功率芯片贴装盘是用于贴装功率芯片的承载座，其中功率芯片比封装体内的其它集成电路芯片消耗的能量高。与其它普通芯片贴装盘处于不同深度的功率芯片贴装盘可通过简单的压模成型实现，参加图10所示实施例。引线框架的水平基架260放置于成啮合关系的上模101和下模102之间。当给上模101一个冲压力后，引线框架26的功率芯片贴装盘部分被冲压到与其它部分平行的处于不同深度的位置。从图上看，功率芯片贴装盘处于引线框架26的下部分段261。功率芯片贴装盘的下压使得它的外表面能暴露于封装体外以利于散热。功率芯片贴装盘的下移也可以采用其它的方法实现。在一个实施例中，功率芯片贴装盘和引线框架基底平面间的距离取决于机械强度要求，封装参数和其它因素。
在步骤902，将芯片贴装到芯片贴装盘上。其中，功率芯片贴装到功率芯片贴装盘上，普通芯片贴装到普通贴装盘上。参加图10，功率芯片贴装到引线框架26下部分段261的上表面。功率芯片贴装盘和普通芯片贴装盘的不同深度决定功率芯片和普通芯片的贴装深度的不同。
在步骤903，引线耦接，将芯片间或芯片与引线框架间的焊盘通过引线耦接。该引线一般为金丝，也可为铝丝或其它材料。引线耦接使得芯片之间或芯片和外部电路之间实现电互连。
在步骤904，引线框架的主体部分、芯片和引线被封装材料包封，同时封装材料成型，将外露引脚和功率芯片贴装盘的背面露出封装材料表面。封装材料可为塑料或陶瓷。
在步骤905，对引线框架的外露出封装材料的外露引脚进行切筋成形，形成封装体成品。
在其它的实施例中，芯片贴装盘可不作为引线框架的一部分，通过其它的成型方式和固定技术使功率芯片和普通芯片处于不同的深度，其中部分芯片贴装盘的外表面暴露于封装体外。或可以理解为使用多个引线框架实现芯片贴装盘的不同深度，如使用两层引线框架，其中一层引线框架包含普通芯片贴装盘和引脚；另一层引线框架包含功率芯片贴装盘。在制作互连和封装过程中，两层引线框架固定于不同的水平来实现功率芯片贴装盘暴露于封装材料表面，而普通芯片和普通芯片贴装盘则位于封装材料的内部。

Claims (21)

1.一种多芯片封装体，包含至少两个芯片、至少两个芯片贴装盘和封装材料，其中所述芯片贴装于所述芯片贴装盘上，所述芯片和所述芯片贴装盘被封装材料包封，并使部分所述芯片贴装盘的背面暴露于所述封装材料表面。
2.如权利要求1所述的封装体，其特征在于：
所述至少两个芯片包含至少一个功率芯片和至少一个普通芯片，所述功率芯片比所述普通芯片消耗更多的能量；
所述芯片贴装盘包含至少一个功率芯片贴装盘用于贴装所述功率芯片，以及至少一个普通芯片贴装盘用于贴装所述普通芯片，其中所述功率芯片贴装盘的背面暴露于所述封装材料表面形成散热面。
3.如权利要求2所述的封装体，其特征在于，所述功率芯片包含开关器件。
4.如权利要求2所述的封装体，其特征在于，所述普通芯片包含控制器件，控制所述功率芯片的运行。
5.如权利要求2所述的封装体，其特征在于，所述普通芯片贴装盘位于封装体中心平面附近。
6.如权利要求2所述的封装体，其特征在于包括引线框架，所述引线框架包括所述功率芯片贴装盘、所述普通芯片贴装盘、引脚和连接结构。
7.如权利要求6所述的封装体，其特征在于，所述引线框架包括：
基体部分，包含所述普通芯片贴装盘和所述引脚； 
暴露部分，包含所述功率芯片贴装盘，其中所述功率芯片贴装盘的一表面暴露于所述封装材料表面；
倾斜部分，连接所述基体部分和暴露部分；
其中所述基体部分平面和所述暴露部分平面相互平行且距离大于零。
8.如权利要求6所述的封装体，其特征在于，所述引线框架材料为铜。
9.如权利要求6所述的封装体，其特征在于，所述功率芯片上的一部分焊盘和所述普通芯片上的一部分焊盘通过引线耦接，所述功率芯片和所述普通芯片上的另一部分焊盘和所述引线框架通过引线耦接。
10.如权利要求6所述的封装体，其特征在于，所述功率芯片和所述普通芯片上的焊盘和所述引线框架通过引线耦接。
11.如权利要求6所述的封装体，其特征在于，所述引脚包括露出于封装体材料外的外露引脚，该外露引脚伸展方向和所述散热面朝向相反。
12.如权利要求11所述的封装体，其特征在于，所述散热面和散热器接触。
13.如权利要求12所述的封装体，其特征在于，所述散热面和所述散热器之间有导热膜。
14.如权利要求6所述的封装体，其特征在于，所述引脚包括露出封装材料外的外露引脚，该外露引脚的伸展方向和所述散热面朝向相同。
15.如权利要求14所述的封装体，其特征在于，所述散热面和固定封装体的印刷电路板的一个表面接触。
16.如权利要求15所述的封装体，其特征在于，所述散热面和所述印刷电路板的一个表面之间有导热膜。
17.如权利要求11或14所述的封装体，其特征在于，所述封装体为直插式、针脚式、表面贴装式或球栅阵列式。
18.一种引线框架，包括：
基体部分；
暴露部分，一表面暴露于封装材料表面；
其中所述基体部分平面和所述暴露部分平面相互平行且距离大于零。
19.如权利要求18所述的引线框架，其特征在于，所述暴露部分包括至少一个芯片贴装盘，所述芯片贴装盘一面贴装芯片并位于所述封装材料内，另一面暴露于所述封装材料表面；所述基体部分包括至少一个芯片贴装盘，被所述封装材料包封。
20.一种多芯片封装制造方法，包括：
制造含至少两个芯片贴装盘的引线框架，其中所述至少两个芯片贴装盘处于相互平行的不同水平面上；
将芯片贴装到所述芯片贴装盘；
制作互连；
将所述引线框架、所述芯片和所述互连用封装材料包封，其中部分芯片贴装盘背面和所述引线框架的外露引脚暴露于所述封装材料表面；
将外露引脚切筋成形。
21.如权利要求20所述的制造方法，其中所述引线框架采用压模成型技术使所述芯片贴装盘处于相互平行的不同水平面上。
CN2010101299313A 2009-04-06 2010-03-23 一种多芯片封装及制造方法 Pending CN101887886A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/419,212 2009-04-06
US12/419,212 US20100252918A1 (en) 2009-04-06 2009-04-06 Multi-die package with improved heat dissipation

Publications (1)

Publication Number Publication Date
CN101887886A true CN101887886A (zh) 2010-11-17

Family

ID=42825490

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010101299313A Pending CN101887886A (zh) 2009-04-06 2010-03-23 一种多芯片封装及制造方法

Country Status (3)

Country Link
US (1) US20100252918A1 (zh)
CN (1) CN101887886A (zh)
TW (1) TW201041097A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103875060A (zh) * 2011-08-16 2014-06-18 先进模拟科技公司 具有一个或更多个嵌入的芯片垫的多芯片半导体封装体
CN105118818A (zh) * 2015-07-20 2015-12-02 东南大学 一种方形扁平无引脚封装结构的功率模块
CN109727943A (zh) * 2019-02-27 2019-05-07 无锡新洁能股份有限公司 一种具有低热阻的半导体器件封装结构及其制造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8283758B2 (en) * 2010-12-16 2012-10-09 Monolithic Power Systems, Inc. Microelectronic packages with enhanced heat dissipation and methods of manufacturing
CN103762214B (zh) * 2014-01-24 2016-08-17 矽力杰半导体技术(杭州)有限公司 应用于开关型调节器的集成电路组件
CN104900780B (zh) * 2014-03-06 2017-06-23 刘胜 Led卷对卷封装模组
JP6345583B2 (ja) * 2014-12-03 2018-06-20 ルネサスエレクトロニクス株式会社 半導体装置
CN105023922A (zh) * 2015-07-31 2015-11-04 天水华天科技股份有限公司 一种热沉结构双载体led驱动电路封装件及其制造方法
US10553524B2 (en) * 2017-10-30 2020-02-04 Microchip Technology Incorporated Integrated circuit (IC) die attached between an offset lead frame die-attach pad and a discrete die-attach pad
US11081455B2 (en) * 2019-04-29 2021-08-03 Infineon Technologies Austria Ag Semiconductor device with bond pad extensions formed on molded appendage

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030011054A1 (en) * 2001-06-11 2003-01-16 Fairchild Semiconductor Corporation Power module package having improved heat dissipating capability

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582013B2 (ja) * 1991-02-08 1997-02-19 株式会社東芝 樹脂封止型半導体装置及びその製造方法
US6831352B1 (en) * 1998-10-22 2004-12-14 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
US6677672B2 (en) * 2002-04-26 2004-01-13 Semiconductor Components Industries Llc Structure and method of forming a multiple leadframe semiconductor device
CN100490140C (zh) * 2003-07-15 2009-05-20 飞思卡尔半导体公司 双规引线框
JP2005129900A (ja) * 2003-09-30 2005-05-19 Sanyo Electric Co Ltd 回路装置およびその製造方法
KR101037246B1 (ko) * 2004-10-18 2011-05-26 스태츠 칩팩, 엘티디. 멀티 칩 리드 프레임 패키지
US8395251B2 (en) * 2005-05-12 2013-03-12 Stats Chippac Ltd. Integrated circuit package to package stacking system
US7868432B2 (en) * 2006-02-13 2011-01-11 Fairchild Semiconductor Corporation Multi-chip module for battery power control

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030011054A1 (en) * 2001-06-11 2003-01-16 Fairchild Semiconductor Corporation Power module package having improved heat dissipating capability

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103875060A (zh) * 2011-08-16 2014-06-18 先进模拟科技公司 具有一个或更多个嵌入的芯片垫的多芯片半导体封装体
CN103875060B (zh) * 2011-08-16 2016-06-15 先进模拟科技公司 具有一个或更多个嵌入的芯片垫的多芯片半导体封装体
CN105118818A (zh) * 2015-07-20 2015-12-02 东南大学 一种方形扁平无引脚封装结构的功率模块
CN105118818B (zh) * 2015-07-20 2018-08-21 东南大学 一种方形扁平无引脚封装结构的功率模块
CN109727943A (zh) * 2019-02-27 2019-05-07 无锡新洁能股份有限公司 一种具有低热阻的半导体器件封装结构及其制造方法

Also Published As

Publication number Publication date
US20100252918A1 (en) 2010-10-07
TW201041097A (en) 2010-11-16

Similar Documents

Publication Publication Date Title
CN101887886A (zh) 一种多芯片封装及制造方法
US7196403B2 (en) Semiconductor package with heat spreader
CN100380636C (zh) 用于整体成型组件的热增强封装及其制造方法
US5065281A (en) Molded integrated circuit package incorporating heat sink
US6552428B1 (en) Semiconductor package having an exposed heat spreader
US7439099B1 (en) Thin ball grid array package
US20020038904A1 (en) Area array type semiconductor package and fabrication method
CN102420217A (zh) 多芯片半导体封装体及其组装
CN103378017A (zh) 高密度3d封装
KR19980058198A (ko) 버텀리드 반도체 패키지
CN206282838U (zh) 无源器件与有源器件的集成封装结构
CN106898591A (zh) 一种散热的多芯片框架封装结构及其制备方法
US20130099275A1 (en) Led package and method of making the same
CN103346136A (zh) 功率模块及其封装方法
CN103594432B (zh) 一种刚柔结合板的三维封装散热结构
CN201000882Y (zh) 内嵌导热绝缘体具散热片的新型半导体器件封装结构
JP2015106602A (ja) 半導体装置および半導体装置の製造方法
CN101740528B (zh) 增进散热的无外引脚式半导体封装构造及其组合
CN101882606B (zh) 散热型半导体封装构造及其制造方法
CN202034361U (zh) 一种半导体封装结构
CN108400218B (zh) 一种基于csp型式的led封装方法
CN212587519U (zh) 一种led晶元封装结构
CN115662965A (zh) 一种新型大功耗芯片封装结构及封装方法
CN115332195A (zh) 双面SiP封装结构及其制作方法
CN111710769A (zh) 一种led晶元封装结构及其制作工艺

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20101117