WO2006082785A1 - 多層プリント配線板 - Google Patents
多層プリント配線板 Download PDFInfo
- Publication number
- WO2006082785A1 WO2006082785A1 PCT/JP2006/301455 JP2006301455W WO2006082785A1 WO 2006082785 A1 WO2006082785 A1 WO 2006082785A1 JP 2006301455 W JP2006301455 W JP 2006301455W WO 2006082785 A1 WO2006082785 A1 WO 2006082785A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- filled via
- layer
- hole
- wiring board
- printed wiring
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to a multilayer printed wiring board, and more particularly to a build-up multilayer printed wiring board that can be suitably used for a package substrate for mounting an IC chip.
- an interlayer insulating resin is formed on both sides or one side of a core substrate in which a through hole is formed by a drill for interlayer conduction. These via holes are opened by laser or photoetching to form an interlayer resin insulation layer.
- a conductor layer is formed on the inner wall of the via hole by plating or the like, and a pattern is formed through etching or the like to create a conductor circuit.
- a build-up multilayer printed wiring board can be obtained by repeatedly forming an interlayer insulating layer and a conductor layer.
- a conductor layer (covering layer) covering the surface of the through-hole is provided, and a via hole is formed on the covering.
- a so-called stacked via structure in which a filled via filling a no-hole with a conductor and a field via is provided immediately above the filled via is used for shortening the wiring length.
- Patent Document 1 and Patent Document 2 are examples of a conventional build-up multilayer wiring board having a through hole provided with a cover layer and a prior art build-up multilayer wiring board having a filled via.
- Patent Document 1 Japanese Patent Laid-Open No. 2001-127435
- Patent Document 2 Japanese Patent Laid-Open No. 11-251749
- the via hole reliability is easily lowered, and it is difficult to reduce the via hole diameter.
- the conductor formed in the via hole and the lower layer conductor (land) The joint area between the via hole and the land decreased, and when the heat cycle test and the like were performed, the connection resistance tended to increase between the two.
- via holes in the build-up multilayer wiring board are formed by forming an electroless plating film and forming an electrolytic plating film. Since the electroless plating film formed earlier contains organic matter, hydrogen molecules, hydrogen atoms and the like and is brittle, it is considered that cracks are likely to occur in the electroless plating film. In addition, the electroless plating film has low ductility, so if the printed wiring board is warped when an IC chip or the like is mounted, the electroless plating film cannot follow the warping! / Easy to peel off!
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer print in which a filled via is formed immediately above a small-diameter filled via and connection reliability is not lowered. It is to provide a wiring board.
- the second filled via the second interlayer insulating layer formed immediately above the filled via (hereinafter referred to as the first filled via) of the first interlayer insulating layer.
- the bottom diameter of the filled via of the second interlayer insulating layer formed immediately above the filled via of the first interlayer insulating layer is made larger than the bottom diameter of the filled via of the first interlayer insulating layer.
- the amount of depression (the amount of depression of the upper end surface force) P1 is 7 m or less
- the amount of protrusion upper flatness as shown in FIG. 19 (B)).
- a via with a P2 of 7 m or less is defined as a filled via.
- the first filled via can be formed on the lid-like conductor layer (covered layer).
- the lid-like conductor layer When formed on the lid-like conductor layer, the physical properties of the insulating substrate that forms the through-hole and the core are different. Therefore, the lid-like conductor layer is greatly complicated and deformed. Large stress is likely to be applied.
- FIG. 7 shows a cross-sectional view of the multilayer printed wiring board 10
- FIG. 8 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG.
- the conductor circuit 34 is formed on the surface of the core substrate 30.
- the front surface and the back surface of the core substrate 30 are connected via a through hole 36.
- the through hole 36 includes lidded layers 36a and 36d constituting the through hole land, and a side wall conductor layer 36b, and the side wall conductor layer 36b is filled with a resin filler 37.
- Covered layer (through-hole land) 36a, 36d, interlayer resin insulation layer 50 with filled via 60 and conductor circuit 58 formed thereon, interlayer resin insulation layer 150 with filled via 160 and conductor circuit 158 formed therein Is arranged.
- a solder resist layer 70 is formed above the filled via 160 and the conductor circuit 158, and bumps 78U and 78D are formed on the filled via 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. Yes.
- solder bump 78 U on the upper surface side of the multilayer printed wiring board 10 is connected to the land 92 of the IC chip 90.
- the lower solder bump 78D is connected to the land 96 of the daughter board 94!
- FIG. 9A is a plan view of a capped layer (through-hole land) 36a.
- the opening for the through hole is formed with a drill between 0.08mm and 0.25mm.
- the lid capping layer 36a is formed in a circular shape, and the bottom of the filled via 60 on the lid plating layer 36a is formed inside the side wall conductor layer 36b.
- the bottom of filled via 60 is formed to have a diameter of dl (60) m.
- a filled via 160 formed in the upper interlayer insulating layer 150 of the filled via 60 shown in FIG. 6 has a diameter d2 (45 ⁇ m) at the bottom.
- FIG. 9B is a plan view of the capped layer (through-hole land) 36d.
- the lid capping layer 36d is formed in a dharma shape in which two semicircles are combined, and the bottom of the filled via 60 on the lid plating layer 36d is formed in a portion that is not above the through hole.
- the bottom of the key 60 is formed with a diameter dl (60) / zm.
- a filled via 160 formed immediately above the filled via 60 shown in FIG. 6 has a diameter d2 (45 ⁇ m) at the bottom.
- the capped layer does not have to be a part of a circle.
- the through holes can be arranged at a narrow pitch. Further, the through hole may be filled with the same material as that of the side wall conductor layer without being filled with the filler.
- 3D thermal stress simulation was performed by the finite element method (FEM). If the analytical structure contains a material with remarkable plastic 'creep characteristics, such as solder, a nonlinear thermal stress simulation considering the plastic' creep characteristics is required.
- FEM finite element method
- the multi-scaling (sub-modeling) method is used for the analysis of the mesh, and the calculated displacement is also used as the boundary condition of the sub-model divided by the mesh.
- the thermal stress during the thermal shock test applied to the micro-layer of the high-layer / high-density organic package was analyzed.
- the bottom of the filled via 160 formed in the second interlayer resin insulation layer 150 is more heat-treated than the bottom of the filled via 60 formed on the lid-like conductor layer (covered layer) 36d.
- the stress applied to is small.
- the bottom diameter d2 of the filled via 160 is made smaller than the bottom diameter dl of the filled via 60 formed on the lid-like conductor layers (covered layers) 36a, 36d.
- FIGS. 9C and 9D show the shape of another example of the lidded layer.
- a filled via 60 is formed on the side wall conductor layer 36b in the circular lidded layer 36a.
- a fill via 60 is formed on the upper side of the sidewall conductor layer 36b in the Dalma-type lidded layer 36d.
- 9G shows the form of the filled via on the land 36e, and the land 36e of the filled via is connected to the covering layer 36a and the through-hole side wall conductor layer 36b by the wiring 12. Even in such a case, it is desirable that the fill via 60 be larger than the diameter of the filled via 160 in order to improve the connection reliability.
- the roughening surface 36a is formed on the sidewall conductor layer 36b and the surface of the through hole 36 by performing the original processing (FIG. 1D).
- filler 37 containing copper particles with an average particle size of 10 ⁇ m is screen-printed on through-hole 36 Fill, dry, and cure (Fig. 2 (A)). This is applied to the substrate on which a mask having an opening in the through hole portion is placed by a printing method so that the through hole is filled, and after filling, dried and cured.
- the filler 37 protruding from the through hole 36 was removed by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rigaku), and this belt support was further removed.
- the surface of the substrate 30 is flattened by performing puff polishing for removing scratches caused by the base polishing (see FIG. 2B). In this way, the substrate 30 is obtained in which the side wall conductor layer 36b of the through hole 36 and the resin filler 37 are firmly adhered to each other through the rough coating layer 36a.
- An electroless copper having a thickness of 0.6 m is formed by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate 30 flattened in the above (3) and applying electroless copper plating.
- a plating film 23 is formed (see FIG. 2C).
- electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 24 having a thickness of 15 m, thickening the portion to become the conductor circuit 34, and filling the through hole 36.
- a portion to be a lidded layer (through-hole land) covering the filled filler 37 is formed (Fig. 2 (D)).
- 9 (A) if there is a side wall conductor layer 36b, the filled via 60 must be inside the side wall conductor layer 36b, and if the through hole is filled with the same material, Must be in opening 16.
- 9 (C) and 9 (D) the through hole is filled with the same material (for example, copper (a combination of electroless copper and electrolytic copper) or conductive paste). The filled via 60 is over the opening 16.
- the resin film for the interlayer resin insulation layer is subjected to main pressure bonding on the substrate under the conditions of a vacuum of 67 Pa, a pressure of 0.4 Mpa, a temperature of 85 ° C., a pressure bonding time of 60 seconds, and then at 170 ° C. for 40 minutes. Heat cured.
- the substrate after the above treatment was immersed in a neutralizing solution (manufactured by Shipley Co., Ltd.) and washed with water. Furthermore, by applying a palladium catalyst to the surface of the roughened substrate (roughness depth 3 m), catalyst nuclei are attached to the surface of the interlayer resin insulation layer and the inner wall surface of the filled via opening. I let you. That is, the above substrate is made of palladium chloride (PbC) and stannous chloride (SnC).
- PbC palladium chloride
- SnC stannous chloride
- the catalyst was applied by dipping in a catalyst solution containing 12 12 and depositing palladium metal.
- a commercially available photosensitive dry film is attached to the substrate on which the electroless copper plating film 52 is formed, a mask is placed, and the substrate is exposed with lOmjZcm 2 , and 0.8% sodium carbonate.
- a resist 54 having a thickness of 25 ⁇ m was provided (Fig. 4 (C)).
- the substrate 30 is washed and degreased with 50 ° C. water, washed with 25 ° C. water, further washed with sulfuric acid, and subjected to electrolytic plating under the following conditions. Electrolytic plating film 56 was formed (Fig. 5 (A)).
- the same processing as in (4) above was performed to form a rough surface 58 ⁇ on the surfaces of the conductor circuit 58 and the filled via 60.
- the thickness of the upper conductor circuit 58 was 15 m (FIG. 5 (C)).
- the upper conductor circuit may have a thickness of 5 to 25 / ⁇ ⁇ .
- an interlayer insulating layer 150 having an upper conductor circuit 158 and a filled via 160 was formed to obtain a multilayer wiring board (FIG. 5 ( D)).
- the filled via 160 was adjusted to have a diameter force of 5 ⁇ m on the bottom surface.
- solder resist composition 70 is applied to both sides of the multilayer wiring board at a thickness of 20 ⁇ m, and the conditions are 70 ° C for 20 minutes and 70 ° C for 30 minutes. After the drying process, a photomask with a thickness of 5 mm on which the pattern of the opening of the solder resist was drawn was brought into close contact with the solder resist layer 70, exposed to 1000 miZcm2 ultraviolet light, developed with DMTG solution, and 200 m A diameter opening 71 was formed (FIG. 6A).
- solder resist layer is cured by heating at 80 ° C for 1 hour, 100 ° C for 1 hour, 120 ° C for 1 hour, and 150 ° C for 3 hours, respectively. Then, a solder resist pattern layer having a thickness of 15 to 25 ⁇ m was formed.
- the substrate on which the solder resist layer 70 is formed is made of nickel chloride (2.3 X lO 'mol ZD, sodium hypophosphite (2.8 X 10—imolZD, sodium taenoate (1
- a single layer of tin or a noble metal layer may be formed.
- solder paste containing soot-lead is printed on the opening 71 of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed, and further the opening of the solder resist layer on the other surface
- solder bumps solder bodies
- solder bumps 78U and 78D are formed by reflowing at 200 ° C, and solder bumps 78U and 78D are provided.
- a multilayer printed wiring board was manufactured (Fig. 7).
- IC chip 90 is attached via solder bump 78U. Then, it is attached to the daughter board 94 via the solder bump 78D (FIG. 8).
- the bottom diameter of the first and second filled vias is adjusted by the laser conditions shown in step (10) above, and the formation position is adjusted to the land shape of the filled vias and the formation position on the land. This was done by inputting the data on the position where the hole was formed into the machine.
- the land shape of the first field via was adjusted by adjusting the mask pattern as described in the process (6) with reference to Fig. 2 (E).
- An IC chip was mounted on the multilayer printed wiring boards of Examples and Comparative Examples produced in this way, and then a sealing resin was filled between the IC chip and the multilayer printed wiring board to obtain a UC mounting board.
- the electrical resistance of the specific circuit through the IC chip (the electrical resistance between a pair of electrodes exposed on the surface opposite to the IC chip mounting surface of the IC mounting substrate and connected to the IC chip) is measured, and The value was taken as the initial value.
- a heat cycle test was performed on these IC-mounted substrates, with -55 degrees X 5 minutes and 125 degrees X 5 minutes as one cycle, and this was repeated 2500 times.
- the electrical resistance at the 500th, 1000th, 1250th, 1500th, 1750th, 2000th, and 2500th cycles was measured and the rate of change from the initial value (100 X (measured value initial value ) Z initial value (%;)) was determined. The results are shown in FIGS.
- Examples 121 to 240 were obtained.
- a heat cycle test was conducted. In this case, the electrolytic copper plating condition in the opening was set to 0.1 AZdm 2 .
- the evaluation results of Examples 120 to 240 are shown in FIGS.
- the second filled via and the surrounding insulating resin layer are not easily deformed so as to relieve the stress, so the stress during heating / cooling is the land of the first filled via (the land shape is (i), (iii) , (iv), the lid-like conductor layer is concentrated on the bottom of the first filled via, and it is assumed that the connection resistance increases due to the weak connection between the bottom of the first filled via and the land. ing.
- the insulating substrate 30 is formed with through holes having different physical properties such as Young's modulus, Poisson's ratio, and thermal expansion coefficient from the insulating substrate.
- the land shape of the first filled via, the position of the first filled via It is presumed that the stress applied between the bottom of the first filled via and the land changes depending on the presence of wiring between the land and the through hole. Since the physical properties of the through hole and the insulating substrate are different, the insulating substrate and the through hole are deformed differently.
- the bottom of the first filled via is covered on both sides, so the stress at the bottom of the first filled via is assumed to be greater than (i) to (iii).
- the first filled via is on the through-hole or on the insulating substrate, so that the heat cycle resistance is excellent.
- the bottom diameter of the first filled via Z and the bottom diameter of the second filled via are preferably 1.3 to 1.7. If this is within this range, the bonding force between the bottom of the second filled via and the surface of the first filled via is the run of the first filled via.
- FIG. 1 is a process diagram showing a method for producing a multilayer printed wiring board according to a first embodiment of the present invention.
- FIG. 2 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
- FIG. 3 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
- FIG. 4 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
- FIG. 5 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
- FIG. 6 is a process diagram showing a method for producing the multilayer printed wiring board according to the first embodiment.
- FIG. 7 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment.
- FIG. 8 is a cross-sectional view showing a state where an IC chip is placed on the multilayer printed wiring board according to the first embodiment.
- FIG. 9 is a plan view of a through hole lidded layer.
- FIG. 10 is a chart showing evaluation results of examples.
- FIG. 11 is a chart showing evaluation results of examples.
- FIG. 12 is a chart showing evaluation results of examples.
- FIG. 13 is a chart showing evaluation results of examples and comparative examples.
- FIG. 14 is a chart showing evaluation results of examples.
- FIG. 15 is a chart showing evaluation results of examples.
- FIG. 16 is a chart showing evaluation results of examples.
- FIG. 17 is a chart showing evaluation results of examples.
- FIG. 18 is a chart showing the evaluation results of the second example.
- FIG. 19 is an explanatory view showing filled vias in the present invention.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200680003852XA CN101112141B (zh) | 2005-02-02 | 2006-01-30 | 多层印刷线路板 |
KR1020097019066A KR20090104142A (ko) | 2005-02-02 | 2006-01-30 | 다층 프린트 배선판 |
EP06712598A EP1845762B1 (en) | 2005-02-02 | 2006-01-30 | Multilayer printed wiring board |
US11/832,673 US8003896B2 (en) | 2005-02-02 | 2007-08-02 | Multi-layer printed wiring board and manufacturing method thereof |
US13/156,715 US8800143B2 (en) | 2005-02-02 | 2011-06-09 | Multilayer printed wiring board and manufacturing method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005026898A JP2006216713A (ja) | 2005-02-02 | 2005-02-02 | 多層プリント配線板 |
JP2005-026898 | 2005-02-02 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/832,673 Continuation US8003896B2 (en) | 2005-02-02 | 2007-08-02 | Multi-layer printed wiring board and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
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WO2006082785A1 true WO2006082785A1 (ja) | 2006-08-10 |
Family
ID=36777169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/301455 WO2006082785A1 (ja) | 2005-02-02 | 2006-01-30 | 多層プリント配線板 |
Country Status (7)
Country | Link |
---|---|
US (2) | US8003896B2 (ja) |
EP (1) | EP1845762B1 (ja) |
JP (1) | JP2006216713A (ja) |
KR (3) | KR20100099351A (ja) |
CN (1) | CN101112141B (ja) |
TW (1) | TW200635471A (ja) |
WO (1) | WO2006082785A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016166855A (ja) * | 2015-03-09 | 2016-09-15 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 半導体装置及びその製造方法 |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101171894B (zh) * | 2005-06-30 | 2010-05-19 | 揖斐电株式会社 | 印刷线路板 |
WO2007004658A1 (ja) * | 2005-06-30 | 2007-01-11 | Ibiden Co., Ltd. | プリント配線板 |
US8314348B2 (en) | 2008-03-03 | 2012-11-20 | Ibiden Co., Ltd. | Multilayer printed wiring board and method of manufacturing multilayer printed wiring board |
KR101037505B1 (ko) * | 2009-01-07 | 2011-05-26 | 삼성전기주식회사 | 그라비아 인쇄법을 이용한 인쇄회로기판의 제조방법 |
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- 2006-02-03 TW TW095103772A patent/TW200635471A/zh unknown
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Also Published As
Publication number | Publication date |
---|---|
TW200635471A (en) | 2006-10-01 |
CN101112141B (zh) | 2012-05-30 |
EP1845762A1 (en) | 2007-10-17 |
EP1845762A4 (en) | 2009-11-18 |
US8003896B2 (en) | 2011-08-23 |
US8800143B2 (en) | 2014-08-12 |
US20080053693A1 (en) | 2008-03-06 |
US20110232086A1 (en) | 2011-09-29 |
CN101112141A (zh) | 2008-01-23 |
KR20100099351A (ko) | 2010-09-10 |
KR20070089887A (ko) | 2007-09-03 |
JP2006216713A (ja) | 2006-08-17 |
KR20090104142A (ko) | 2009-10-05 |
TWI331889B (ja) | 2010-10-11 |
EP1845762B1 (en) | 2011-05-25 |
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