Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G1/00—Details of arrangements for controlling amplification
  • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
  • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
  • H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45138—Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45572—Indexing scheme relating to differential amplifiers the IC comprising one or more Zener diodes to the input leads
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45616—Indexing scheme relating to differential amplifiers the IC comprising more than one switch, which are not cross coupled

Definitions

• the present invention relates generally to the front end systems.
• the present invention relates to a unified analog input front end apparatus and method.
• the analog input front end includes a configurable gain stage and an analog-to-digital converter.
• the configurable gain stage receives an analog input signal, such as a differential analog input signal, and provides a gain value to the analog input signal so as to output a gain-adjusted analog signal within a particular voltage range compatible with the input range of the Analog to Digital Converter.
• the analog-to-digital converter receives the gain-adjusted analog input signal and performs analog-to- digital conversion on the gain-adjusted analog input signal, so as to output a digital signal that is indicative of the analog input signal.
• Another aspect of the invention relates to a method of converting an analog input signal to a digital signal, which includes receiving, by a configurable gain stage, the analog input signal.
• the method also includes providing, by the configurable gain stage, a gain value to the analog input signal so as to output a gain-adjusted analog input signal that is within a particular voltage range between a maximum and a minimum value.
• the method further includes receiving, by an analog-to-digital converter, the gain-adjusted analog input signal output from the configurable gain stage.
• the method still further includes performing, by the analog-to-digital converter, analog-to-digital conversion on the gain-adjusted analog input signal, so as to output a digital signal that is indicative of the analog input signal.
• a configurable gain stage which includes a positive differential input signal stage that includes a first resistor having a first resistance value, a second resistor having a second resistance value, and a first operational amplifier.
• the configurable gain stage also includes a negative differential input signal stage that includes a third resistor having the first resistance value, a fourth resistor having the second resistance value, and a second operational amplifier.
• the configurable gain stage further includes first through sixth switches, the first and second switches being provided on the positive differential input signal stage, the third and fourth switches being provided on the negative differential input signal stage, the fifth switch being provided between the positive and negative differential input signal stages, and the sixth switch being provided between a ground potential and at least one of the positive and negative differential input signal stages.
• the configurable gain stage is capable of operating in a first mode of operation providing a gain value greater than unity to an T/US2005/035483
• a second mode of operation providing a unity gain value to the input differential signal pair
• a third mode of operation provide a gain value greater than zero but less than unity to the input differential signal pair
• the calibration circuit includes an operational amplifier, a digital-to-analog converter, a resistor ladder provided between the operational amplifier and the digital-to-analog converter, a voltage reference unit connected to the digital-to-analog converter and a plurality of switches that provide an on/off connection to the gain stage and the analog-to-digital converter unit.
• the calibration circuit is configured to maintain a total error of the gain stage and the analog-to-digital converter unit to be less than a predetermined value, for all operating modes of the gain stage and the analog-to-digital converter.
• Figure 1 is a circuit level diagram illustrating an overall topology of a unified analog input front end according to a first embodiment of the invention
• Figure 2 is a circuit level diagram illustrating the configurable gain stage portion of the unified analog input front end, with actual resistance values and capacitance values provided in a preferred configuration of the first embodiment
• Figure 3 is a circuit level diagram illustrating the configurable gain stage operating in attenuation mode
• Figure 4 is a circuit level diagram illustrating the configurable gain stage operating in unity gain mode
• Figure 5 is a circuit level diagram illustrating the configurable gain stage operating in positive gain mode
• Figure 6 is a block diagram illustrating an analog-to-digital converter that can be utilized according to a preferred configuration of the first embodiment
• Figure 7 is a block diagram illustrating the error effects on the system according to the first embodiment
• Figure 8 is a block diagram illustrating a calibration unit coupled to a unified analog input front end, according to a second embodiment of the invention.
• Figure 9 is a circuit level diagram illustrating the calibration unit according to a preferred configuration of the second embodiment.
• the unified analog input front end is a high-performance yet very general purpose analog signal processing and conversion circuit for data acquisition. It is configurable in real-time by way of digital commands which can set the unified analog input front end to perform analog-to- digital (A-to-D) conversion on input signals, such as differential signals, in a plurality of full-scale ranges.
• A-to-D analog-to- digital
• other full-scale ranges may be possible for a unified analog input front end made in accordance with the present invention.
• the unified analog input front end is capable of performing signal processing and conversion for analog input signals from D. C. up to a predetermined frequency.
• the predetermined frequency is 500 Hz, but of course it may be set to any desired frequency to suit a particular purpose, as known to one of ordinary skill in the art (e.g., a value between 50 Hz and 10 kHz).
• the unified analog input front is designed to have a 14 bit resolution and an accuracy of better than 1 % full scale. This is accomplished with a carefully developed and very flexible topology and by the use of custom designed components, such as ones manufactured by Maxim Integrated Products, Inc., and by Alpha, Inc.
• the unified analog input front end 100 includes a configurable gain stage 1 10 constructed of discrete components, and an analog-to-digital converter 120.
• the analog-to-digital converter 120 is a Max1338 A/D converter manufactured by Maxim Integrated Products, Inc., but one of ordinary skill in the art will recognize that other types of converters may ⁇ be utilized for the analog-to-digital converter 120 portion of the unified analog input front end 100, while remaining within the scope of the invention.
• variable full scale range discussed herein is a function of the Max 1338, and other types of A/D converters that may be utilized with a unified analog input front end according to an embodiment of the present invention may or may not have such a feature.
• the configurable gain stage 1 10 includes a first resistor R1 with a resistance value of 19R (R being a predetermined value), a second resistor R2 with a resistance value of R, a third resistor R3 with a resistance value of 7R, a first capacitor C1 with a capacitance value of C, a first Zener diode D1 , a first operational amplifier UI , a fourth resistor R4 with a resistance value of 19R, a fifth resistor R5 with a resistance value of R, a sixth resistor R6 with a resistance value of 7R, a second capacitor C2 with a capacitance value of C, a second Zener diode D2, and a second operational amplifier U2. Also included in the unified analog input front end 100 is a first switch S1 , a second switch S2, a third switch S3, a fourth switch S4, a fifth switch
• a positive differential input signal (of a differential input signal pair) is input to the first resistor R1
• a negative differential input signal (of the differential input signal pair) is input to the fourth resistor R4, whereby the unified analog input front end 100 is configured to determine a digital value corresponding to the differential input signal.
• the configurable gain stage 1 10 serves three basic purposes: a) to attenuate large signals which are beyond the A/D converter's 120 input signal range and that could damage the A/D converter 120, b) to amplify small signals which less than the input signal range of the A/D converter 120, and c) to serve as a high input impedance/low output impedance buffer for signal sources which may be attenuated by the relatively low input impedance (around 15K Ohm) of the A/D converter 120.
• the three different gain configurations of the configurable gain stage 1 10 are selectable by way of digitally controlled analog switches S1 - S6.
• R1 - R3 and R4 - R6 are preferably resistors custom-packaged in threes, such as ones sold by Alpha, Inc. In the preferred embodiment, each of the resistor packs meet a 19:1 :32 resistance ratio with 0.02% accuracy.
• OpAmps U1 and U2 are preferably high precision, low bias current, low offset voltage operational amplifiers.
• Capacitors C1 and C2 are 1 O pF capacitors in the preferred embodiment, whereby they are included so as to provide some filtering and oscillation protection to the OpAmps U1 and U2, while keeping the high end of the low-pass filter they create well above a predetermined frequency range.
• the predetermined frequency range (for signals input to the unified analog input front end 100) is D. C. (0 Hz) to 500 Hz, which is the range of signals the unified analog input front end 100 is designed to measure.
• FIG. 3 illustrates the topology of the configurable gain stage 1 10 when switched to attenuation mode, with a gain of 0.05, whereby actual resistance and capacitance values are shown in a preferred implementation of the configurable gain stage 1 10. This mode of operation is useful when the input voltage range is large, such as a ⁇ 200 V input range, whereby that large input range is collapsed to a ⁇ 10V input range that is suitable for input to an A/D.
• switches S1 , S4 and S6 are closed, while all of the other switches (S2, S3 and S5) are open.
• the switches S1 - S6 are represented by 5 ⁇ resistances, to represent the maximum on-resistance of the Maxim Max4665 switches that are used in the preferred implementation of the configurable gain stage 1 10.
• the configurable gain stage 1 10 functions as a voltage divider, whereby the gain of the configurable gain stage 1 10 is:
• G (G + + G-) / 2 + K (G + - G-) (7)
• K VincWVindiff, the ratio of input common mode to input differential.
• Gain Error is introduced by the tolerance of the resistors (0.02% tolerance for the resistors used in the preferred embodiment) and the resistance of the switches (3 - 5 ⁇ for the Max 4665 switches used in the preferred embodiment). From Equation #7, above, it can be seen that Gain Error can occur either as a result of an average error common to both the positive and negative differential legs (in the first term) or mismatched error proportional to the common mode ratio K (in the second term).
• G + MiN (32393.52 + 3 + 3) / (32393.52 _+ 615723.12 + 3 + 3)
• G-MAx (32406.48 + 5) / (615476.88 _+ 32406.48 + 5)
• G-MiN (32393.52+ 3) / (32393.52 _ + 615723.12 + 3)
• the largest error is dependent on the largest average error of the two legs for K ⁇ 0.5 (the point at which the negative leg is grounded).
• error is proportional to common mode, and becomes a limiting factor of common mode, based upon the percent of the error budget being used by offset in the configurable gain stage 1 10 and error figures of the A/D converter 120.
• This mode of operation is suitable when the input signal voltage range is in a proper range for input to an A/D, but where a high input impedance/low input impedance buffer is needed.
• the 32.4 k ⁇ resistor R2, R5 are not switched in as either a voltage divider or to create amplification around the operational amplifiers U1 and U2.
• the offset error in the preferred embodiment is:
• FIG. 5 shows the configurable gain stage 1 10 operating in the gain mode (gain > 1).
• This mode of operation is useful when the input voltage range is small, such as ⁇ 0.3125 V input range, whereby that small input range is expanded to a +2.5V input range that is suitable for input to the A/D 120.
• the negative side of the differential is coupled to ViN-, and the voltage is buffered through operational amplifier U1 with no gain.
• Switch S3 is closed, so that the low side of resistor R5 is attached to Vout-.
• operational amplifier U2 and resistors R5 and R6 act as a basic non-inverting amplifier. Instead of being referenced to ground, this amplifier is referenced to Vout-, which is equal to VIN-.
• the ideal gains for the configurable gain stage in the gain mode are:
• VOUT -H VIN- + (ViN + - VOUT) * 8 (18)
• Offset in the positive leg of the configurable gain stage 1 10 differs because of the 32.4 k ⁇ resistor R5 is switched in (by switches S3, S4 and S5 being closed), whereby negative current is split between the 32.4 k ⁇ resistor R5 and the 226.8 k ⁇ resistor R6. Also, since the error due to this combination is added to the output rather than to the input, it should be divided by gain to reference it to the input. The expression for offset is then computed as:
• Analog-to-Digital Converter 120 which forms part of the unified analog input front end 100.
• the Analog-to-Digital Converter 120 corresponds to an ACGO 4-Channel, 14-bit differential A-D converter in the preferred embodiment, but one of ordinary skill in the art will recognize that any type or model of A-D converter may be utilized, while remaining within the spirit and scope of the present invention.
• Figure 6 shows details of the ACGO A-D Converter 120.
• a track-and-hold circuit 610 allows all four channels to be sampled simultaneously and converted in sequence by a single block of conversion circuitry.
• a range selection circuit 620 which is implemented as a programmable gate array in the preferred embodiment, allows the A-D converter 120 to be configured for a plurality of different ranges on a channel-by-channel basis by way of digital commands (signals DO, DD input to the A-D Converter 120.
• the different ranges correspond to: ⁇ 10V, ⁇ 5V, ⁇ 2.5V, ⁇ 1.25V.
• One of ordinary skill in the art will recognize that the number of possible ranges, and the actual values of those ranges, may be different from the ones discussed above with respect to the preferred embodiment, while remaining within the spirit and scope of the invention.
• the 4x differential multiplexer 630 of the A-D Converter 120 of the preferred embodiment is capable of 83
• Error specifications for the A-D Converter 120 according to the preferred embodiment of the invention are provided by the manufacturer (Maxim) as end-to-end tolerances (mostly in LSB, or least significant bits), including errors resident in all stages of the A-D Converter 12O. Errors can be classified as either offset errors (errors independent of input and temperature) or gain errors (errors dependent upon input).
• Vos 2Vosopam P + (1 / (1 /615.6K + 1 /32.4K))(IBIAS ⁇ H- IOFF ⁇ ) (26) 005/035483
• Vos 2Vosopamp + 615.6K(IBIAS ⁇ + IOFF ⁇ ) + 226.8(IBIAS ⁇ + IOFF ⁇ ) (27 )
• G 8 mode:
• Vos 2Voso P amp + 615.6K(IBIAS ⁇ + IOFF ⁇ ) + 32.4(IBIAS ⁇ + IOFF ⁇ )
• Vosopamp is the specified offset voltage of the particular type of operational amplifiers used for operational amplifiers UI , U2, and where IBIAS ⁇ and IOFF ⁇ are the maximum expected differences in current considering the minimum current to be Zero (0) and the maximum current to be the datasheet "typical" specification value (0.5, 0.2 nA for the 4177 operational amplifier).
• IBIAS ⁇ and IOFF ⁇ are the maximum expected differences in current considering the minimum current to be Zero (0) and the maximum current to be the datasheet "typical" specification value (0.5, 0.2 nA for the 4177 operational amplifier).
• a block diagram can be constructed to show the error effects on the entire system, and Figure 7 is such a block diagram.
• the gain of the A-D Converter 120 is shown an one (unity), as the block diagram envisions the circuit mapping an input voltage range to a selected A-D range.
• the range selection programmable gate array is set to an appropriate gain to map the selected range to an internal converter range of the A-D Converter 120, with some error included in the A-D Converter 120 as denoted by Gerr.
• FSERROR% 100 * FSERROR / ADCMAX (30)
• FSERROR% (((CGSERR _ CGSGERR * ADDGERR) / CGSGGAIN) +
• ADCGERR / ADCMAX + ADCGERR -1- ADCOFF * 100 (31 )
• FSERROR% can be approximated as: FSERROR% S ((CGSGERR / CGSGGAIN) + (CGSOFF / FSIN) + (ADCGERR +
• Figure 8 shows a unified analog input front end 100 with a calibration circuit 800, according to a second embodiment of the invention. Since switches S1 and S4 are always open during calibration, the only loads on the calibration output will be the 615.6 k ⁇ and 226.8 k ⁇ resistors and the input leakage of the operational amplifiers U1 and U2. A single channel current draw will be low, and so one calibration circuit 800 can be utilized to service many input channels, such as the two channels of the configurable gain stage 1 10.
• the calibration circuit 800 includes an operational amplifier U3, resistors R7, R8, R9, switches S7, S8, S9, a digital-to-analog converter (DAC) 810, and a voltage reference unit 820 (2.5 V reference in the preferred embodiment).
• DAC digital-to-analog converter
• FIG. 9 shows a more detailed diagram of the calibration circuit 800, with component types specified for the preferred embodiment.
• the voltage reference unit 820 is shown as a type ADR421 A. Capacitors C1 , C2 and C3 are coupled to the ADR421A, and a + 5V reference voltage is provided to a VIN input of the ADR421A.
• the DAC 810 is shown as a MAX 5223 DAC, which inputs digital data on its DIN (data in), CLK (clock), and CS (chip select) inputs.
• the operational amplifier U3 is shown as a type 4177.
• Resistor R7 is shown as a 226.8 k ⁇ resistor
• resistor R8 is shown as a 615.6 k ⁇ resistor
• resistor R9 is shown as a 32.4 k ⁇ resistor in the preferred embodiment of the calibration circuit 800.
• resistor R7 is shown as a 226.8 k ⁇ resistor
• resistor R8 is shown as a 615.6 k ⁇ resistor
• resistor R9 is shown as a 32.4 k ⁇ resistor in the preferred embodiment of the calibration circuit 800.
• Unfiltered noise on the output of the DAC 120 is not negligible, but its effects are mitigated in this embodiment by the inherent averaging of the moving calibration point approach. Additional averaging at each calibration point and/or state of switch S9 can also be performed, in an alternative configuration of a calibration method in accordance with an embodiment of the present invention.
• GcFERR (((REF + REFERR) ((226.8 ⁇ O.O2%)/(61 5.6 ⁇ O.O2%») / 0.92105) - 1 (33)
• REFERR is ⁇ 3 mV, assuming that calibration will take place once, at a temperature of around 25 0 C.
• GCF has an accuracy of ⁇ 0.16%.
• GcF is the ratio of ideal gain to actual gain
• GCFERROR is the factor by which GCF itself is in error. So, the actual value is:
• VoutG CFACTUAL VlN (GACTUAL/GACTUAL) ( 1 + GCFERR)
• the calibration circuit 800 lessens the error for the unified analog input front end 100 to an acceptable level of ⁇ 1 % for all but the last range/gain configuration (whereby that one is only slightly above 1 %).
• a third embodiment of the invention referring back to Figure 1 , the zener diodes D1 and D2 are replaced by low-capacitance signal diode clamps (not shown), such as BAV 99 diodes with ⁇ 12 V clamping range.
• the clamp diodes of the third embodiment may experience current leakage greater than an acceptable amount, causing an undesirable offset voltage in the 615.6 k ⁇ resistors. However, based on the type of clamp diodes being used, the current leakage may be maintained to an acceptable amount.
• the switches may be selected so that they have their own internal protection diodes, such as a Max 313 Quad SPST (Single Pole, Single Throw) switch, which has its own protection diodes to ⁇ 12 V.
• these internal protection diodes of the switches alone can provide the overvoltage protection, and thus there is no need for the zener diodes D1, D2 of the first embodiment in this instance.
• switch S2 does not get closed for any of the gain US2005/035483
• switch S2 may be removed from the configurable gain stage to thereby leave only five (5) switches in an alternative configuration of the first (or other) embodiments of the configurable gain stage.
• the configurable gain stage may be utilized to provide an impedance buffer and/or an input signal dynamic range adjustment mechanism for other devices other than A/Ds that are to receive signals output by the configurable gain stage, and that are to process those signals in some way.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Theoretical Computer Science (AREA)
• Analogue/Digital Conversion (AREA)
• Control Of Amplification And Gain Control (AREA)
• Amplifiers (AREA)

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• 2004
  • 2004-10-01 US US10/954,485 patent/US7049989B2/en not_active Expired - Lifetime
• 2005
  • 2005-09-30 WO PCT/US2005/035483 patent/WO2006039649A2/en not_active Ceased
  • 2005-09-30 KR KR1020077009969A patent/KR101222278B1/ko not_active Expired - Fee Related
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• 2007
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