WO2006025409A1 - シリコンエピタキシャルウェーハ及びその製造方法 - Google Patents
シリコンエピタキシャルウェーハ及びその製造方法 Download PDFInfo
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- WO2006025409A1 WO2006025409A1 PCT/JP2005/015801 JP2005015801W WO2006025409A1 WO 2006025409 A1 WO2006025409 A1 WO 2006025409A1 JP 2005015801 W JP2005015801 W JP 2005015801W WO 2006025409 A1 WO2006025409 A1 WO 2006025409A1
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- single crystal
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 93
- 239000010703 silicon Substances 0.000 title claims abstract description 93
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims description 50
- 238000000034 method Methods 0.000 title claims description 33
- 239000013078 crystal Substances 0.000 claims abstract description 61
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 17
- 235000012431 wafers Nutrition 0.000 claims description 140
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 45
- 229910052760 oxygen Inorganic materials 0.000 claims description 45
- 239000001301 oxygen Substances 0.000 claims description 45
- 239000004593 Epoxy Substances 0.000 claims description 19
- 238000001556 precipitation Methods 0.000 claims description 14
- 239000000919 ceramic Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 50
- 230000000694 effects Effects 0.000 description 30
- 238000010438 heat treatment Methods 0.000 description 27
- 238000005247 gettering Methods 0.000 description 23
- 239000002244 precipitate Substances 0.000 description 22
- 230000000052 comparative effect Effects 0.000 description 20
- 238000003384 imaging method Methods 0.000 description 15
- 229910001385 heavy metal Inorganic materials 0.000 description 13
- 238000011109 contamination Methods 0.000 description 12
- 238000000407 epitaxy Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 11
- 238000012360 testing method Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 238000004088 simulation Methods 0.000 description 7
- 230000002950 deficient Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 150000002118 epoxides Chemical class 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
- Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
- Y10T428/264—Up to 3 mils
- Y10T428/265—1 mil or less
Definitions
- the present invention relates to a silicon epitaxial wafer (hereinafter referred to as an epoxy wafer) suitable for uses such as CCD (Charge Coupled Device) and CMOS (Complementally MetaFoxide Semiconductor).
- CCD Charge Coupled Device
- CMOS Complementally MetaFoxide Semiconductor
- CMOS image sensors which are image sensors
- the image sensor has a problem of a white spot defect that prevents an image from being taken at a certain part of the device, which causes a decrease in device yield.
- White spot defects are known to be caused by heavy metal contamination of silicon wafers.
- DZ-IG Denuded Zone-Intrinsic Gettering
- DZ—Silicon single crystal is epitaxially grown on the surface of the IG wafer to form a silicon epitaxial layer.
- -IG Epepiwa has been used.
- the imaging board must have a strong gettering effect to remove heavy metal contamination.
- DZ—IG Wafer is a DZ heat treatment in which oxygen on the surface of the wafer is diffused outward at a temperature of about 1100 ° C to 1200 ° C to make the wafer surface a defect-free layer, and 600 ° C to 900 ° C. It is produced by performing two stages of IG heat treatment, which forms oxygen precipitation nuclei inside the wafer at a temperature of C. DZ—IG heat treatment usually requires a treatment time of 10 hours or more, which increases the cost of manufacturing the wafer.
- the wafer may be contaminated with heavy metals during the heat treatment.
- DZ-IG wafers manufactured using DZ-IG wafers there were problems of high manufacturing costs and heavy metal contamination during heat treatment.
- Patent Document 1 Japanese Patent Laid-Open No. 10-229093
- the oxygen concentration is 12 to 18 X 10 17 atoms / cm 3 (ASTM F121—1979)
- the carbon concentration is 0.3 to 2.5 X 10 15 atoms.
- the silicon single crystal is pulled up by the CZ (Chiochralski) method while controlling to each range of / cm 3 (ASTM F123- 1981).
- annealing treatment is performed at a temperature of 600 ° C or higher and 900 ° C or lower for 15 minutes or longer and 4 hours or shorter, and the EG (Extrinsic Gettering) effect is obtained.
- EG Extransic Gettering
- the carbon concentration is set to 0.1 to 2.5 X 10 15 atoms / cm 3 (ASTM F123-198 l).
- the silicon wafer for semiconductor devices is cut out from the silicon single crystal pulled by the CZ method or MCZ method by controlling the oxygen concentration in the range of 10 to 18 X 10 17 atomsZcm 3 (ASTM F121—1979) .
- One or both surfaces of this wafer are mirror-polished and a silicon epitaxial film is formed on the surface, followed by heat treatment for forming microdefects in the silicon crystal.
- Patent Document 3 Japanese Patent Laid-Open No. 2001-2372407 discloses a method for manufacturing an epitaxial wafer in which epitaxial growth is performed on a CZ silicon wafer doped with carbon at a temperature lower than 1000 ° C. According to the methods disclosed in Patent Documents 1 to 3, an epoxy wafer that can exhibit a sufficient IG effect in a low-temperature device process can be obtained.
- a method for manufacturing a semiconductor device comprising: a step of forming an EG layer on a back surface of a semiconductor wafer; and a step of injecting an element serving as an oxygen precipitation nucleus between the EG layer and an element formation region of the semiconductor wafer.
- Patent Document 4 Japanese Patent No. 3203740.
- a highly sustainable gettering capability can be imparted to the semiconductor device, and the device yield is greatly improved.
- Patent Document 5 Patent No. 3173106
- an impurity contamination prevention film is formed on the surface of the semiconductor substrate, and the back side of the semiconductor substrate is formed.
- a gettering layer composed of a high-concentration impurity diffusion layer is formed by introducing impurities into the surface layer. Remove impurity prevention film, semiconductor After cleaning the substrate, an epitaxial layer is deposited on the surface of the semiconductor substrate.
- the gettering layer is formed of a high-concentration impurity diffusion layer, so that gettering is performed strongly.
- Epi wafers obtained by the methods disclosed in Patent Documents 1 to 3 described above have the same density as that of the conventionally used DZ-IG wafers in experiments in which simulated heat treatment corresponding to the CCD manufacturing process is performed. An oxygen precipitate was formed.
- the above-mentioned epoxy wafer had a lower oxygen precipitate density at the initial stage of the device manufacturing process than the conventional DZ-IG epoxy wafer. This indicates that the above-mentioned Epi wafer has an IG effect equivalent to that of the DZ-IG Ephew wafer after the intermediate stage of the device manufacturing process, but is inferior to the DZ-IG Ep wafer at the initial stage.
- An object of the present invention is to provide a silicon epitaxial wafer that can be produced at a lower production cost than DZ-IG epoxy wafers, has an excellent gettering effect, and is free from heavy metal contamination, and a method for producing the same. There is.
- Another object of the present invention is to provide a silicon epitaxial wafer and a method for manufacturing the same, in which a powerful gettering effect can be expected in the initial stage of the imaging device manufacturing process.
- the present inventors formed a polycrystalline silicon layer for the purpose of the EG effect on the back surface of the carbon-doped wafer. After the formation of the polycrystalline silicon layer, an epitaxial layer was formed on the wafer surface by epitaxial growth, thereby producing the silicon epitaxial wafer of the present invention.
- the first aspect of the invention is that silicon cut from a CZ silicon ingot doped with carbon in a concentration range of 5 ⁇ 10 15 atomsZcm 3 or more and 5 ⁇ 10 17 atomsZcm 3 or less (ASTM F123-1981).
- a polycrystalline silicon layer having a thickness of 0.5 111 or more and 1.5 ⁇ m or less is formed on the back surface of the silicon single crystal wafer.
- the silicon epitaxial wafer according to the first aspect has a sufficient IG effect because oxygen precipitates of 5 ⁇ 10 9 pieces / cm 3 or more are formed at the initial stage of the imaging device manufacturing process, and more The EG effect of the crystalline silicon layer is added, making it ideal for the production of imaging devices that are sensitive to heavy metal contamination, and can contribute to yield improvement.
- carbon is cut out from a CZ silicon ingot doped with carbon in a concentration range of 5 x 10 15 atoms / cm 3 or more and 5 x 10 17 atoms / cm 3 or less (ASTM F123-1981).
- a polycrystalline silicon layer having a thickness of not less than 0.1 and not more than 1.5 / zm is formed on the back surface of the silicon single crystal wafer, and oxygen precipitate nuclei are formed inside the silicon single crystal wafer.
- an epitaxial wafer can be manufactured at a lower manufacturing cost than the DZ-IG epoxy wafer by going through the above steps in this order.
- Epoxytaxic wafers which are free from heavy metal contamination in the wafer manufacturing process, can be expected to have a strong gettering effect from the initial stage of the imaging device manufacturing process.
- the epitaxy wafer of the present invention has a sufficient IG effect because oxygen precipitates of 5 ⁇ 10 9 pieces Zcm 3 or more are formed in the initial stage of the imaging device manufacturing process, and further, due to the polycrystalline silicon layer. Because the EG effect is added, it is optimal for manufacturing imaging devices that are sensitive to heavy metal contamination, and can contribute to yield improvement.
- the manufacturing method of the epitaxy woofer of the present invention is a heavy Epitaki Shar- ueha can be manufactured at a lower manufacturing cost than DZ—IG Epiwaha, which is highly likely to be contaminated with the genus.
- a strong gettering effect can be expected from the initial stage of the imaging device manufacturing process where heavy metal contamination does not occur in the wafer manufacturing process.
- FIGS. 1A to 1D are process diagrams showing a method of manufacturing a silicon epitaxial wafer according to the present invention.
- FIG. 2 is a diagram showing a temperature profile of DZ-IG two-stage heat treatment in Comparative Example 1.
- FIG. 3 is a diagram showing the oxygen precipitate density for each device process step in Comparative Test 1.
- FIG. 4 is a diagram showing a non-defective product rate in an oxide film pressure resistance evaluation test by TZDB in Comparative Test 2.
- the silicon epitaxial wafer of the present invention shown in FIG. 1C is doped with carbon in a concentration range of 5 ⁇ 10 15 at oms / cm 3 or more and 5 ⁇ 10 17 atoms / cm 3 or less (ASTM F123-1981).
- This is an improvement of the silicon epitaxial wafer 10 in which an epitaxial layer 13 having a silicon single crystal force is formed by epitaxial growth on the surface of the silicon single crystal wafer 11 cut from the formed CZ silicon ingot.
- a polycrystalline silicon layer 12 having a thickness of not less than 0 and not more than 1.5 / zm is formed.
- a polycrystalline silicon layer 12 By forming a polycrystalline silicon layer 12 on the back surface of the silicon single crystal wafer 11, a multi-crystal structure is formed.
- the crystalline silicon layer 12 In addition to the EG effect that the crystalline silicon layer 12 has, if the vacancies are supplied from the polycrystalline silicon layer 12 into the silicon single crystal wafer 11 and the oxygen precipitation inside the wafer is promoted! Fruit can also be obtained. Therefore, many oxygen precipitation nuclei are formed inside the silicon single crystal wafer 11.
- oxygen precipitates ib of 5 ⁇ 10 9 pieces / cm 3 or more are formed in the initial stage of the imaging device manufacturing process as shown in FIG. 1D.
- the oxygen precipitate l ib provides a sufficient IG effect, and the addition of the EG effect by the polycrystalline silicon layer 12 makes the above epitaxial wafer ideal for the production of imaging devices sensitive to heavy metal contamination. Yes, it can contribute to yield improvement.
- carbon is cut out from a CZ silicon ingot doped with a concentration range of 5 ⁇ 10 15 atoms / cm 3 or more and 5 ⁇ 10 17 atoms / cm 3 or less (ASTM F123-1981).
- Carbon concentration is less than 5 X 10 15 a tomsZ cm 3 , it Generating an 5 X 10 9 atoms / cm 3 or more oxygen precipitate density in the device process becomes difficult instrument also insufficient gettering.
- the carbon concentration exceeds 5 ⁇ 10 17 at O msZcm 3 , crystal dislocation occurs and single crystal cannot be grown.
- the carbon doping concentration is specified in the range of 5 ⁇ 10 15 atoms / cm 3 or more and 5 ⁇ 10 17 atoms / cm 3 or less (ASTM F12 3-1981).
- a preferable carbon dope concentration is 5 ⁇ 10 15 to 5 ⁇ 10 16 atoms / cm 3.
- the oxygen concentration range of the silicon single crystal wafer 11 is preferably 14 to 18 ⁇ 10 17 atoms Zcm 3 (ASTM F121-1979). If the oxygen concentration is less than 14 ⁇ 10 17 atoms / cm 3 , it is difficult to generate an oxygen precipitate density of 5 ⁇ 10 9 atoms / cm 3 or more in the device process, and gettering is insufficient. When the oxygen concentration exceeds 18 ⁇ 10 17 atoms / cm 3 , epi-defects due to oxygen precipitation tend to occur. A preferable oxygen concentration is 14 to 16 ⁇ 10 17 atoms / cm 3 .
- the specific resistance value of the silicon single crystal wafer 11 is not particularly limited, but the low-resistance substrate of about 0.1 ⁇ 'cm or a high-resistance substrate exceeding 100 ⁇ ⁇ cm can be used for the epitaxial wafer of the present invention.
- Can adapt to The silicon single crystal wafer 11 to be used is preferably a silicon wafer having at least a main surface subjected to mirror polishing.
- the thickness of the silicon single crystal wafer 11 on the back surface is not less than 0.5 111
- a polycrystalline silicon layer 12 of 5 / zm or less is formed, and oxygen precipitation nuclei 11a are formed inside the silicon single crystal wafer 11.
- oxygen precipitation nuclei are formed in a very short time. Oxygen precipitation nuclei are formed inside the silicon single crystal wafer 11 due to the thermal history in the process.
- the thickness of the polycrystalline silicon layer 12 is specified to be 0.5 ⁇ m or more and 1.5 m or less.
- a preferable thickness of the polycrystalline silicon layer 12 is 0.8 to 1.2 ⁇ m.
- an epitaxial layer 13 made of silicon single crystal is formed on the surface of the silicon single crystal wafer 11 by epitaxial growth.
- the thickness of the epitaxial layer 13 is preferably in the range of 5 to 20 m.
- the silicon epitaxial wafer 10 of the present invention is obtained.
- This Epitaxial wafer can be manufactured at a lower manufacturing cost than the DZ-IG EP wafer, and does not require high-temperature heat treatment, so there is no heavy metal contamination in the wafer manufacturing process, and imaging device manufacturing Initial stage power A powerful gettering effect can be expected.
- P is doped at a concentration of 4.4 ⁇ 10 14 atoms / cm 3
- carbon is doped at a concentration of 1 ⁇ 10 16 atoms / cm 3 (ASTM F123—1981), and the oxygen concentration is 15 ⁇ 10 17 atoms.
- a silicon ingot with a low efficiency of 10 ⁇ 'cm was grown by CZ method / cm 3 (ASTM F121—1979).
- An n-type silicon single crystal wafer having a diameter of 8 inches was cut from the ingot.
- a 1 m thick polycrystalline silicon layer was formed on the back side of the silicon single crystal wafer.
- an epitaxial layer having a silicon single crystal force of 10 ⁇ m with an n-type resistivity of 10 ⁇ 'cm was formed on the surface of the silicon single crystal wafer by epitaxy growth to obtain an epitaxial wafer.
- P is doped at a concentration of 4.4 ⁇ 10 14 atoms / cm 3 , and a silicon ingot having an oxygen concentration of 15 ⁇ 10 17 atom s / cm 3 (ASTM F121—1979) and a resistivity of 10 ⁇ ′cm. It was trained by the CZ method. An n-type silicon single crystal wafer having a diameter of 8 inches was cut from the ingot. Next, this silicon single crystal wafer was subjected to a DZ-IG two-stage heat treatment consisting of a first-stage heat treatment and a second-stage heat treatment shown in FIG. 2 to form a DZ-IG wafer. This DZ-IG heat treatment was performed in an N gas atmosphere containing 3% 0. Next, on the surface of the DZ—IG wafer
- An epitaxial layer made of a silicon single crystal having an n-type resistivity of 10 ⁇ 'cm is formed on the surface of the n-type silicon single crystal wafer cut out from the ingot of Example 1 by epitaxy, and 10 / zm is formed.
- a polycrystalline silicon layer was formed on the back surface of the wafer, and it was strong.
- Example 1 and Comparative Examples 1 to 3 were used as samples, respectively, and subjected to thermal simulation heat treatment simulating a CCD manufacturing process.
- This thermal simulation heat treatment simulates the initial, intermediate and final stages of the device process. Wafers that had completed the initial, intermediate, and final stages of the device process were extracted for each process, and samples were obtained. The sample was cleaved into strips, and the cleaved wafer was etched by 2 ⁇ m using chemical selective etching (Wright etching) to reveal oxygen precipitates. Using these samples, the oxygen precipitate density at the woofer cross section was measured with an optical microscope. The results are shown in Fig. 3. “As Epi” in Fig.
- FIG. 3 shows the measurement results of the oxygen precipitate density of each epi-woofer immediately after the formation of the epitaxy layer before the thermal simulation heat treatment.
- the downward arrow in FIG. 3 indicates that the oxygen precipitate density of as Epi and the oxygen precipitate density in the initial stage of the comparative examples 2 and 3 have reached the lower limit of measurement.
- Ni having a concentration of 1 ⁇ 10 12 atoms / cm 2 was forcibly contaminated on the surface of the epoxy wafer obtained in Example 1 and Comparative Examples 1 to 3, respectively.
- thermal simulation heat treatment simulating the CCD manufacturing process performed in the comparative test 1 was applied to each epi-wafer that had been forcibly contaminated with Ni until the final stage.
- the epoxy film pressure evaluation test by TZDB Time Zero Dielectric Breakdown was conducted on the Epoxy wafer after the thermal simulation heat treatment under the conditions of a gate oxide film thickness of 10 nm and a judgment voltage of 8 MVZcm.
- Figure 4 shows the results of the yield rate in this evaluation test. As is clear from FIG.
- pZp- and pZp + epi wafers with a polycrystalline silicon layer formed on a carbon-doped p-type wafer are prepared, and thermal simulation heat treatment simulating the CMOS image sensor process is performed on these epi wafers to the final stage. gave.
- Thermal simulation After the heat treatment an epoxide oxide pressure resistance test using TZDB was conducted under the same conditions as the above test conditions. As a result, all chips are non-defective and 100% non-defective, and even for p-type wafer-based wafers, a polycrystalline silicon layer is formed on the back surface of the carbon-doped wafer, and the wafer surface is epitaxial. It was confirmed that the epitaxial wafer of the present invention in which the layer was formed can obtain a high yield.
- the epitaxy wafer of the present invention provides a sufficient IG effect due to the formation of oxygen precipitates in the initial stage of the imaging device manufacturing process, and further adds the EG effect due to the polycrystalline silicon layer. It is ideal for the production of sensitive imaging devices and can contribute to the improvement of device manufacturing yield.
- the manufacturing method of the epitaxy wafer of the present invention can produce the epitaxy silicon wafer at a lower production cost than the DZ-IG epoxy wafer, which has a high production cost and is likely to be contaminated with heavy metals during production.
- a strong gettering effect can be expected from the initial stage of the imaging device manufacturing process where heavy metal contamination does not occur in the wafer manufacturing process.
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US11/661,724 US20090017291A1 (en) | 2004-08-31 | 2005-08-30 | Silicon epitaxial wafer and production method for same |
EP05781511A EP1801863A4 (en) | 2004-08-31 | 2005-08-30 | SILICON EPITAXIAL WAFERS AND METHOD FOR THE PRODUCTION THEREOF |
US13/051,909 US20110171814A1 (en) | 2004-08-31 | 2011-03-18 | Silicon epitaxial wafer and production method for same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2004251837A JP2006073580A (ja) | 2004-08-31 | 2004-08-31 | シリコンエピタキシャルウェーハ及びその製造方法 |
JP2004-251837 | 2004-08-31 |
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US (2) | US20090017291A1 (ja) |
EP (1) | EP1801863A4 (ja) |
JP (1) | JP2006073580A (ja) |
KR (1) | KR100877772B1 (ja) |
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WO2010131412A1 (ja) * | 2009-05-15 | 2010-11-18 | 株式会社Sumco | シリコンウェーハおよびその製造方法 |
CN107532325A (zh) * | 2015-05-08 | 2018-01-02 | 胜高股份有限公司 | 硅外延晶圆及其制造方法 |
CN107532325B (zh) * | 2015-05-08 | 2019-01-11 | 胜高股份有限公司 | 硅外延晶圆及其制造方法 |
US10211066B2 (en) | 2015-05-08 | 2019-02-19 | Sumco Corporation | Silicon epitaxial wafer and method of producing same |
Also Published As
Publication number | Publication date |
---|---|
US20110171814A1 (en) | 2011-07-14 |
KR20070036801A (ko) | 2007-04-03 |
TWI278040B (en) | 2007-04-01 |
JP2006073580A (ja) | 2006-03-16 |
TW200614379A (en) | 2006-05-01 |
EP1801863A1 (en) | 2007-06-27 |
EP1801863A4 (en) | 2008-09-24 |
KR100877772B1 (ko) | 2009-01-08 |
US20090017291A1 (en) | 2009-01-15 |
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