JP4650493B2 - 固体撮像素子用半導体基板およびその製造方法 - Google Patents
固体撮像素子用半導体基板およびその製造方法 Download PDFInfo
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 75
- 229910052799 carbon Inorganic materials 0.000 claims description 74
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 66
- 229910052710 silicon Inorganic materials 0.000 claims description 66
- 239000010703 silicon Substances 0.000 claims description 61
- 229910052760 oxygen Inorganic materials 0.000 claims description 52
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 51
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- 238000010438 heat treatment Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 6
- CSJDCSCTVDEHRN-UHFFFAOYSA-N methane;molecular oxygen Chemical compound C.O=O CSJDCSCTVDEHRN-UHFFFAOYSA-N 0.000 claims description 5
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- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
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- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
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Description
ここで、半導体基板に重金属が不純物として混入する要因としては、第一に、半導体基板の製造工程における金属汚染、第二に、固体撮像素子の製造工程における重金属汚染が挙げられる。
さらに、本発明は、上記の半導体基板上に回路を形成することによって、優れた電気特性を与えた高性能の固体撮像素子を、その有利な製造方法に併せて提供することを目的とする。
(1)シリコン基板の上に、シリコンのエピタキシャル層を有し、該エピタキシャル層の上に酸化膜を有し、前記シリコン基板中に、濃度が3×1016〜8×1016atoms/cm3の固溶炭素および濃度が1.4×1018〜1.6×1018atoms/cm3 の固溶酸素を有し、かつサイズが75〜180nmの炭素・酸素系析出物が1×10 7 〜1×108個/cm2の密度で存在することを特徴とする固体撮像素子用半導体基板。
なお、この場合のサイズとは、シリコン基板の厚み方向断面のTEM観察像における析出物の対角線長を意味し、該観察視野内の析出物の平均値で示すこととする。
2 エピタキシャル層
3 半導体基板
4 酸化膜
5 窒化膜
6 固体撮像素子
図1は、本発明の固体撮像素子用半導体基板の製造方法を説明する図であり、図示例では、まず、例えば石英坩堝内にシリコン結晶の原料であるポリシリコンを積層配置し、さらにこのポリシリコン表面上にグラファイト粉を適量塗布し、例えばチョクラルスキー法(CZ法)に従って、炭素を添加したCZ結晶を作製する。
なお、CZ結晶とは、磁場印加CZ結晶も含めたチョクラルスキー法で製造された結晶の呼称である。
一方、1.6×1018 atoms/cm3を超えると、酸素析出物のサイズが減少し母体シリコン原子と析出物界面における歪みの効果が緩和され歪みによるゲッタリング効果が低下することが懸念されるからである。
なお、フォトダイオード接合リーク電流の測定は、以下のように行った。まず、上記のシリコン基板をSC−1洗浄液(NH4OH:H2O2:H2O=1:1:5)で洗浄し、次いでSC−2洗浄液(HCl:H2O2:H2O=1:1:5)で洗浄した。次に、このウェーハを1100℃で110分間、ウェット酸化することにより、ウェーハ表面に厚さ600nmのフィールド酸化膜を形成した。その後、この酸化膜をフォトリソグラフィ技術によりパターニングして拡散窓を作り、そこにオキシ塩化リン(POCl3)を用いた固層拡散でn+層を形成した。その際、リン拡散の条件は、900℃で20分間、PSG(リンシリケートガラス)膜をエッチングにより除去した後、1000℃、60分の条件で熱拡散した。n+層の拡散深さは約2μmでその濃度は1×1019/cm3である。コンタクトホールをあけた後、そこに1.5mass%Siを含むAlをスパッタリングで500nmで堆積した。電極パターニングの後、N2雰囲気下、450℃でアニール処理を行い、最後に裏面酸化膜を除去した。接合面積は1.8mm□の形状のパターンを用いた。
かくして得られたシリコン基板のpn接合部に電圧を印加し、HP4140(pA)メータで、接合のリーク電流を測定した。このときHP4141B(カレントボルテージソース)でガードリングにバイアスを印加することによって、p型の表面反転を抑える工夫を行った。負のガードリングバイアスとして、−20Vを用いた。この測定は、シリコン基板(ウェーハ)20箇所について行い、その平均値をリーク電流とした。
なお、エピタキシャル層2の成長には、各種CVD法(化学気相成長法)を用いることができる。
すなわち、デバイス工程は、まず、図5(a)に示すように、図5(b)に示したシリコン基板1の上にn型のエピタキシャル層2を形成した半導体基板3を用意し、図5(b)に示すように、このエピタキシャル層2の所定位置に第1のp型ウエル領域11を形成する。その後、図5(c)に示すように、表面にゲート絶縁膜12を形成するとともに、第1のp型ウエル領域11の内部にイオン注入によってn型及びp型の不純物を選択的に注入して、垂直転送レジスタを構成するn型の転送チャネル領域13、p型のチャネルストップ領域14および第2のp型ウエル領域15をそれぞれ形成する。
その後、各シリコン基板について、そのゲッタリング能力を、原子吸光分析にて各シリコン基板表面の金属汚染濃度を測定し、下記式に従ってゲッタリング効率を求めた。
記
ゲッタリング効率=(熱処理後の表面汚染濃度)/(初期表面汚染濃度)×100(%)
Claims (4)
- シリコン基板の上に、シリコンのエピタキシャル層を有し、該エピタキシャル層の上に酸化膜を有し、前記シリコン基板中に、濃度が3×1016〜8×1016atoms/cm3の固溶炭素および濃度が1.4×1018〜1.6×1018atoms/cm3 の固溶酸素を有し、かつサイズが75〜180nmの炭素・酸素系析出物が1×10 7 〜1×108個/cm2の密度で存在することを特徴とする固体撮像素子用半導体基板。
- 前記酸化膜の上に、窒化膜を有する請求項1に記載の固体撮像素子用半導体基板。
- 固溶炭素を3×10 16 〜8×10 16 atoms/cm 3 及び固溶酸素を1.4×10 18 〜1.6×10 18 atoms/cm 3 含有するシリコン単結晶から製造したシリコン基板の上に、シリコンのエピタキシャル層を成長させ、該エピタキシャル層の上に酸化膜を形成したのち、600〜700℃の低温熱処理を施し、サイズが75〜180nmの炭素・酸素系析出物を1×10 7 〜1×108個/cm2の密度で析出させることを特徴とする固体撮像素子用半導体基板の製造方法。
- 前記シリコン基板は、CZ(チョクラルスキー)法またはMCZ(磁場印加)法を用いて製造する請求項3に記載の固体撮像素子用半導体基板の製造方法。
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PCT/JP2007/067518 WO2008029918A1 (fr) | 2006-09-07 | 2007-09-07 | Substrat à semi-conducteurs pour dispositif de formation d'image à semi-conducteurs, dispositif de formation d'image à semi-conducteurs et procédé pour les fabriquer |
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Families Citing this family (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
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EP3113224B1 (en) | 2015-06-12 | 2020-07-08 | Canon Kabushiki Kaisha | Imaging apparatus, method of manufacturing the same, and camera |
JP6531729B2 (ja) * | 2016-07-19 | 2019-06-19 | 株式会社Sumco | シリコン試料の炭素濃度評価方法、シリコンウェーハ製造工程の評価方法、シリコンウェーハの製造方法およびシリコン単結晶インゴットの製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005038899A1 (ja) * | 2003-10-21 | 2005-04-28 | Sumco Corporation | 高抵抗シリコンウェーハの製造方法、並びにエピタキシャルウェーハおよびsoiウェーハの製造方法 |
WO2006025409A1 (ja) * | 2004-08-31 | 2006-03-09 | Sumco Corporation | シリコンエピタキシャルウェーハ及びその製造方法 |
JP2007273959A (ja) * | 2006-03-06 | 2007-10-18 | Matsushita Electric Ind Co Ltd | 光検出素子及びその製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3384506B2 (ja) * | 1993-03-30 | 2003-03-10 | ソニー株式会社 | 半導体基板の製造方法 |
JP2002353434A (ja) | 2001-05-22 | 2002-12-06 | Sony Corp | 固体撮像装置の製造方法 |
JP2004006615A (ja) * | 2002-04-26 | 2004-01-08 | Sumitomo Mitsubishi Silicon Corp | 高抵抗シリコンウエーハ及びその製造方法 |
WO2004008521A1 (ja) * | 2002-07-17 | 2004-01-22 | Sumitomo Mitsubishi Silicon Corporation | 高抵抗シリコンウエーハ及びその製造方法 |
WO2006003812A1 (ja) * | 2004-06-30 | 2006-01-12 | Sumitomo Mitsubishi Silicon Corporation | シリコンウェーハの製造方法及びこの方法により製造されたシリコンウェーハ |
CN101351890A (zh) * | 2006-09-07 | 2009-01-21 | 胜高股份有限公司 | 固态图像传感装置的半导体基板以及固态图像传感装置和其制造方法 |
JP2009212354A (ja) * | 2008-03-05 | 2009-09-17 | Sumco Corp | シリコン基板の製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20100148297A1 (en) | 2010-06-17 |
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JP4650584B2 (ja) | 2011-03-16 |
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