Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/211—Gated diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes

Definitions

• the present invention relates generally to semiconductors, and more particularly to a semiconductor device and method of forming the same.
• FIG. 1 illustrates, in cross-sectional view, a semiconductor device in accordance with one embodiment of the present invention
• FIG. 2 illustrates, in graphical form, a current versus voltage (cathode to anode voltage) graph illustrating cathode current and substrate current produced by the semiconductor device of FIG. 1.
• FIG. 1 illustrates, in cross-sectional view, a semiconductor device in accordance with one embodiment of the present invention.
• P-, P, P+, and P++ will represent semiconductor material having P-type conductivity, wherein the dopant concentrations vary from lowest dopant concentrations for P-, higher dopant concentration for P, even higher dopant concentration for P+, and the highest dopant concentration for P++.
• N, N+, and N++ will represent semiconductor material having N-type conductivity, wherein the dopant concentrations vary from lowest dopant concentrations for N, higher dopant concentration for N+, and the highest dopant concentration for N++.
• the semiconductor device 10 is a diode, where the anode 42 is formed from P++ region 30, P+ region 20, P- region 24, and P region 26, and the cathode 40 is formed from N++ region 32 and N region 22.
• P region 12 is a semiconductor substrate and N+ region 13 may be a buried layer, or alternately may be an N+ layer formed in any manner.
• N+ region 16 may be implemented as a conductive sinker.
• N+ region 16, in combination with N+ layer 13, forms a conductive isolation tub or conductive isolation feature which may be used to conductively isolate diode 10 from the rest of the integrated circuit.
• Dielectric layer 14 may be used to surround diode 10.
• Dielectric layer 14 forms an electrical isolation barrier which may be used to electrically isolate diode 10 from the rest of the integrated circuit.
• dielectric layer 14 may be formed of any dielectric material. Oxide is just one possible dielectric material that may be used. Any other appropriate material may be used, such as, for example, oxide and polysilicon combinations.
• Anode 42 includes P++ region 30, cathode 40 includes N++ region 32, and isolation region 16 includes N++ region 34.
• regions 30, 32, and 34 are all heavily doped in order to allow for good ohmic contact, and thus may be called ohmic regions herein.
• metal contacts may be formed overlying regions 30, 32, and 34 respectively.
• a dielectric layer 27 is formed overlying the junction between the anode 42 and the cathode 40.
• dielectric layer 27 may be formed of any dielectric material.
• a thin oxide layer is used to form dielectric layer 27.
• a conductive layer 28 is formed overlying the dielectric layer 27.
• the conductive layer 28 may be formed of any conductive or semi-conductive material.
• a polysilicon layer is used to form conductive layer 28.
• each of dielectric layer 27 and conductive layer 28 may be formed using a plurality of layers.
• a dielectric layer 19 is formed between the anode 42 and N+ region 16.
• dielectric layer 19 may be formed of any dielectric material.
• a field oxide layer is used to form dielectric layer 19.
• Oxide is just one possible dielectric material that may be used. Any other appropriate dielectric material may be used.
• a dielectric layer is just one possible dielectric material that may be used. Any other appropriate dielectric material may be used.
• dielectric layer 18 is formed as a ring around the N++ region 32.
• dielectric layer 18 may be formed of any dielectric material.
• a field oxide layer is used to form dielectric layer 18.
• Oxide is just one possible dielectric material that may be used. Any other appropriate dielectric material may be used.
• dielectric layer 18 may be a shallow trench isolation region.
• One purpose for dielectric layer 18 is to support a higher voltage difference between N++ region 32 and conductive layer or conductive plate 28. Alternate embodiments of the present invention may not use dielectric layer 18 and may instead allow the other regions to extend up to the surface plane (i.e. the surface plane adjacent to the bottom surface of layer 27).
• anode 42 is electrically coupled to conductive layer 28 by way of conductive layer 44.
• Conductive layer 44 has not been illustrated with any specific topology to make clear that any desired topology may be used.
• Conductive layer 44 may be formed using any conductive material that can be formed on a semiconductor device 10. Alternate embodiments of the present invention may electrically bias the N isolation region formed by N++ region 34, N+ region 16, and N+ region 13 in order to reduce the parasitic current injected into substrate 12 from the vertical parasitic NPN and PNP devices. Note that in the illustrated embodiment, the vertical parasitic NPN transistor has a first N region formed from regions 32 and 22, has a P region formed from regions 30, 20, 24, and 26, and has a second N region formed from region 13.
• the vertical parasitic PNP transistor has a first P region formed from regions 30, 20, 24, and 26, has an N region formed from region 13, and has a second P region formed from region 12. If the N++ region 34 is electrically coupled (e.g. shorted) to anode 42, the emitter and base of the vertical parasitic PNP transistor are at approximately the same voltage, and thus there is no emitter/base bias. Consequently, the vertical parasitic PNP transistor produces very little collector current which is injected into P substrate 12. Also, if the N++ region 34 is electrically coupled (e.g. shorted) to anode 42, the base and collector of the vertical parasitic NPN transistor are at approximately the same voltage; and thus there is no way for the collector voltage to drop below ground to a negative voltage.
• the collector was allowed to drop to a negative voltage, then the junction between the N+ region 13 and the P substrate 12 may form a conducting diode junction, thus injecting current into substrate 12.
• the N++ region 34 is electrically coupled (e.g. shorted) to cathode 40, it will be possible to support a higher voltage on cathode 40. Electrically coupling N++ region 34 and cathode 40 produces a negative bias on the junction between N region 22 and P region 26, and also on the junction between P region 26 and N+ region 13.
• These two reverse bias junctions together reduce the electrical field in N region 22, particularly those portions of N region 22 which are closest to P- region 24 and closest to dielectric layer 18. This reduced electric field allows a higher maximum voltage to be supported on cathode 40.
• anode 42 includes a plurality of dopant concentrations.
• P++ region 30 has a dopant concentration on the order of 1E20
• P+ region 20 has a dopant concentration in the range of 2E17 to 4E17
• P- region 24 has a dopant concentration in the range of 1E15 to 5E15
• P region 26 has a dopant concentration in the range of 2E16 to 5E16.
• These dopant concentrations are given just for illustrative purposes only. Alternate embodiments of the present invention may use any appropriate dopant concentrations.
• the heavy dopant concentration in P++ region 30 is for the purpose of forming a good ohmic contact with an overlying conductive layer (not shown). Thus P++ region 30 may be called an ohmic region herein.
• Alternate embodiments of the present invention may have at least two orders of magnitude (i.e. two powers of ten, or 100 times) difference between the lowest P-type dopant concentration used in anode 42 and the highest P-type dopant concentration used in anode 42.
• alternate embodiments of the present invention may designate the difference between the lowest and the highest dopant concentrations at any desired point between 0 (i.e. no difference) and the maximum difference allowed by integrated circuit fabricating technology.
• cathode 40 includes a plurality of dopant concentrations.
• N++ region 32 has a dopant concentration on the order of 5E20
• N region 22 has a dopant concentration in the range of 3E16 to 6E16. These dopant concentrations are given just for illustrative purposes only. Alternate embodiments of the present invention may use any appropriate dopant concentrations.
• the heavy dopant concentration in N++ region 32 is for the purpose of forming a good ohmic contact with an overlying conductive layer (not shown). Thus N++ region 32 may be called an ohmic region herein.
• Interface 49 forms an anode/cathode junction interface between anode 42 and cathode 40.
• the isolation region (34, 16, 13) includes a plurality of dopant concentrations.
• N++ region 34 has a dopant concentration on the order of 5E20
• N+ region 16 has a dopant concentration in the range of 5E17 to 8E17
• N+ region 13 has a dopant concentration in the range of 1E18 to 5E18.
• These dopant concentrations are given just for illustrative purposes only. Alternate embodiments of the present invention may use any appropriate dopant concentrations.
• the heavy dopant concentration in N++ region 34 is for the purpose of forming a good ohmic contact with an overlying conductive layer (not shown).
• N++ region 34 may be called an ohmic region herein.
• P substrate 12 may be doped to form a P+ substrate 12.
• substrate 12 may be a P++ substrate having an overlying P-type epitaxial layer formed thereon.
• implantation and diffusion may be used to form an N-type buried layer which serves a similar function as the N+ region 13 illustrated in FIG. 1.
• a second P-type epitaxial layer may be deposited overlying the N-type buried layer. This second P-type epitaxial layer may serve a similar function as the P- region 24 illustrated in FIG. 1.
• implantation may be used to form the P region 26 and the N region 22.
• the same implantation mask may be used to form regions 26 and 22.
• etching and oxide deposition may be performed to form layers 14, 18, and 19.
• implantation may be used to form the P+ region 20, and a separate implantation may be used to form N+ region 16.
• Alternate embodiments of the present invention may use a plurality of implant steps and masks for forming N+ region 16.
• oxide deposition may be performed to form layer 27, and polysilicon deposition may be performed to form layer 28.
• implantation may be used to form the N++ regions 32 and 34, and a separate implantation may be used to form P++ region 30.
• Alternate embodiments of the present invention may use any appropriate alternate processing steps, in any appropriate order, to form various embodiments of semiconductor device 10.
• FIG. 2 illustrates, in graphical form, a current versus voltage (cathode to anode voltage) graph illustrating cathode current (Icathode 50) and substrate current (Isubstrate 52) produced by the semiconductor device 10 of FIG. 1.
• the parasitic current (Isubstrate 52) injected into substrate 12 is approximately six orders of magnitude less than the cathode current (Icathode 50).
• FIG. 2 assumes that N++ region 34 (the isolation region) has been shorted to the anode 42 and both are approximately 0 Volts, the voltage of cathode 40 is pulled below 0 Volts, substrate 12 is biased to -10 volts, and the temperature of semiconductor device 10 is approximately 150 degrees Celsius.
• Increasing the width of N+ region 16 beyond 10 micrometers may further reduce the cathode current injected into substrate 12; however, a trade-off often must be made between the amount of semiconductor area required to form semiconductor device 10 and the electrical performance of semiconductor device 10.
• the parasitic current injected into the substrate is approximately 10% of the cathode current.
• a conventional non-isolated diode injects a very large amount of parasitic current into the substrate, causing potential malfunctions of adjacent circuitry formed on the same integrated circuit.
• semiconductor materials used to form the various portions of semiconductor device 10 may be any appropriate material.
• substrate 12 may be silicon or any another appropriate semiconductor material.
• semiconductor device 10 may be incorporated into a power integrated circuit which is operable for high voltages and high currents.

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• Element Separation (AREA)
• Bipolar Integrated Circuits (AREA)
• Electrodes Of Semiconductors (AREA)
• Bipolar Transistors (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)

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• 2004
  • 2004-04-30 US US10/836,170 patent/US7095092B2/en not_active Expired - Lifetime
• 2005
  • 2005-04-06 JP JP2007510745A patent/JP5172330B2/ja not_active Expired - Fee Related
  • 2005-04-06 WO PCT/US2005/011276 patent/WO2005111817A2/en not_active Ceased
  • 2005-04-06 EP EP05732887A patent/EP1756949A4/en not_active Withdrawn
  • 2005-04-06 CN CNA2005800134293A patent/CN1947258A/zh active Pending
  • 2005-04-28 TW TW094113757A patent/TWI364057B/zh not_active IP Right Cessation
• 2006
  • 2006-06-27 US US11/426,815 patent/US7476593B2/en not_active Expired - Fee Related

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