WO2005076319A2 - Halbleiterbauteil mit einem halbleiterchipstapel auf einer umverdrahtungsplatte und herstellung desselben - Google Patents
Halbleiterbauteil mit einem halbleiterchipstapel auf einer umverdrahtungsplatte und herstellung desselben Download PDFInfo
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- WO2005076319A2 WO2005076319A2 PCT/DE2005/000175 DE2005000175W WO2005076319A2 WO 2005076319 A2 WO2005076319 A2 WO 2005076319A2 DE 2005000175 W DE2005000175 W DE 2005000175W WO 2005076319 A2 WO2005076319 A2 WO 2005076319A2
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- semiconductor
- semiconductor chip
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0101—Neon [Ne]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01021—Scandium [Sc]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01052—Tellurium [Te]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0293—Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the invention relates to a semiconductor component with a semiconductor chip stack on a rewiring plate which carries the semiconductor chip stack on its upper side and has an umwiring structure which is electrically connected to the contact surfaces of the semiconductor chips of the semiconductor chip stack.
- the invention further relates to a method for producing such a semiconductor component.
- Multichip modules are determined and can be used in memory modules (SIMM, single in-line memory module) or in double-sided memory modules (DIMM, dual in-line memory module).
- these memory modules have a base in the form of a printed circuit board.
- This printed circuit board has a rewiring structure on which contact connection areas for flipchip contacts and contact connection areas for bond wire connections are arranged.
- the semiconductor chip stack is formed in that a semiconductor chip with flip chip contacts and a semiconductor chip with bondable contact areas are stacked on one another with their rear sides.
- the flipchip contacts are connected directly to the rewiring structure and the stacked semiconductor chip is coupled to the rewiring structure via bonding wires, the associated contact pads for the semiconductor chips are connected together on the printed circuit board via rewiring lines.
- a disadvantage of such a component is that after the electrical connections have been made, the semiconductor chips of the semiconductor chip stack can only be checked together. An error display during the test therefore does not provide a reliable statement as to which of the components has caused a technical failure, since the error can no longer be clearly assigned.
- This disadvantage has an aggravating effect on production analyzes, error frequency investigations and process optimization, since after bonding only statements about the properties of the stack are possible. Unreliability in the contacting can neither be assigned to a single bond connection nor to a single connection with a flipchip contact.
- US-6,071,754 discloses a similar stacking of two semiconductor chips as US-6,007,752.
- the underside of the semiconductor plate is provided with a further rewiring structure. Through contacts are also provided to this underside rewiring structure. Nevertheless, the problem is not solved that the semiconductor chips connected to the rewiring structures on the top and bottom of the rewiring substrate or the printed circuit board can no longer be tested individually.
- the object of the invention is to create a semiconductor component with a semiconductor chip stack, in which even after the individual semiconductor chips of the semiconductor chip stack have been connected to the rewiring structures of a rewiring the substrate of the functions of the individual semiconductor chips can be checked, and malfunctions can be clearly assigned without affecting the manufacturing costs, so that with the same manufacturing effort, an increased reliability of semiconductor components with semiconductor chip stacks is achieved.
- a semiconductor component with a semiconductor chip stack is created on a rewiring board.
- the underside of the rewiring plate also forms the underside of the semiconductor component.
- At least one external contact surface is arranged on this underside, which has a plurality of external contact surface regions that are spatially separated from one another.
- the individual external contact area areas are assigned to the individual semiconductor chips of the semiconductor chip stack.
- the spatially separated external contact area areas of an individual external contact area are electrically connected via a common external contact.
- This semiconductor component has the advantage that prior to the application of external contacts to the external contact area areas of an individual external contact area of each semiconductor chip of the semiconductor chip stack, individual testing can be carried out within the semiconductor component.
- the number of semiconductor chips is not limited to two semiconductor chips in the stack, but, depending on the size of the external contact area, a plurality of spatially separated external contact area areas can be provided in order to individually test a corresponding number of semiconductor chips in a semiconductor chip stack.
- the size of a measuring probe also determines the possible number of stackable semiconductor chips, because the spatial expansion of the measuring probe provides for a minimum size for each of the outer contact area areas. With the currently available miniaturization of measuring probes and the technically meaningful sizes of external contact areas, up to six external contact area areas of an external contact area can be spatially separated from one another, so that up to six stacked semiconductor chips individually follow over the external contact area area
- Completion of the semiconductor device can be tested.
- the attachment of external contacts can only take place after the test, however the attachment of external contacts to spatially separated external contact area areas is technically less problematic than the internal wiring of contact areas of semiconductor chips with corresponding rewiring structures of a U wiring printed circuit board.
- the redistribution board has a redistribution structure on its upper side, which has contact connection areas in its center for connecting a semiconductor chip with flipchip contacts.
- the edge area of the rewiring plate which surrounds the center, can have contact connection areas for bond connection to one or more stacked semiconductor chips.
- Another advantage of such a semiconductor component is that it has a very compact chip stack, because the back of the stacked semiconductor chip to be provided with bond connections can be positioned on the back of the first semiconductor chip with flip chip contacts. With such a technology, the memory capacity of both a SIMM module and a DIMM module can be approximately doubled.
- the rewiring plate has a rewiring structure in the center of its upper side for attaching a rear side of a lower semiconductor chip.
- the redistribution structure in the edge regions of the redistribution board has contact connection areas for bond connections to the upper sides of the stacked semiconductor chips and the lower semiconductor chips.
- Rewiring leads to the through contacts, which can be provided both on the top and on the bottom of the rewiring plate, in order to ensure a connection of external contact area regions to the associated or corresponding contact connection areas of the individual semiconductor chips.
- the semiconductor chips of a stack have contact areas on their active upper sides, which are connected to the contact connection areas on the upper side of the rewiring plate via flip chip contacts and / or bond connections.
- the previous technologies can be used for such a bond connection, the semiconductor component according to the invention having the advantage that each individual one of these bond connections can still be tested after the bond connections have been embedded in a plastic housing compound.
- Another aspect of the invention relates to a panel or a rewiring substrate strip which has component positions with semiconductor components arranged in rows and columns. These semiconductor components are structured in such a way that they have chip stacks on the top of the panel in the semiconductor component positions, which have corresponding stacks Connections are connected to a rewiring structure on the upper side of the panel and which have external contact areas on the lower side, which form spatially separate external contact area regions, which correspond to the semiconductor chips in the semiconductor chip stack of the semiconductor component.
- Such a benefit has the advantage that, for several semiconductor components, a uniform plastic cover can be applied to the benefit, which covers several semiconductor component positions. Even after covering several semiconductor component positions with plastic, individual testing of the individual semiconductor chips of a stack of semiconductor chips on the panel or the rewiring substrate strip is possible.
- a method for producing and testing a panel with semiconductor components arranged in rows and columns with semiconductor chip stacks has the following method steps.
- a circuit carrier with rewiring lines is produced in the form of a rewiring plate, which are electrically connected via vias and contact connection areas on the top side of the circuit board to external contact area areas on the underside of the circuit board.
- the outer contact area areas are structured in such a way that a plurality of outer contact area areas are provided for the attachment of a single external contact.
- the outer contact area regions are spatially separated, but are not arranged close to one another, so that a single external contact can electrically connect them to one another.
- the circuit carrier in the area of the semiconductor component positions can then be covered with a plastic compound.
- This covering has the advantage that in the subsequent test method, the sensitive electrical connections between the rewiring structure of the rewiring board and the individual semiconductor chips in the semiconductor chip stack are already massively protected by the plastic cover.
- the individual semiconductor chips of a semiconductor chip stack are then tested via the corresponding external contact area regions on the underside of the circuit carrier.
- the test of each individual semiconductor chip from the underside of the panel can be carried out individually for each individual semiconductor chip due to the special structure of the spatial arrangement of the external contact area regions. After testing, the defective semiconductor components can be marked so that they and their faults can be checked individually.
- the present invention enables a stacked semiconductor chip to be subsequently connected.
- the invention results in components for a so-called ball-grid-array (BGA) design.
- the semiconductor component has a grid-shaped arrangement of external contacts in the form of solder balls, solder balls or solder bumps on its underside.
- the underside with the external contacts is carried by a rewiring plate, on which a stack of semiconductor chips can be located, which can be arranged differently in this invention.
- a combination of different semiconductor chips can be connected to the external contacts with the rewiring plate.
- These semiconductor chips in a stack can be based on flip technology and / or on semiconductors with bond wire connection.
- a stack can also have only semiconductor chips that are based only on bond wire connections.
- semiconductor chips can be provided which are stacked in that they are arranged next to one another on their side edges and are connected to the external contacts of the rewiring plate via the side edges.
- These different structures are also called flip-chip wirebond stack, wirebond-wirebond stack, and / or side-by-side multichip package (SSMCP) in semiconductor technology.
- SSMCP side-by-side multichip package
- the invention advantageously enables the electrical connection to the external contacts to be designed in such a way that the chips defy the completion of the semiconductor component. risch are not yet connected to each other and can thus be individually tested electrically from the outside from the underside of the semiconductor component. These connections of the individual lines to the individual chips are only realized via the external contacts in the form of solder balls, solder balls or solder bumps. This has the advantages:
- the semiconductor chips can initially be tested completely separately from one another without influencing one another.
- a baseband chip and a DRAM chip, or an analog chip and a digital chip can be tested completely isolated from one another and individually, even though they are already fully packaged in the component housing. Testing can even be carried out on a panel or a substrate strip on which several components are present in groups under a plastic cover, even before this substrate strip or the panel is separated into individual semiconductor components.
- FIG. 1 shows a schematic plan view of a rewiring plate of a semiconductor component, according to a first embodiment of the invention, for stacking two semiconductor chips;
- FIG. 2 shows a schematic plan view of a rewiring plate of a semiconductor component, according to a second embodiment of the invention, for stacking four semiconductor chips;
- FIG. 3 shows a schematic plan view of a rewiring plate of a semiconductor component, according to a third embodiment of the invention.
- FIG. 4 shows a schematic top view of a rewiring board with stacked semiconductor chips according to FIG. 3,
- FIG. 5 shows a schematic cross section through a semiconductor component with a semiconductor chip stack according to the first embodiment of the invention according to FIG. 1 with the possibility of testing the stacked semiconductor chips of the semiconductor chip stack individually;
- FIG. 6 shows a schematic cross section of the semiconductor component according to FIG. 5 after attaching external contacts on the underside of the semiconductor component.
- FIG. 1 shows a schematic plan view of a redistribution board 2 of a semiconductor component according to a first embodiment of the invention for stacking two semiconductor chips.
- the plan view depicted in FIG. 1 is only a partial view of the top side 25 of the rewiring plate 2.
- the rewiring structures 15 on the top side 25 of the rewiring plate 2 are shown in FIG. 1 with solid lines.
- the redistribution structures on the underside of the redistribution board 2 are shown with hatched hatched areas. Accordingly, two types of contact pads 16 and 20 are shown on the top 25 of the rewiring plate 2.
- the larger contact connection areas 20 are arranged in an edge region 17 of the upper side 25 of the rewiring plate and are used for attaching bond wire connections. They currently have a length of approximately 150 ⁇ m and a width in the range from 70 to 100 ⁇ m in order to accommodate correspondingly thick bond wires on the contact pad 20.
- the contact connection area 16 has only a diameter of a few 10 micrometers, which is currently approximately 60 to 80 ⁇ m and serves to connect flipchip contacts to the rewiring structure 15 on the top side 25 of the rewiring plate 2.
- Separate rewiring lines 26 lead from the contact connection areas 16 and 20 to through contacts 24, which electrically connect the rewiring structure 15 on the upper side 25 of the rewiring plate 2 with the rewiring structures 15 Connect on the underside of the rewiring plate 2.
- the rewiring lines 26 for the contact pads 16 and 20 are also separated from one another on the underside of the rewiring plate 2. They are also not electrically connected to one another by the external contact surface 5 arranged on the underside. Rather, they are connected to spatially separated external contact area regions 6 and 7, which are separated by a gap 29.
- the gap 29 has a distance a between an external contact area 6, which corresponds to the contact pad 16 for flipchip contacts, and the contact area 7, which corresponds to the contact pad 20 for bond wire connections.
- the two outer contact area regions 6 and 7 are also electrically separated from one another by the distance a, so that the semiconductor chips in the chip stack can be tested individually. After the test, a lonely external contact can then be applied to the external contact surface areas 6 ′′ and 7 of the external contact surface 5, which provides an electrical connection.
- FIG. 2 shows a schematic plan view of a redistribution board 2 of a semiconductor component according to a second embodiment of the invention for stacking four semiconductor chips. Components with the same functions as in FIG. 1 are identified by the same reference symbols and are not discussed separately.
- FIG. 2 shows a corner area of the upper side 25 of the rewiring plate 2. Three contact connection areas 20 for attaching bond wire connections are arranged on this corner area, so that it is possible to borrow three stacked semiconductor chips for bond wire connections via these contact connection areas 20 with the external contact area areas 7, 8 and 9 on the underside of the To connect the rewiring plate 2 via the through contacts 24.
- the lowermost semiconductor chip can have flipchip contacts which are arranged on contact connection areas 16 for flipchip contacts, which are located below the semiconductor chip stack 1, the outer contour of which is marked by the dashed line 30.
- four semiconductor chips of a semiconductor chip stack can be tested individually and individually via the external contact area regions 6, 7, 8 and 9 via the redistribution board 2 of the second embodiment of the invention, their contact areas not shown here being electrically connected to one another only when external contacts are attached become.
- FIG. 3 shows a schematic plan view of a rewiring board 2 of a semiconductor component 4, according to a third embodiment of the invention.
- FIG. 3 shows an edge region 17 of the rewiring plate 2 and the position of the edges 30, 31, 32 and 33 of stacked semiconductor chips 10, 11, 12 and 13 in relation to one another.
- the top 25 of the rewiring plate 2 is indicated by solid lines.
- An edge side of a lowermost semiconductor chip 10 is marked with a dashed line 30, this semiconductor chip 10 being applied to the upper side 25 of the rewiring plate 2 in a materially bonded manner.
- a contact surface 27 is likewise marked with a dashed line on the top side 23 of the semiconductor chip 10 in FIG. 3.
- a bond connection 21, which is also marked with dashed lines, can thus be arranged from the contact area 27 of the semiconductor chip 10 to the contact connection area 20 on the upper side 25 of the rewiring plate 2.
- the edge of the next stacked semiconductor chip 12 is marked with a dash-and-dot line 32 and set back to such an extent that the contact surface 27 of the semiconductor chip 11 underneath remains freely accessible. It is thus possible to connect the contact area 27 of the semiconductor chip 11 marked with a dash-dotted line to a contact connection area 20 via a bond connection 21 marked with a dash-dotted line.
- the side edge of the fourth semiconductor chip 13 of this stack is marked by a three-dot chain line 33 and has a contact area 27 on the semiconductor chip 13, which is also marked with a three-dot chain line and via a corresponding bond connection 21 with a corresponding contact pad 20 on the top 25 of
- Rewiring plate 2 is connected.
- the four contact pads 20 shown on the top 25 of the rewiring plate 2 are connected via four through contacts 24 to the four outer contact area regions 6, 7, 8 and 9 of an outer contact surface 5 on the underside of the rewiring plate 2.
- the structure on the underside of the rewiring plate 2 is again identified by dashed, hatched areas.
- the semiconductor stack is cast into a plastic mass, which is not shown in FIG. 3, so that only the underside of the rewiring plate 2 is accessible for a test. Due to the arrangement of the invention Rewiring structures 15 make it possible to test each semiconductor chip 10 to 13 of the stack 1 of this semiconductor component 4 individually, even after bonding and also after applying the plastic compound.
- FIG. 4 shows a schematic plan view of a rewiring board 2 with four stacked semiconductor chips 10, 11, 12 and 13, similar to that in FIG. 3. Components with the same functions as in FIG. 3 are identified by the same reference symbols and are not discussed separately. The difference from FIG. 3 is that the lowermost semiconductor chip 10, the edge of which is identified by dashed line 30, does not require any bond connections, but via flip chip contacts with corresponding contact connection areas 16, which are arranged under the semiconductor chip stack 1 on the top side 25 of the rewiring plate 2 are connected.
- the three upper stacked semiconductor chips 11, 12 and 13 are in turn arranged so as to be staggered with their edge sides in such a way that their contact surfaces 27 can be connected via bond connections 21 to the corresponding contact connection surfaces 20 in the edge region 17 of the top side 25 of the rewiring plate 2.
- the external contact area 5 on the underside of the rewiring plate 2 is again divided into four external contact area areas 6, 7, 8 and 9, the external contact area area 6 being reserved for connection to the flip chip contacts of the lowermost semiconductor chip 10.
- the uppermost semiconductor chip 13 can have a larger active upper side 23 than in FIG. 3.
- FIG. 5 shows a schematic cross section through a semiconductor component 4 with semiconductor chip stack 1 according to the first embodiment of the invention according to FIG. 1 with the possibility of individually testing the stacked semiconductor chips 10 and 11 of the semiconductor chip stack 1.
- the semiconductor chip 10 has an active upper side 23 with contact areas 27 which are equipped with flipchip contacts 18. These flip-chip contacts 18 are partially connected via through contacts 24 of the rewiring plate 2 to external contact area regions 6 on the underside 3 of the rewiring plate 2.
- On the rear side 22 of the lower semiconductor chip 10 another semiconductor chip 11 is stacked with its rear side 22, which has an upper side 23 with contact areas 27 in the edge region of the semiconductor chip 11.
- These contact areas 27 of the semiconductor chip 11 are connected via bond connections 21 to corresponding contact connection areas 20 on the upper side 25 of the rewiring board 2.
- the contact connection areas 27 of the upper semiconductor chip 11 are assigned to individual external contact areas 5 in external contact area regions 7.
- the outer contact area regions 6 and 7 are arranged electrically separated from one another at a distance a on the underside 3 of the rewiring plate 2, so that a continuous gap 29 ensures that the contact areas 27 of the upper semiconductor component 11 can be tested via the outer contact area regions 7 and that Contact areas 27 of the lower semiconductor chip 10 can be checked electrically via the external contact area areas 6. This review is also still possible if, as shown in FIG. 5, the semiconductor chip stack 1 is cast into a plastic compound 28.
- FIG. 6 shows a schematic cross section of the semiconductor component 4 according to FIG. 5 after the application of external contacts 14 on the underside 3 of the semiconductor component 4.
- Components with the same functions as in FIG. 5 are identified by the same reference symbols and are not discussed separately.
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/588,401 US7521809B2 (en) | 2004-02-04 | 2005-02-03 | Semiconductor device having a chip stack on a rewiring plate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102004005586.6 | 2004-02-04 | ||
DE102004005586A DE102004005586B3 (de) | 2004-02-04 | 2004-02-04 | Halbleiterbauteil mit einem Halbleiterchipstapel auf einer Umverdrahtungsplatte und Herstellung desselben |
Publications (2)
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WO2005076319A2 true WO2005076319A2 (de) | 2005-08-18 |
WO2005076319A3 WO2005076319A3 (de) | 2005-11-10 |
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PCT/DE2005/000175 WO2005076319A2 (de) | 2004-02-04 | 2005-02-03 | Halbleiterbauteil mit einem halbleiterchipstapel auf einer umverdrahtungsplatte und herstellung desselben |
Country Status (3)
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US (1) | US7521809B2 (de) |
DE (1) | DE102004005586B3 (de) |
WO (1) | WO2005076319A2 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4185499B2 (ja) * | 2005-02-18 | 2008-11-26 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
DE102008014774B4 (de) | 2008-03-18 | 2015-09-03 | Austriamicrosystems Ag | Halbleiteranordnung mit Testanschlüssen und Verfahren zur Messung eines Widerstandes zwischen zwei Anschlüssen eines Wafer-Level-Packages |
US8923004B2 (en) * | 2008-07-31 | 2014-12-30 | Micron Technology, Inc. | Microelectronic packages with small footprints and associated methods of manufacturing |
US8642382B2 (en) * | 2011-06-20 | 2014-02-04 | Stats Chippac Ltd. | Integrated circuit packaging system with support structure and method of manufacture thereof |
CN103489792B (zh) * | 2013-08-06 | 2016-02-03 | 江苏长电科技股份有限公司 | 先封后蚀三维系统级芯片倒装封装结构及工艺方法 |
CN103390563B (zh) * | 2013-08-06 | 2016-03-30 | 江苏长电科技股份有限公司 | 先封后蚀芯片倒装三维系统级金属线路板结构及工艺方法 |
US9462691B1 (en) * | 2014-01-17 | 2016-10-04 | Altera Corporation | Enhanced ball grid array |
US10796975B2 (en) * | 2016-04-02 | 2020-10-06 | Intel Corporation | Semiconductor package with supported stacked die |
US11410932B2 (en) * | 2020-03-30 | 2022-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930599A (en) * | 1996-02-19 | 1999-07-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
US5973403A (en) * | 1996-11-20 | 1999-10-26 | Micron Technology, Inc. | Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
US6018462A (en) * | 1997-06-30 | 2000-01-25 | Nec Corporation | Multi-tip module |
US20020192857A1 (en) * | 2001-06-19 | 2002-12-19 | Yusuke Igarashi | Method for fabricating a circuit device |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61190950A (ja) * | 1985-02-20 | 1986-08-25 | Hitachi Ltd | 半導体装置 |
US7166495B2 (en) * | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
JP2765567B2 (ja) | 1996-06-11 | 1998-06-18 | 日本電気株式会社 | 半導体装置 |
DE19626126C2 (de) * | 1996-06-28 | 1998-04-16 | Fraunhofer Ges Forschung | Verfahren zur Ausbildung einer räumlichen Chipanordnung und räumliche Chipanordung |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
JP3565319B2 (ja) * | 1999-04-14 | 2004-09-15 | シャープ株式会社 | 半導体装置及びその製造方法 |
KR100533673B1 (ko) * | 1999-09-03 | 2005-12-05 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기 |
JP3523189B2 (ja) * | 2000-12-27 | 2004-04-26 | 株式会社東芝 | 半導体装置 |
JP2003197856A (ja) * | 2001-12-28 | 2003-07-11 | Oki Electric Ind Co Ltd | 半導体装置 |
JP3625815B2 (ja) * | 2002-11-12 | 2005-03-02 | 沖電気工業株式会社 | 半導体装置とその製造方法 |
JP3566957B2 (ja) * | 2002-12-24 | 2004-09-15 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
-
2004
- 2004-02-04 DE DE102004005586A patent/DE102004005586B3/de not_active Expired - Fee Related
-
2005
- 2005-02-03 US US10/588,401 patent/US7521809B2/en not_active Expired - Fee Related
- 2005-02-03 WO PCT/DE2005/000175 patent/WO2005076319A2/de active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930599A (en) * | 1996-02-19 | 1999-07-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
US5973403A (en) * | 1996-11-20 | 1999-10-26 | Micron Technology, Inc. | Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
US6018462A (en) * | 1997-06-30 | 2000-01-25 | Nec Corporation | Multi-tip module |
US20020192857A1 (en) * | 2001-06-19 | 2002-12-19 | Yusuke Igarashi | Method for fabricating a circuit device |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN Bd. 1998, Nr. 04, 31. März 1998 (1998-03-31) -& JP 09 330993 A (NEC CORP), 22. Dezember 1997 (1997-12-22) * |
Also Published As
Publication number | Publication date |
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WO2005076319A3 (de) | 2005-11-10 |
US7521809B2 (en) | 2009-04-21 |
US20070262467A1 (en) | 2007-11-15 |
DE102004005586B3 (de) | 2005-09-29 |
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