WO2005076319A3 - Halbleiterbauteil mit einem halbleiterchipstapel auf einer umverdrahtungsplatte und herstellung desselben - Google Patents

Halbleiterbauteil mit einem halbleiterchipstapel auf einer umverdrahtungsplatte und herstellung desselben Download PDF

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Publication number
WO2005076319A3
WO2005076319A3 PCT/DE2005/000175 DE2005000175W WO2005076319A3 WO 2005076319 A3 WO2005076319 A3 WO 2005076319A3 DE 2005000175 W DE2005000175 W DE 2005000175W WO 2005076319 A3 WO2005076319 A3 WO 2005076319A3
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WIPO (PCT)
Prior art keywords
external contact
chip stack
contact surface
semiconductor
semiconductor chip
Prior art date
Application number
PCT/DE2005/000175
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English (en)
French (fr)
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WO2005076319A2 (de
Inventor
Christian Birzer
Jens Pohl
Original Assignee
Infineon Technologies Ag
Christian Birzer
Jens Pohl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Christian Birzer, Jens Pohl filed Critical Infineon Technologies Ag
Priority to US10/588,401 priority Critical patent/US7521809B2/en
Publication of WO2005076319A2 publication Critical patent/WO2005076319A2/de
Publication of WO2005076319A3 publication Critical patent/WO2005076319A3/de

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0101—Neon [Ne]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01021—Scandium [Sc]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0293—Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Die Erfindung betrifft ein Halbleiterbauteil (4) mit einem Halbleiterchipstapel (1) auf einer Umverdrahtungsplatte (2). Auf der Unterseite (3) ist eine Außenkontaktfläche (5) angeordnet, die mehrere voneinander räumlich getrennte Außenkontaktflächen-Bereiche (6, 7) aufweist. Die einzelnen Außenkontaktflächen-Bereiche (6, 7) sind den einzelnen Halbleiterchips (10, 11) des Halbleiterchipstapels (1) zugeordnet, wobei die Außenkontakt-Bereiche (6, 7) einer einzelnen Außenkontaktfläche (5) einen gemeinsamen Außenkontakt (14) aufweisen, der die Außenkontaktflächen-Bereiche (6, 7) elektrisch verbindet.
PCT/DE2005/000175 2004-02-04 2005-02-03 Halbleiterbauteil mit einem halbleiterchipstapel auf einer umverdrahtungsplatte und herstellung desselben WO2005076319A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/588,401 US7521809B2 (en) 2004-02-04 2005-02-03 Semiconductor device having a chip stack on a rewiring plate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004005586A DE102004005586B3 (de) 2004-02-04 2004-02-04 Halbleiterbauteil mit einem Halbleiterchipstapel auf einer Umverdrahtungsplatte und Herstellung desselben
DE102004005586.6 2004-02-04

Publications (2)

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WO2005076319A2 WO2005076319A2 (de) 2005-08-18
WO2005076319A3 true WO2005076319A3 (de) 2005-11-10

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Country Link
US (1) US7521809B2 (de)
DE (1) DE102004005586B3 (de)
WO (1) WO2005076319A2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4185499B2 (ja) * 2005-02-18 2008-11-26 富士通マイクロエレクトロニクス株式会社 半導体装置
DE102008014774B4 (de) 2008-03-18 2015-09-03 Austriamicrosystems Ag Halbleiteranordnung mit Testanschlüssen und Verfahren zur Messung eines Widerstandes zwischen zwei Anschlüssen eines Wafer-Level-Packages
US8923004B2 (en) * 2008-07-31 2014-12-30 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
US8642382B2 (en) * 2011-06-20 2014-02-04 Stats Chippac Ltd. Integrated circuit packaging system with support structure and method of manufacture thereof
CN103390563B (zh) * 2013-08-06 2016-03-30 江苏长电科技股份有限公司 先封后蚀芯片倒装三维系统级金属线路板结构及工艺方法
CN103489792B (zh) * 2013-08-06 2016-02-03 江苏长电科技股份有限公司 先封后蚀三维系统级芯片倒装封装结构及工艺方法
US9462691B1 (en) * 2014-01-17 2016-10-04 Altera Corporation Enhanced ball grid array
WO2017166325A1 (en) * 2016-04-02 2017-10-05 Intel Corporation Semiconductor package with supported stacked die
US11410932B2 (en) * 2020-03-30 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09330993A (ja) * 1996-06-11 1997-12-22 Nec Corp 半導体装置
US5930599A (en) * 1996-02-19 1999-07-27 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US5973403A (en) * 1996-11-20 1999-10-26 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US6018462A (en) * 1997-06-30 2000-01-25 Nec Corporation Multi-tip module
US20020192857A1 (en) * 2001-06-19 2002-12-19 Yusuke Igarashi Method for fabricating a circuit device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61190950A (ja) * 1985-02-20 1986-08-25 Hitachi Ltd 半導体装置
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
DE19626126C2 (de) * 1996-06-28 1998-04-16 Fraunhofer Ges Forschung Verfahren zur Ausbildung einer räumlichen Chipanordnung und räumliche Chipanordung
JPH11219984A (ja) * 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
JP3565319B2 (ja) * 1999-04-14 2004-09-15 シャープ株式会社 半導体装置及びその製造方法
KR100533673B1 (ko) * 1999-09-03 2005-12-05 세이코 엡슨 가부시키가이샤 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기
JP3523189B2 (ja) * 2000-12-27 2004-04-26 株式会社東芝 半導体装置
JP2003197856A (ja) * 2001-12-28 2003-07-11 Oki Electric Ind Co Ltd 半導体装置
JP3625815B2 (ja) * 2002-11-12 2005-03-02 沖電気工業株式会社 半導体装置とその製造方法
JP3566957B2 (ja) * 2002-12-24 2004-09-15 沖電気工業株式会社 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5930599A (en) * 1996-02-19 1999-07-27 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JPH09330993A (ja) * 1996-06-11 1997-12-22 Nec Corp 半導体装置
US5973403A (en) * 1996-11-20 1999-10-26 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US6018462A (en) * 1997-06-30 2000-01-25 Nec Corporation Multi-tip module
US20020192857A1 (en) * 2001-06-19 2002-12-19 Yusuke Igarashi Method for fabricating a circuit device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 04 31 March 1998 (1998-03-31) *

Also Published As

Publication number Publication date
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WO2005076319A2 (de) 2005-08-18
DE102004005586B3 (de) 2005-09-29
US20070262467A1 (en) 2007-11-15

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