WO2005069386A1 - 太陽電池とその製造方法 - Google Patents
太陽電池とその製造方法 Download PDFInfo
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- WO2005069386A1 WO2005069386A1 PCT/JP2005/000247 JP2005000247W WO2005069386A1 WO 2005069386 A1 WO2005069386 A1 WO 2005069386A1 JP 2005000247 W JP2005000247 W JP 2005000247W WO 2005069386 A1 WO2005069386 A1 WO 2005069386A1
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- 238000004519 manufacturing process Methods 0.000 title claims description 58
- 239000000446 fuel Substances 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 183
- 239000013078 crystal Substances 0.000 claims abstract description 172
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0749—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type including a AIBIIICVI compound, e.g. CdS/CulnSe2 [CIS] heterojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
- H01L31/022483—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of zinc oxide [ZnO]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/541—CuInSe2 material PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a solar cell.
- the present invention relates to a substrate type solar cell.
- a substrate, a lower electrode formed on the substrate, a light absorption layer formed on the conductive film, a window layer formed on the light absorption layer, and a window layer are formed.
- a substrate type solar cell including an upper electrode is known.
- a substrate-type solar cell is further known that further includes a nofer layer formed between the light absorption layer and the window layer.
- a conventional substrate-type solar cell specifically, a glass substrate containing an alkali metal such as Na, and a metal such as an MO film formed on the glass substrate by applying a sputtering method or the like.
- n-type transparent conductive film such as Zn 0: A1 film (For example, see JP-A-10-74967).
- p-type Cu (In, Ga) Se crystals are grown slowly over time in order to fabricate solar cells with high energy conversion efficiency.
- a glass substrate As a conventional substrate type solar cell, a glass substrate, a metal film (lower electrode) such as an MO film formed on the glass substrate by applying a notching method, etc., and a metal film P-type Cu (In, Ga) Se formed by applying the selenization method to
- a compound semiconductor layer (light absorption layer) with a chalcopyrite structure with p-type conductivity, such as two layers, and Z formed on the compound semiconductor A structure including a buffer layer such as a ⁇ film, a window layer such as ⁇ : ⁇ 1 film, and an upper electrode has been proposed (see, for example, JP-A-10-135498).
- the selenium method after forming a CuGaZl nZSe precursor (a multilayer film consisting of a CuGa film, an In film, and a Se film), the CuGa ZlnZSe precursor is solid-phase diffused by heating to form a p-type Cu (In, Ga) Se layer
- the CuGaZln precursor is
- a Zn (0, H) film, a Zn (0, S, OH) film, or the like formed by applying a solution method is used as a nofer layer.
- Configurations provided are known (see, for example, Tokio Nakada et al. Thin Solid Film 431-432 (2003) 242-248).
- the result is a solar cell with an energy conversion efficiency of less than 10%. This is because when the p-type Cu (ln, Ga) Se layer is formed at high speed, the crystallinity of the p-type Cu (In, Ga) Se layer deteriorates.
- the CdS layer coverage is insufficient, and it is also a force that causes a low resistance of the shunt resistance in the equivalent circuit.
- This low resistance of the shunt resistance is due to the fact that a high concentration of n-type ITO film is formed on the n-type CdS layer with insufficient coverage, so that a part of the n-type ITO film passes through the n-type CdS layer. This is due to the direct contact with the P-type Cu (In, Ga) Se layer.
- the phenomenon of lowering resistance is not limited to the case of p-type Cu (In, Ga) Se layers, and multi-source deposition is applied.
- the reduction of the shunt resistance is due to the fact that the n-type transparent conductive film is formed on the n-type buffer layer and the n-type window layer with insufficient coverage. This is due to the direct contact with the light absorbing layer without passing through both n-type window layers.
- a compound semiconductor layer formed at a high speed and having an uneven surface, and an n-type window layer with insufficient coverage formed on the compound semiconductor layer.
- the solar cell characteristics such as the energy conversion efficiency of the battery are improved by the high resistance of the shunt resistor in the equivalent circuit of the solar cell, that is, by reducing the leakage current of the solar cell.
- a solar cell according to the present invention includes a substrate, a conductive film formed on the substrate, an ib group element, an mb group element, and a vib formed on the conductive film.
- a compound semiconductor layer having a P-type semiconductor crystal containing a group element, an n-type window layer having an opening formed on the compound semiconductor layer, and a compound semiconductor layer on the n-type window layer and below the opening of the n-type window layer A solar cell including an n-type transparent conductive film formed thereon, wherein the compound semiconductor layer is formed in a part near the surface on the opposite side of the conductive film, and is doped with a p-type semiconductor crystal.
- the n-type impurity means an element that functions as a donor when doped in a p-type semiconductor crystal.
- a method for manufacturing a solar cell according to the present invention includes a step of forming a conductive film on a substrate, a lb group element, an Illb group element, and a Vlb group element on the conductive film.
- a step of growing a P-type semiconductor crystal containing n-type and an n-type having an opening on the p-type semiconductor crystal A method of manufacturing a solar cell, comprising: forming a window layer; and forming an n-type transparent conductive film on a p-type semiconductor crystal on the n-type window layer and under the opening of the n-type window layer, wherein n A step of doping an n-type impurity in the vicinity of the surface of the P-type semiconductor crystal under the opening of the n-type window layer between the step of forming the n-type window layer and the step of forming the n-type transparent conductive film; It is characterized by.
- FIG. 1 is a circuit diagram showing an equivalent circuit for a solar cell according to Embodiment 1.
- FIG. 2 is a schematic cross-sectional view showing a structural example of the solar cell according to Embodiment 1.
- FIG. 3 (A) -FIG. 3 (D) is a schematic cross-sectional view for each process for explaining an example of the first manufacturing method of the solar cell in the first embodiment.
- FIG. 4 (A)-(D) is a schematic cross-sectional view by process for explaining an example of a second manufacturing method of the solar cell in the second embodiment.
- FIG. 5 (A) -FIG. 5 (C) is a schematic cross-sectional view for each process for explaining an example of the third manufacturing method of the solar cell in the third embodiment.
- FIG. 6 is a schematic cross-sectional view showing a structural example of a solar cell according to Embodiment 4.
- the solar cell of the present invention includes a substrate, a conductive film, a compound semiconductor layer having a high resistance portion, an n-type window layer, and an n-type transparent conductive film.
- the surface of the compound semiconductor layer on the n-type window layer side is an uneven surface.
- the n-type window layer has an opening (hereinafter also referred to as “pinhole”), and the high resistance portion is located near the surface of the p-type semiconductor crystal under the opening of the n-type window layer.
- the high resistance portion is a portion formed by doping an n-type impurity in a part near the surface of the p-type semiconductor crystal.
- “near the surface” means a region where the depth of the surface force of the compound semiconductor layer is 500 nm or less.
- the resistivity of the high resistance portion is higher than the resistivity of the portion other than the high resistance portion (hereinafter, this portion is also referred to as “low resistance portion”) when the n-type impurity is not doped in the P-type semiconductor crystal. large.
- the n-type impurity doped in the p-type semiconductor crystal functions as a donor, so This is because the donor concentration increases compared to the low resistance portion, and the carrier concentration determined by the acceptor concentration and the donor concentration in the P-type semiconductor crystal decreases.
- FIG. 1 is a circuit diagram showing an equivalent circuit of the solar cell of the present invention. Note that the equivalent circuit of a conventional solar cell is also represented by the same configuration as the circuit diagram shown in FIG. As shown in FIG. 1, the equivalent circuit of the solar cell of the present invention is connected to the constant current source 4 (short-circuit current) and the constant current source 4 in parallel.
- the constant current source 4 short-circuit current
- the resistance value R of 2 is preferably small. Shunt resistance 1.
- the shunt resistance 1 is preferably 2 k Q 'cm 2 or more.
- the solar cell of the present invention can reduce the area in which the low resistance portion and the n-type transparent conductive film are in direct contact even if the coverage of the n-type window layer is insufficient.
- Shunt resistor 1 can be made high resistance. Therefore, solar cell characteristics such as energy conversion efficiency can be improved. Further, by controlling the size of the high resistance portion and the concentration of the n-type impurity in the high resistance portion, the shunt resistance 1 can be set to 2 k Q′cm 2 or more.
- the resistance of the high resistance portion is larger than the resistance of the n-type window layer.
- the resistance at the portion where the n-type transparent conductive film and the low resistance portion are in contact via the high resistance portion can be greater than the resistance at the portion where the n-type transparent conductive layer is in contact via the n-type window layer.
- the leakage current at the portion where the conductive film and the compound semiconductor layer are in direct contact can be further reduced, that is, the shunt resistance 1 can be further increased.
- the compound semiconductor layer may have a concave surface on the surface opposite to the conductive film, and the high resistance portion may be formed in the vicinity of the concave surface.
- the opening in the n-type window layer with insufficient coverage is formed on the concave surface of the compound semiconductor layer having an uneven surface. Therefore, it is possible to efficiently increase the resistance of the shunt resistor 1 by forming the high resistance portion in the vicinity of the concave surface.
- the high resistance portion may be formed in a part near the concave surface! /, Or may be formed in a wider area including the vicinity of the concave surface.
- corrugated surface although it becomes a factor which generates many pinholes, there exists an effect which improves energy conversion efficiency by incidently reflecting incident sunlight.
- the n-type transparent conductive film is connected to a portion other than the high resistance portion (low resistance portion) in the compound semiconductor layer only through at least one of the n type window layer and the high resistance portion. It is preferable that With this configuration, the low resistance portion and the n-type transparent conductive film are not in direct contact with each other, and the shunt resistor 1 can be made to have a very high resistance.
- the high resistance portion may have at least one element selected from the group consisting of an Ila group element and a lib group element as an n-type impurity.
- group IIa and Group IIb mean “Group 2" and "Group 12" in the long-period periodic table recommended by IUPAC, respectively.
- the high resistance section includes a configuration having one type of Ila group element, a configuration having multiple types of Ila group elements, a configuration having one type of lib group elements, and a plurality of types of lib group elements. And a configuration having at least one Ila group element and at least one lib group element.
- Ila group elements and lib group elements function as donors when doped into p-type semiconductor crystals.
- Ila group elements and lib group elements are easily taken into vacancies that function as acceptors of p-type semiconductor crystals, it is possible to reduce the acceptor concentration and increase the donor concentration. Accordingly, the donor concentration relative to the acceptor concentration in the high resistance portion can be increased efficiently.
- the high resistance part may exhibit very high resistance n-type conductivity but not low resistance n-type conductivity due to an increase in doping amount of the Ila group element and lib group element. Absent.
- the n-type impurity in the high resistance portion is Zn, Mg or Ca so that it can be incorporated into the lb group element vacancies and the like to function as a donor.
- the p-type semiconductor crystal in the compound semiconductor layer contains Cu as a lb group element, and contains at least one element selected from the group consisting of Ga and In as a III b group element, and a Vlb group element.
- a compound semiconductor crystal having a chalcopyrite structure containing at least one element selected from the group consisting of S and Se is preferred. This is because this configuration results in a solar cell that has high energy conversion efficiency and little deterioration over time due to light irradiation.
- the p-type semiconductor crystal of the compound semiconductor layer includes a chalcopyrite-type CuInSe crystal and a chalcopyrite-type Cu (Ga
- the low resistance portion and the high resistance portion may contain other elements as desired as long as the effects of the present invention are not impaired.
- the n-type window layer is preferably a ZnO film or a ZnMgO film.
- the n-type window layer in the solar cell of the present invention may have the same configuration as the n-type window layer in any known solar cell.
- the solar cell of the present invention may further include an n-type buffer layer formed between the compound semiconductor layer and the n-type window layer and having an opening communicating with the opening of the n-type window layer. Even when the compound semiconductor layer and the n-type transparent conductive film are in contact with each other through the communication port that connects the n-type window layer and the n-type buffer layer, the area where the low resistance portion and the n-type transparent conductive film are in direct contact Since it can be reduced, the shunt resistor 1 can be increased in resistance.
- the notfer layer is preferably a Zn (0, OH) film or a Zn (0, S, OH) film.
- the n-type buffer layer in the solar cell of the present invention may have the same configuration as the n-type buffer layer in any known solar cell.
- the n-type transparent conductive film comprises an ITO film, a SnO film, an InO film, ZnO: A1
- a film or a ZnO: B film is preferred.
- the n-type transparent conductive film in the solar cell of the present invention has the same configuration as the n-type transparent conductive film in any known solar cell.
- a substrate containing a la group element (alkali metal element) is preferable.
- “Group Ia” means “Group 1” in the long-period periodic table recommended by IUPAC.
- the substrate contains a la group element, the p-type semiconductor crystal of the compound semiconductor layer is formed when the substrate is formed. This is a force that improves the crystallinity of the p-type semiconductor crystal by diffusing the la group element of the p-type semiconductor crystal through the conductive film.
- it is preferable that the difference between the linear expansion coefficient of the substrate and the linear expansion coefficient of the p-type semiconductor crystal is small. This is because if the difference is small, crystal defects in the p-type semiconductor crystal are reduced.
- the substrate is a glass substrate containing at least one alkali metal element selected from the group consisting of Na (Natrium), K (Potassium), and Li (Lithium) forces.
- the difference between the linear expansion coefficient and the linear expansion coefficient of the p-type semiconductor crystal is preferably in the range below 1 X 10- 6 ⁇ (Kelvin) or more 3 X 10- 6 ⁇ .
- a metal film such as a Mo (molybdenum) film, a Cr (chromium) film, an Au (gold) film, or Pt (platinum) is preferable.
- the conductive film in the solar cell of the present invention may have the same configuration as the conductive film in any known solar cell.
- the method for producing a solar cell of the present invention includes a step of forming a conductive film, a step of growing a p-type semiconductor crystal, a step of forming an n-type window layer having an opening, and an n-type window. A step of doping an n-type impurity in the vicinity of the surface of the p-type semiconductor crystal under the opening of the layer and a step of forming an n-type transparent conductive film.
- the n-type impurity is doped into the p-type semiconductor crystal, thereby selecting a high resistance portion near the surface of the p-type semiconductor crystal under the opening of the n-type window layer. Can be formed.
- the n-type impurity is not doped! /, And the portion becomes a low resistance portion.
- the range is from 0.2 mZ to 2 mZ.
- the film forming speed is 0. min or less.
- the speed is within 5 mZ min.
- the energy conversion efficiency is significantly higher than when a P-type semiconductor crystal is grown at a film formation speed of less than 0.2 mZ as in the past. Mass productivity can be greatly improved without a significant reduction.
- a vapor deposition method or a vapor deposition method is applied to the n-type window layer and the n-type window layer.
- An n-type impurity is deposited on the p-type semiconductor crystal exposed by the opening of the n-type to form an impurity film, and the n-type impurity in the impurity film is diffused into a part of the p-type semiconductor crystal by heat treatment (Hereinafter, also referred to as “first manufacturing method”).
- first manufacturing method the high resistance portion can be reliably formed inside the p-type semiconductor crystal.
- a high resistance portion having a desired size and containing an n-type impurity can be easily formed. It can be done.
- the n-type impurity when depositing the n-type impurity, the n-type impurity may be deposited while changing the deposition direction of the impurity with respect to the substrate. For example, the substrate is rotated at a predetermined angle with respect to the deposition direction of the n-type impurity, or the substrate is powered so as to draw a conical surface with the vertical axis of the substrate surface as the deposition axis central axis. In addition, along with these movements, the angle between the normal direction of the substrate surface and the deposition direction of the n-type impurity is changed.
- the n-type window layer in the compound semiconductor layer is a dent-like concave surface, the n-type is satisfactorily applied to a wide range of the exposed surface. Impurities can be deposited.
- a plating method is applied to expose the p-type semiconductor connection exposed through the opening of the n-type window layer. It is possible to apply a method in which an n-type impurity is deposited on the crystal to form an impurity film, and the n-type impurity in the impurity film is diffused into a part of the p-type semiconductor crystal by heat treatment (hereinafter, “ Also referred to as “second manufacturing method”). According to the second manufacturing method, the high resistance portion can be reliably formed inside the p-type semiconductor crystal.
- the impurity film can be selectively formed on the p-type semiconductor crystal exposed by the opening of the n-type window layer, Can be efficiently formed in an effective portion. Furthermore, even if the exposed surface exposed by the opening of the n-type window layer in the p-type semiconductor crystal is a concave surface that enters into a bay shape, impurities can be reliably deposited on the concave surface that enters into the bay shape. it can. Also, by controlling the film thickness of the impurity film, the processing temperature and the processing time in the heat treatment, it is possible to easily form a high resistance portion having a desired size and containing an n-type impurity at a desired concentration. it can
- an impurity film is interposed between the step of doping the p-type semiconductor crystal with an n-type impurity and the step of forming an n-type transparent conductive film.
- the method further comprises the step of removing. If the impurity film remains, the series resistance 2 (R) in the equivalent circuit of the solar cell shown in FIG. 1 is increased, and this is a force that deteriorates the solar cell characteristics such as energy conversion efficiency and curve factor.
- a part of the p-type semiconductor crystal is applied through an opening of the n-type window layer by applying an ion implantation method.
- a method of implanting n-type impurities can be applied to (hereinafter also referred to as “third manufacturing method”).
- the third manufacturing method the high resistance portion can be reliably formed inside the p-type semiconductor crystal. Also, by adjusting the dose, a high resistance portion having a desired n-type impurity concentration can be easily formed.
- the n-type impurity may be implanted while changing the implantation direction of the n-type impurity ions into the substrate.
- the substrate may be rotated so that the substrate is tilted at a predetermined angle with respect to the n-type impurity ion implantation direction, or the substrate surface is driven to draw a conical surface with the normal force-type impurity ion implantation direction as the central axis.
- the angle between the normal direction of the substrate surface and the implantation direction of the n-type impurity ions is changed along with the movement.
- the step of doping the n-type impurity into the p-type semiconductor crystal it is preferable to perform a heat treatment after the n-type impurity is implanted. If heat treatment is performed, the damage that occurs during ion implantation of n-type impurities can be recovered. In addition, the ion-implanted n-type impurity can be diffused in the p-type semiconductor crystal. Further, by controlling the treatment temperature and treatment time in the heat treatment, a high resistance portion having a desired size and containing an n-type impurity at a desired concentration can be easily formed.
- an opening is formed between the step of growing the p-type semiconductor crystal and the step of forming the n-type window layer.
- the method may further include the step of forming an n-type buffer layer having the same. If this method is applied, a solar cell having an n-type buffer layer formed between a p-type semiconductor crystal and an n-type window layer can be manufactured.
- the n-type window layer, the n-type buffer layer, and the n-type transparent conductive film known techniques may be used, respectively.
- FIG. 2 is a schematic cross-sectional view showing the structure of the solar cell of the first embodiment.
- FIG. 3A to FIG. 3D are schematic sectional views for explaining the first manufacturing method for manufacturing the solar cell of the first embodiment.
- 3A shows a process of laminating a conductive film, a p-type semiconductor crystal, and an n-type window layer on a substrate
- FIG. 3B shows an impurity film formed by applying a vacuum evaporation method.
- 3 (C) shows a step of diffusing the shape impurity
- FIG. 3 (D) shows a step of removing the impurity film.
- the solar cell shown in FIG. 2 is formed on the substrate 21, the conductive film 22 formed on the substrate 21, the compound semiconductor layer 23 formed on the conductive film 22, and the compound semiconductor layer 23.
- N-type conductive n-type window layer 24 having pinholes 29 (openings), and n-type window layer 24 and compound semiconductor layer 23 exposed by n-type window layer 24 pinhole 29.
- an n-type transparent conductive film 25 is formed on the p-type conductive low-resistance portion 23A formed on the conductive film 22, and on the low-resistance portion 23A, and is formed below the pinhole 29 of the n-type window layer 24 and is n-type.
- a high resistance portion 23B doped with impurities.
- the n-type transparent conductive film 25 is connected to the low-resistance part 23A only through the high-resistance part 23B or the n-type window layer 24. It is preferable.
- the substrate 21 is a substrate containing a la group element (alkali metal) such as Na
- the conductive film 22 is a metal film such as a Mo film
- the compound semiconductor layer 23 The p-type semiconductor crystal is p-type such as CuInSe crystal, Cu (Ga, In) Se crystal, CuIn (S, Se) crystal, etc.
- Conductive chalcopyrite structure lb—Ilb—VIb crystal, impurity doped in high resistance 23B is Zn
- n-type window layer 24 is n-type ZnMgO film
- n-type transparent conductive film 25 is preferably an ITO film, SnO film, InO film, ZnO: A1 film or ZnO: B film.
- the difference between the linear expansion coefficient and the linear expansion coefficient of the p-type semiconductor crystal substrate 21 is preferably in the l X lo K or 3 X 10- 6 ⁇ less.
- the solar cell of the first embodiment having the structure shown in FIG. 2 is manufactured as follows. First, as shown in FIG. 3A, a conductive film 22 is formed on the substrate 21 by applying a sputtering method or the like.
- the sheet resistance of the conductive film 22 is preferably 0.5 ⁇ or lower.
- a Mo film having a thickness of about 0.4 m is formed by applying a sputtering method.
- a P-type semiconductor crystal 33 is formed on the conductive film 22 by applying a multi-source deposition method or a selenization method.
- the p-type semiconductor crystal 33 is a chalcopyrite-type Cu (Ga, In) Se crystal, Cu, Ga, In, Se is often used as the evaporation source.
- the original vapor deposition method can be applied. At this time, it is preferable that the film is grown at a film forming speed within a range from 0. minutes to 1. minutes.
- the selenization method after forming the CuGaZlnZSe precursor by sputtering, the CuGaZlnZSe precursor is heated to about 450-550 ° C, and a Cu (Ga, In) Se film is formed by solid phase diffusion. Or
- the CuGaZln precursor is formed by sputtering.
- a Cu (Ga, In) Se film is formed by heat treatment in Se gas. Multi-source deposition or
- the p-type semiconductor crystal 33 formed by applying the selenization method has an uneven surface on the upper surface.
- the n-type window layer 24 is formed on the uneven surface of the p-type semiconductor crystal 33 by applying a sputtering method or a solution method.
- a sputtering method or a solution method For example, as the n-type window layer 24, ZnMgO having a film thickness of about lOOnm is formed by applying a sputtering method using ZnO and MgO as targets. Since the top surface of the p-type semiconductor crystal 33 is an uneven surface, the n-type window layer 24 has pinholes 2 9 (opening) is formed.
- the upper force of the n-type window layer 24 is n-type impurities by applying a vacuum deposition method or a CVD method (chemical vapor deposition method).
- Zn is deposited to form an impurity film 36 on the n-type window layer 24 and inside the pinhole 29 of the n-type window layer 24.
- a Zn film having a thickness of about 20 nm is formed as the impurity film 36.
- the stacked body including the substrate 21, the conductive film 22, the p-type semiconductor crystal 33, the n-type window layer 24 and the impurity film 36 is annealed (heat treatment). For example, heat in a nitrogen atmosphere at 170 ° C for 20 minutes.
- the n-type impurity diffuses into the p-type semiconductor crystal 33 from the portion of the impurity film 36 (impurity film inside the pinhole 29) that is in direct contact with the p-type semiconductor crystal 33, as shown in FIG.
- the compound semiconductor layer 23 having the high resistance portion 23B including the n-type impurity diffused from the impurity film 36 and the low resistance portion 23A not including the n-type impurity is formed.
- the impurity film 36 remaining on the compound semiconductor layer 23 and the n-type window layer 24 is removed by applying an etching method.
- a dry etching technique may be used to remove the impurity film 36, but in order to remove only the impurity film 36 in a simple and reliable manner, wet etching in contact with an etching solution such as hydrochloric acid is used. It is preferable. For example, the laminate is immersed in hydrochloric acid for several seconds. After removing the impurity film 36 (see FIG. 3C), the substrate 21, the conductive film 22, the compound semiconductor layer 23 having the low resistance portion 23 A and the high resistance portion 23 B, and the n-type window layer 24 are formed. Wash the laminate with a cleaning solution such as pure water.
- the solar cell of the first embodiment having the structure shown in FIG. 2 can be manufactured.
- the steps shown in Fig. 3 (B)-Fig. 3 (D) are performed.
- the shunt resistance 1 (see Fig. 1) in the equivalent circuit can be reliably increased compared to the solar cell of the comparative example that is manufactured without passing through and the high resistance portion 23B does not contain n-type impurities.
- the solar cell of the first embodiment is The shunt resistance 1 of the equivalent circuit may be 5 times or more compared to the solar cell of the comparative example with respect to the first embodiment, or may be 2 k ⁇ 'cm 2 or more which is a suitable value for the solar cell. it can.
- the energy conversion efficiency can be set to 17% or more, and the n value as the diode index can be set to 1.5 or less.
- a buffer layer may be formed between the compound semiconductor layer and the n-type window layer if desired.
- FIGS. 4A to 4D are schematic sectional views for explaining the second manufacturing method for manufacturing the solar cell of the second embodiment.
- 4A shows the process of forming the impurity film by applying the plating method
- FIG. 4B shows the process after the process of forming the impurity film
- FIG. 4C shows n
- 4D shows the process of diffusing the impurity
- FIG. 4D shows the process of removing the impurity film.
- the solar cell of the second embodiment is manufactured by the same method as the method of manufacturing the solar cell of the first embodiment, except for the method of forming the high resistance portion. Further, the structure of the solar cell of the second embodiment is substantially the same as the solar cell of the first embodiment shown in FIG. Therefore, only the second manufacturing method for manufacturing the solar cell of the second embodiment will be described. Refer to Figure 2 as necessary.
- the solar cell of the second embodiment is manufactured as follows. First, as shown in FIG. 4 (A), the n-type having the conductive film 22, the p-type semiconductor crystal 33, and the pinhole 29 on the substrate 21 by the same method as in the first embodiment.
- the window layer 24 is laminated in this order to form a laminate.
- the Zn metal casing provided in the electroplating solution 42 is used.
- a voltage is applied with the electrode 41 formed as an anode and the conductive film 22 of the laminate as a cathode.
- ionized n-type impurities n-type impurity ions
- p Semiconductor connection Precipitates selectively on the surface of crystal 33.
- n-type impurity ions In order to form a pn junction in which the resistance of the n-type window layer 24 is large and the n-type window layer 24 and the compound semiconductor layer 23 are applied with a reverse bias voltage, an n-type window layer 24 having n-type conductivity is provided. The n-type impurity ions are not deposited on the n-type window layer 24 or only a small amount are deposited. On the other hand, since a current flows through the surface of the p-type semiconductor crystal 33 exposed by the pinhole 29 of the n-type window layer 24, n-type impurity ions are sequentially deposited on the surface.
- n-type impurity ions can be selectively deposited on the surface of the p-type semiconductor crystal 33 exposed by the pinhole 29 of the n-type window layer 24.
- the impurity film 46 is selectively formed on the p-type semiconductor crystal 33 exposed by the pinhole 29 of the n-type window layer 24.
- a Zn film having a thickness of about 20 nm is formed as the impurity film 46.
- the stacked body on which the impurity film 46 is formed is annealed (heat treatment), and the n-type impurity constituting the impurity film 46 is diffused into the p-type semiconductor crystal 33.
- heat treatment heat at 170 ° C for 20 minutes in a nitrogen atmosphere.
- n -type impurities diffuse into the p-type semiconductor crystal 33 from the portion of the impurity film 36 (impurity film inside the pinhole 29) that is in direct contact with the p-type semiconductor crystal 33, as shown in FIG.
- the compound semiconductor layer 23 having the high resistance portion 23B including the n-type impurity diffused from the impurity film 36 and the low resistance portion 23A not including the n-type impurity diffused from the impurity film 36 is formed. .
- the impurity film 46 remaining on the compound semiconductor layer 23 is removed by the same method as in the first embodiment. After the removal of the impurity film 46 (see FIG. 4C), the substrate 21, the conductive film 22, the compound semiconductor layer 23 having the low resistance portion 23 A and the high resistance portion 23 B, and the window layer 24 are formed. It is preferable to wash the laminate.
- the solar cell of the second embodiment can be manufactured.
- the shunt resistance 1 (see Fig. 1) in the circuit can be reliably increased.
- the shunt resistance 1 of the equivalent circuit for the solar cell of the second embodiment is set to 5 times or more compared to the solar cell of the comparative example for the second embodiment, or a value suitable for a solar cell. It can be 2k ⁇ 'cm 2 or more.
- the energy conversion efficiency can be set to 17% or more, and the n value as a diode index can be set to 1.5 or less.
- FIGS. 5A to 5C are schematic cross-sectional views by process for explaining a third manufacturing method for manufacturing the solar cell of the present invention.
- 5A shows a process of stacking a conductive film, a p-type semiconductor crystal, and an n-type window layer on a substrate
- FIG. 5B shows an n-type impurity implantation using an ion implantation method
- Fig. 5 (C) shows the process of diffusing the implanted n-type impurity to form the high resistance portion.
- the solar cell in the third embodiment is manufactured by the same manufacturing method as the solar cell in the first embodiment and the second embodiment except for the method of forming the high resistance portion. Further, the structure of the solar cell in the third embodiment is substantially the same as the solar cell in the first embodiment shown in FIG. Therefore, only the third manufacturing method for manufacturing the solar cell of the third embodiment will be described. Refer to Figure 2 as necessary.
- the solar cell of the third embodiment is manufactured as follows. First, as shown in FIG. 5A, n-type having conductive film 22, p-type semiconductor crystal 33, and pinhole 29 on substrate 21 by the same method as in the first embodiment.
- the window layer 24 is laminated in this order to form a laminate.
- n-type impurities n-type impurity ions
- n-type impurities n-type impurity ions
- n-type impurities are introduced into the p-type semiconductor crystal 33 through the pinhole 29 of the n-type window layer 24. Ions are implanted, and an ion implanted portion 56B is formed inside the p-type semiconductor crystal 33 below the pinhole 29 in the n-type window layer 24.
- Zn, Mg or Ca is preferable.
- the portion where impurity ions are not implanted is the non-ion implanted portion 56A.
- an ion implanted portion 56B is obtained by implanting Zn ions accelerated to an energy of about 50 keV until the dose amount is 5 ⁇ 10 15 or more and 5 ⁇ 10 16 Zcm 2.
- Zn ions penetrate to a depth of approximately 0.01 ⁇ m—0.05 ⁇ m.
- the acceleration energy and dose should be adjusted as appropriate depending on the type of element used as impurity ions, the type of p-type semiconductor crystal 33 to be ion-implanted, and the like.
- the substrate 21, the conductive film 22, the p-type semiconductor crystal 33 having the non-ion implantation portion 56A and the ion implantation portion 56B, and the n-type window layer 24 are formed.
- the provided stacked body is annealed (heat treatment) to diffuse the n-type impurity in the ion implantation part 56B into the non-ion implantation part 56A.
- Layer 23 is formed.
- this annealing can recover the damage that the compound semiconductor layer 23 (p-type semiconductor crystal 33) received during ion implantation.
- the solar cell of the third embodiment is manufactured.
- FIG. 5A In the solar cell of the third embodiment manufactured through the steps of FIGS. 5A to 5C, FIG.
- the shunt resistance 1 in the equivalent circuit is more reliably High resistance can be achieved.
- the shunt resistance of the equivalent circuit for the solar cell of the third embodiment is set to 5 times or more compared to the solar cell of the comparative example for the third embodiment, or 2k, which is a suitable value for a solar cell. It can also be ⁇ ′cm 2 or more.
- the energy conversion efficiency can be set to 17% or more. It is also possible to set the n value, which is the index, to 1.5 or less.
- Embodiment 4 an embodiment of a solar cell having an n-type buffer layer will be described with reference to FIG.
- the solar cell of the fourth embodiment has the same configuration as the solar cell of the first to third embodiments except that the n-type window layer is a ZnO film and has an n-type buffer layer. . Therefore, the same members are denoted by the same reference numerals, and detailed description thereof is omitted.
- the solar cell shown in FIG. 6 includes a substrate 21, a conductive film 22, a compound semiconductor layer 23, an n-type conductive n-type window layer 24 having a pinhole 29 (opening), n An n-type buffer layer 26 having a pinhole 39 formed between the compound-type transparent conductive film 25 and the compound semiconductor layer 23 and the n-type window layer 24 and communicating with the pinhole 29 of the n-type window layer 24 ing.
- the n-type window layer 24 is preferably a ZnO film
- the n-type buffer layer 26 is preferably a Zn (0, OH) film or a Zn (0, S, OH) film.
- the solar cell of the fourth embodiment was manufactured as follows.
- the method for manufacturing a solar cell according to the fourth embodiment is after the p-type semiconductor crystal is grown in the first to third manufacturing methods described above, and before the step of forming the n-type window layer 24.
- An n-type buffer layer 26 is formed by applying the solution method. For example, an n-type buffer layer 26 having a thickness of about lOOnm is formed.
- the n-type buffer layer 26 is a Zn (0, OH) film, after the p-type semiconductor crystal is grown, the stacked body including the substrate 21, the conductive film 22, and the p-type semiconductor crystal is reduced to about PH7-12.
- a Zn (0, OH) film can be formed by adjusting the temperature of the solution to 50 to 80 ° C and bringing it into contact with ammonia water in which a zinc salt is dissolved.
- the n-type buffer layer 26 is a Zn (0, S, OH) film
- the laminate including the substrate 21, the conductive film 22, and the p-type semiconductor crystal is adjusted to about PH7-12
- a Zn (0, S, OH) film can be formed by contact with ammonia water in which the zinc salt and the salt containing rhodium are dissolved, kept at 50-80 ° C. Since the upper surface of the p-type semiconductor crystal is an uneven surface, a pinhole 39 (opening) is formed in the n-type buffer layer 26.
- a sputtering method or a solution method is applied to form a ZnO film as the n-type window layer 24 on the uneven surface of the n-type buffer layer 26.
- ZnO A ZnO film with a film thickness of about lOOnm is formed by applying the sputtering method. Since the upper surface of the p-type semiconductor crystal and the n-type buffer layer 26 is an uneven surface, a pinhole 29 (opening) is formed in the n-type window layer.
- the solar cell of the present fourth embodiment is manufactured in the same manner as in the first to third manufacturing methods described above.
- the shunt resistance 1 in the equivalent circuit (Fig. 1) is compared to the solar cell of the comparative example having the same configuration except that the high resistance portion 23B does not contain an n-type impurity. Can be reliably increased in resistance. Furthermore, the shunt resistance of the equivalent circuit for the solar cell of the fourth embodiment is set to 5 times or more as compared with the solar cell of the comparative example for the fourth embodiment, or 2 k ⁇ which is a suitable value for the solar cell. It can be 'cm 2 or more. In the solar cell of the fourth embodiment, the energy conversion efficiency can be set to 17% or more, and the n value as the diode index can be set to 1.5 or less.
- Example 1 an example of the solar cell according to Embodiment 1 described above will be described.
- the substrate 21 is a soda lime glass substrate
- the conductive film 22 is a Mo film
- the p-type semiconductor crystal of the compound semiconductor layer 23 is a p of the chalcopyrite structure.
- n-type impurity doped in the high resistance portion 23B is Zn
- the n-type window layer 24 is
- the n-type ZnMgO film was used, and the n-type transparent conductive film 25 was an ITO film.
- the resistance of the high resistance part 23B was made larger than that of the n-type ZnMgO film. Further, the ITO film was formed so as to be substantially connected to the low resistance portion 23A only through at least one of the n-type Zn MgO film and the high resistance portion 23B.
- the solar cell of Example 1 was manufactured as follows. First, as shown in FIG. 3A, a Mo film having a thickness of about 400 nm was formed on a soda lime glass substrate as the substrate 21 by applying a sputtering method or the like as the conductive film 22. The sheet resistance of the Mo film was about 0.5 ⁇ / mouth. Next, as shown in Fig. 3 (A), as the p-type semiconductor crystal 33, a p-type Cu (Ga, In) Se crystal having a chalcopyrite structure is formed on the Mo film by applying a vacuum deposition method. About:
- the film was grown at a film forming speed of mZ until the average film thickness reached about 2 m.
- the surface of p-type Cu (Ga, In) Se crystal was uneven.
- an n-type window layer 24 is formed.
- p-type Cu (Ga, In) Se bonding is applied by sputtering using ZnO and MgO as targets.
- n-type ZnMgO film with a thickness of about lOOnm was formed on 2 crystals.
- pinholes 29 (openings) were formed in the n-type ZnMgO film.
- the pinhole 29 is substantially a concave surface of the p-type Cu (Ga, In) Se crystal.
- Zn was deposited on 2 to form a Zn film having a thickness of about 20 nm as the impurity film 36.
- a compound semiconductor layer 23 having a low resistance portion 23A not containing Zn that diffuses was formed.
- the stacked body in which the high resistance portion 23B is formed is immersed in a hydrochloric acid solution prepared as an etching solution for 3 minutes, and the Z remaining on the p-type Cu (Ga, In) Se crystal and the n-type ZnMgO film
- Example 1 a sputtering method was applied to form an ITO film as the n-type transparent conductive film 25 on the n-type ZnMgO film and the high resistance portion 23B. Thereby, the manufacture of the solar cell of Example 1 was completed.
- the solar cell of Example 1 has a shunt resistance of about 3 kQ'cm 2 , and the solar cell of Example 1 is not used except that the step (impurity film) for forming the high resistance portion 23B is not performed. Compared to the solar cell of Comparative Example 1 which was manufactured by the same manufacturing method as the battery and did not contain Zn in the high resistance portion 23B, it was about 6 times. In addition, the energy conversion efficiency of the solar cell of Example 1 was 17.6%.
- the n value (diode index) of the solar cell of Example 1 is 1.47, and the p-type Cu (Ga, In) Se crystal in the solar cell of Example 1 is polycrystalline.
- Example 2 In Example 2, an example of the solar cell according to Embodiment 2 will be described with reference to FIG. 2 and FIGS. 4 (A) and 1 (D).
- the substrate 21 is a soda lime glass substrate
- the conductive film 22 is a Mo film
- the p-type semiconductor crystal of the compound semiconductor layer 23 is a chalcopyrite structure.
- the n-type impurity doped in the high resistance portion 23B is Zn
- the n-type window layer is a 24-type ZnMgO film
- the n-type transparent conductive film 25 is an ITO film.
- the resistance of the high resistance part 23B was made larger than that of the n-type ZnMgO film.
- the ITO film was formed so as to be connected to the low resistance portion 23A substantially only through at least one of the n-type ZnMgO film and the high resistance portion 23B.
- the solar cell of Example 2 was manufactured as follows. First, as shown in FIG. 4A, a sputtering method or the like was applied to form a Mo film with a film thickness of about 400 nm on a soda lime glass substrate. The sheet resistance of the Mo film was about 0.5 ⁇ . Next, as shown in Fig. 4 (A), a vacuum deposition method is applied, and a p-type semiconductor crystal 33 is formed on the Mo film as a p-type Cu (Ga, In) Se crystal with a chalconelite structure. 1
- the film was grown to a film thickness of about 2 ⁇ m at a deposition rate of 2 mZ.
- the surface of p-type Cu (Ga, In) Se crystal was uneven.
- an n-type ZnMgO film having a thickness of about lOOnm was formed as an n-type window layer 24 on the p-type semiconductor crystal 33 by applying a sputtering method using ZnO and MgO as a target. . Since the surface of the p-type Cu (Ga, In) Se crystal is an uneven surface, the n-type ZnMgO film has a pin
- Pinhole 29 (opening) was formed. Pinhole 29 is essentially a p-type Cu (Ga, In) Se crystal
- a soda-lime glass substrate a Mo film, p-type Cu (Ga , In) Se crystal and n-type Zn
- the laminate provided with the MgO film was immersed. After immersing the laminate, the Zn electrode 41, which is placed in the electroplating solution 42 and also has the Zn (n-type impurity) force, is used as the anode, and the Mo film of the laminate is used as the cathode. 0.5-0.6V A voltage in the range was applied for 3 minutes. By applying voltage, Zn + ions (n-type impurity ions) are eluted from the Zn electrode 41 into the electroplating solution 42, and the p-type Cu (Ga, In) exposed through the pinhole 29 of the eluted Zn + ion-type ZnMgO film Se crystal
- the laminate on which the Zn film was formed was annealed at a substrate temperature of 170 ° C. for 20 minutes. As a result, as shown in FIG.
- the compound semiconductor layer 23 having the high resistance portion 23B containing Zn and the low resistance portion 23A not containing Zn diffusing from the Zn film was formed.
- a wet etching method is applied to immerse the stacked body including the compound semiconductor layer 23 having the low resistance portion 23A and the high resistance portion 23B in a hydrochloric acid solution, so that the n-type ZnMgO film and the high resistance portion 23B are immersed. The remaining Zn film was removed.
- the laminate from which the Zn film was removed was washed with pure water.
- an ITO film was formed as an n-type transparent conductive film 25 on the high resistance portion 23B and the n-type ZnMg 2 O film by applying a sputtering method. Thereby, the production of the solar cell of Example 2 was completed.
- the shunt resistance 1 (see FIG. 1) of the equivalent circuit for the solar cell of Example 2 is about 2 kQ ⁇ cm 2 , and this example is performed except that the process for forming the high resistance part 23B is not performed. Compared to the solar cell of Comparative Example 2 which was manufactured by the same manufacturing method as the solar cell of Example 2 and did not contain Zn in the high resistance portion 23B, it was about 5 times. In addition, the energy conversion efficiency of the solar cell of Example 2 was 17%. Further, the n value (diode index) of the solar cell of Example 2 is 1.5, and the p-type Cu (Ga, In) Se crystal in the solar cell of Example 2 is polycrystalline.
- Example 3 an example of the solar cell according to Embodiment 3 described above will be described.
- the substrate 21 is a soda lime glass substrate
- the conductive film 22 is an Mo film
- the p-type semiconductor crystal of the compound semiconductor layer 23 is a p of the chalcopyrite structure.
- n-type impurity doped in the high resistance portion 23B is Zn
- the n-type window layer 24 is
- the n-type ZnMgO film was used, and the n-type transparent conductive film 25 was an ITO film.
- the resistance of the high resistance part 23B was made larger than that of the n-type ZnMgO film.
- the ITO film was formed so as to be substantially connected to the low resistance portion 23A only through at least one of the n-type Zn MgO film and the high resistance portion 23B.
- the solar cell of Example 3 was manufactured as follows. First, as shown in FIG. 5A, a Mo film having a thickness of about 400 nm was formed as the conductive film 22 on a soda lime glass substrate as the substrate 21 by applying a sputtering method or the like.
- the sheet resistance of the Mo film was about 0.5 ⁇ / ⁇ .
- a vacuum deposition method is applied to form a p-type Cu (Ga, In) Se crystal having a chalcopyrite structure as a P-type semiconductor crystal 33 on the Mo film.
- an n-type ZnMgO film is formed as an n-type window layer 24 on a p-type Cu (Ga, In) Se crystal by sputtering.
- a pinhole 29 (opening) was formed in the gO film.
- the pinhole 29 was formed substantially in the vicinity of the concave surface on the concave-convex surface of the p-type Cu (Ga, In) Se crystal.
- a p-type Cu (Ga, In) Se crystal having an ion implantation portion 56B and a non-ion implantation portion 56A in which impurity ions are not implanted is provided. Based on laminated body
- Annealing was performed at a plate temperature of 170 ° C for 20 minutes to diffuse the injected Zn inside the p-type Cu (Ga, In) Se crystal. As a result, the high resistance portion 23B having Zn and the Zn film are expanded.
- a compound semiconductor layer 23 having a low resistance portion 23A not containing Zn to be diffused was formed. This annealing reduces the damage that the p-type Cu (Ga, In) Se crystal received during ion implantation.
- an n-type transparent conductive film 25 was formed on the n-type ZnMgO film and the surface of the high resistance portion 23B by applying a sputtering method. Thereby, the manufacture of the solar cell of Example 3 was completed.
- the shunt resistance 1 (see Fig. 1) of the equivalent circuit for the solar cell of Example 3 is about 2 k Q ⁇ cm 2 , except that the steps of ion implantation and annealing of Zn are not performed. It is manufactured by the same manufacturing method as the solar cell of Example 3, and the high resistance portion 23B contains Zn. Compared to the solar cell of the comparative example without it, it was about 5 times. In addition, the energy conversion efficiency of the solar cell of Example 3 was 17%. Further, the n value (diode index) of the solar cell of Example 3 is 1.5, and the p-type Cu (Ga, In) Se crystal in the solar cell of Example 3 is obtained.
- the present invention can be used to increase the shunt resistance of an equivalent circuit for a solar cell and improve the energy conversion efficiency of the solar cell. Further, the present invention can be used to improve the mass productivity of solar cells.
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Abstract
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Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/564,116 US7557294B2 (en) | 2004-01-13 | 2005-01-12 | Solar cell and production thereof |
AT05703486T ATE467909T1 (de) | 2004-01-13 | 2005-01-12 | Solarzelle und herstellungsverfahren |
EP05703486A EP1705717B1 (en) | 2004-01-13 | 2005-01-12 | Solar cell and production method |
JP2005517041A JP4098330B2 (ja) | 2004-01-13 | 2005-01-12 | 太陽電池とその製造方法 |
DE602005021200T DE602005021200D1 (de) | 2004-01-13 | 2005-01-12 | Solarzelle und Herstellungsverfahren |
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US (1) | US7557294B2 (ja) |
EP (1) | EP1705717B1 (ja) |
JP (1) | JP4098330B2 (ja) |
CN (1) | CN100459174C (ja) |
AT (1) | ATE467909T1 (ja) |
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WO (1) | WO2005069386A1 (ja) |
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JP2010219097A (ja) * | 2009-03-13 | 2010-09-30 | Tdk Corp | 太陽電池、及び太陽電池の製造方法 |
JP2011176283A (ja) * | 2010-01-29 | 2011-09-08 | Fujifilm Corp | 光電変換素子の製造方法 |
WO2011136249A1 (ja) * | 2010-04-27 | 2011-11-03 | 京セラ株式会社 | 光電変換素子および光電変換装置ならびに光電変換素子の製造方法 |
WO2012063440A1 (ja) * | 2010-11-09 | 2012-05-18 | 富士フイルム株式会社 | 光電変換素子の製造方法 |
JP2014114207A (ja) * | 2012-11-19 | 2014-06-26 | Tosoh Corp | 酸化物焼結体、それを用いたスパッタリングターゲット及び酸化物膜 |
JP6004460B2 (ja) * | 2013-03-26 | 2016-10-05 | キヤノンアネルバ株式会社 | 太陽電池の製造方法、および太陽電池 |
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US20080290875A1 (en) * | 1996-11-04 | 2008-11-27 | Park Larry A | Seismic activity detector |
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- 2005-01-12 JP JP2005517041A patent/JP4098330B2/ja not_active Expired - Fee Related
- 2005-01-12 CN CNB2005800008040A patent/CN100459174C/zh not_active Expired - Fee Related
- 2005-01-12 WO PCT/JP2005/000247 patent/WO2005069386A1/ja not_active Application Discontinuation
- 2005-01-12 US US10/564,116 patent/US7557294B2/en active Active
- 2005-01-12 EP EP05703486A patent/EP1705717B1/en not_active Not-in-force
- 2005-01-12 AT AT05703486T patent/ATE467909T1/de not_active IP Right Cessation
- 2005-01-12 DE DE602005021200T patent/DE602005021200D1/de active Active
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JP2010219097A (ja) * | 2009-03-13 | 2010-09-30 | Tdk Corp | 太陽電池、及び太陽電池の製造方法 |
JP2011176283A (ja) * | 2010-01-29 | 2011-09-08 | Fujifilm Corp | 光電変換素子の製造方法 |
WO2011136249A1 (ja) * | 2010-04-27 | 2011-11-03 | 京セラ株式会社 | 光電変換素子および光電変換装置ならびに光電変換素子の製造方法 |
JPWO2011136249A1 (ja) * | 2010-04-27 | 2013-07-22 | 京セラ株式会社 | 光電変換素子および光電変換装置ならびに光電変換素子の製造方法 |
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JP6004460B2 (ja) * | 2013-03-26 | 2016-10-05 | キヤノンアネルバ株式会社 | 太陽電池の製造方法、および太陽電池 |
Also Published As
Publication number | Publication date |
---|---|
US7557294B2 (en) | 2009-07-07 |
EP1705717A4 (en) | 2009-04-08 |
CN1842920A (zh) | 2006-10-04 |
JP4098330B2 (ja) | 2008-06-11 |
EP1705717B1 (en) | 2010-05-12 |
US20070295396A1 (en) | 2007-12-27 |
CN100459174C (zh) | 2009-02-04 |
JPWO2005069386A1 (ja) | 2007-12-27 |
ATE467909T1 (de) | 2010-05-15 |
EP1705717A1 (en) | 2006-09-27 |
DE602005021200D1 (de) | 2010-06-24 |
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