WO2004090972A1 - 基板処理システムおよびその制御方法、制御プログラム、記憶媒体 - Google Patents
基板処理システムおよびその制御方法、制御プログラム、記憶媒体 Download PDFInfo
- Publication number
- WO2004090972A1 WO2004090972A1 PCT/JP2004/004383 JP2004004383W WO2004090972A1 WO 2004090972 A1 WO2004090972 A1 WO 2004090972A1 JP 2004004383 W JP2004004383 W JP 2004004383W WO 2004090972 A1 WO2004090972 A1 WO 2004090972A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transfer
- substrate
- schedule
- modules
- module
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM]
- G05B19/4189—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM] characterised by the transport system
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67276—Production flow monitoring, e.g. for increasing throughput
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/32—Operator till task planning
- G05B2219/32244—By using graphical display of array and selecting elements, rearrange them
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/45—Nc applications
- G05B2219/45031—Manufacturing semiconductor wafers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Definitions
- the present invention relates to a substrate processing system for performing a process before and after an exposure process on a substrate such as a semiconductor wafer, a control method thereof, a control program, and a storage medium storing the program.
- a resist solution is supplied to the surface of a semiconductor wafer (hereinafter, referred to as a “wafer”) to form a resist film, and a predetermined pattern is applied to the wafer after resist application.
- a resist pattern is formed as a mask for forming a predetermined pattern by a so-called photolithography technique in which the exposure pattern formed on the resist film of the wafer is developed after performing the above exposure processing.
- an exposure apparatus and a substrate processing system having a configuration in which a plurality of modules for performing steps such as resist coating, development, and baking before and after the exposure apparatus are integrated into a single unit are connected, thereby saving space. It is known to improve the throughput and the like (for example, Japanese Patent Application Laid-Open No. 2000-34041).
- a transport mechanism for moving the substrate between the modules is provided.
- Modules and the processing order are diverse, and efficient control of the transport mechanism that moves substrates between these modules is an important factor in determining the performance of a substrate processing system.
- current substrate position information in which module the substrate is located
- the position to be transferred to the target was determined each time based on the transfer recipe (information consisting of a combination of modules and the order of transfer between modules).
- the present invention has been made in view of such circumstances, and it is possible to suppress a disturbance in a transfer time when continuously executing various transfer recipes, and to realize a substrate processing system capable of realizing a stable substrate transfer process. Provide a control method aimed to.
- Another object of the present invention is to provide a substrate processing system capable of realizing an improvement in throughput by shortening the processing time in a continuous processing of a plurality of lots of various transfer recipes, and a control method thereof.
- Another object of the present invention is to provide a substrate processing system capable of realizing various transfer controls by feedforward control in a substrate transfer process, and a control method thereof.
- Still another object of the present invention is to provide a substrate processing system capable of improving operability in substrate transfer control and a control method thereof.
- Still another object of the present invention is to provide a control program capable of realizing the above control and a storage medium storing such a program.
- a substrate processing system including: a plurality of modules into which a substrate is loaded and unloaded; and a substrate moving mechanism configured to move the substrate between the modules.
- a transfer control table for storing a transfer schedule indicating a relationship between the transfer timing of the substrate and the module for loading and unloading the substrate, and the transfer control of the transfer schedule of the plurality of substrates in units of a unit.
- Control means including a function of generating on a table and a function of controlling the substrate moving mechanism based on the transfer schedule read from the transfer control table;
- a substrate processing system comprising:
- a substrate processing system including: a plurality of modules into which a substrate is loaded and unloaded; and a substrate moving mechanism configured to move the substrate between the modules.
- a transfer control table in which a transfer schedule indicating the relationship between the transfer timing of the substrate and the module in which the substrate is loaded and unloaded is stored; and a transfer control table storing the transfer schedule of the plurality of substrates in units of a unit.
- the start timing of the transfer schedule of the subsequent lot is set before the end timing of the preceding lot as long as the function generated above and the transfer schedule of each of the plurality of lots do not interfere with each other.
- Control means including: a function of setting the transfer schedule and a function of controlling the substrate moving mechanism based on the transfer schedule read from the transfer control table.
- a substrate processing system comprising:
- a substrate processing system including: a plurality of modules into which a substrate is loaded and unloaded; and a substrate moving mechanism configured to move the substrate between the modules.
- a transfer control table including a time axis on which a transfer timing at which the transfer operation of the substrate is performed at a predetermined cycle is set, and a transfer flow axis on which the modules for loading and unloading the substrate are arranged;
- control table On the transfer control table, by setting identification information of each of the substrates entering and exiting the module for a cell specified by specifying the specific transfer timing and the module, a plurality of the The function of generating the transfer schedule of the substrate and the contour of the figure formed by the cell group included in the transfer schedule of each of the plurality of lots set on the transfer control table do not interfere with each other. A function of moving the entire cell group included in the transfer schedule of the subsequent lot to the front in the time axis direction, and reading the cell read from the transfer control table for each transfer timing. Control means including a function of controlling the substrate moving mechanism based on a transfer schedule; A substrate processing system comprising:
- a resist coating module for applying a resist to a semiconductor substrate
- a developing module for developing a resist applied to the semiconductor substrate
- a hydrophobizing treatment for the semiconductor substrate.
- a processing module that performs any of processing, cooling processing, and holding processing, and a substrate moving mechanism that moves the semiconductor substrate between the modules.
- a transport control table including a time axis on which a transport timing in which the transport operation of the semiconductor substrate is performed at a predetermined cycle is set, and a transport flow axis on which the modules for loading and unloading the semiconductor substrate are arranged;
- the identification information of each of the semiconductor substrates entering and exiting the module is set for a cell specified by designating the specific transfer timing and the module, whereby a plurality of units in lot units are set.
- Control means including a function of controlling the substrate moving mechanism based on a schedule;
- a substrate processing system comprising:
- a method for controlling a substrate processing system including: a plurality of modules into which a substrate is loaded and unloaded; and a substrate moving mechanism configured to move the substrate between the modules.
- a method for controlling a substrate processing system including: a plurality of modules into which a substrate is loaded and unloaded; and a substrate moving mechanism configured to move the substrate between the modules.
- the start timing of the transfer schedule of the subsequent lot is set to the end of the preceding lot. Moving it forward,
- a method for controlling a substrate processing system including: a plurality of modules into which a substrate is loaded and unloaded; and a substrate moving mechanism configured to move the substrate between the modules.
- the transfer schedule of a plurality of the substrates in a lot unit is generated by setting the identification information of each of the substrates entering and exiting the module with respect to the cell specified by the transmission and reception timing and the module.
- a resist coating module for applying a resist to a semiconductor substrate, a developing module for developing a resist applied to the semiconductor substrate, a hydrophobizing treatment and a heating treatment for the semiconductor substrate.
- a processing module that performs any one of processing, cooling processing, and holding processing; and a substrate moving mechanism that moves the semiconductor substrate between the modules.
- a transfer control table including a time axis for setting a transfer timing in which the transfer operation of the semiconductor substrate is performed in a predetermined cycle and a transfer flow axis in which the modules for loading and unloading the semiconductor substrate are arranged,
- a substrate processing system including: a plurality of modules into which a substrate is loaded and unloaded; a substrate moving mechanism that moves the substrate between the modules; and a computer that controls the module and the substrate moving mechanism. Control program,
- a substrate processing apparatus includes: a plurality of modules into which a substrate is loaded and unloaded; a substrate moving mechanism that moves the substrate between the modules; and a computer that controls the module and the substrate moving mechanism.
- a transfer control table storing a transfer schedule indicating a relationship between the transfer timing of the substrate and the module into which the substrate is loaded and unloaded. And a step of generating the transfer schedule of the plurality of substrates in lot units.
- the start of the transfer schedule of the subsequent lot is earlier than the end timing of the preceding lot.
- a substrate processing method includes: a plurality of modules into which a substrate is loaded and unloaded; a substrate moving mechanism that moves the substrate between the modules; and a computer that controls the module and the substrate moving mechanism.
- a computer-readable storage medium storing a system control program
- a substrate processing includes: a plurality of modules into which a substrate is loaded and unloaded; a substrate moving mechanism that moves the substrate between the modules; and a computer that controls the module and the substrate moving mechanism.
- the start timing of the transfer schedule of the subsequent lot is set longer than the end timing of the preceding lot.
- a storage medium storing a control program for executing the program is provided.
- the relationship between the substrate transfer timing and the passing module is set on the transfer control table for all the wafers in the lot, and this setting is sequentially read out at predetermined intervals in the time axis direction and the substrate is read out. Since the transfer of the substrate is performed by controlling the moving mechanism, the occurrence of disturbance in the transfer time can be suppressed as compared with a case where the transfer position of the substrate is determined each time the transfer is performed. In addition, when processing lots of complicated transfer recipes continuously, the timing of starting transfer of each lot is optimized without causing problems such as overtaking of wafers between lots, and processing of preceding lots is performed. It is possible to start the transfer of the subsequent lot before the completion of the process, and the throughput is improved by shortening the processing time by the parallel transfer processing of a plurality of ports.
- the system administrator can grasp the operating status of each module and transport mechanism, improving operability.
- FIG. 1 is a plan view showing the overall configuration of a semiconductor wafer resist coating and developing system to which a substrate processing system according to an embodiment of the present invention is applied.
- FIG. 2 is a front view showing the resist coating and developing system shown in FIG.
- FIG. 3 is a rear view showing the resist coating and developing system shown in FIG.
- FIG. 4 is a conceptual diagram showing an example of the configuration of a control system of the resist coating and developing system of FIG.
- FIG. 5 is a conceptual diagram for explaining a transfer control table used in the substrate processing system according to one embodiment of the present invention.
- FIG. 6 is a flowchart showing a control flow of a transfer operation of the main wafer transfer mechanism 22 in the resist coating and developing processing system of FIG.
- FIG. 7 is a flowchart showing a control flow of a transfer operation of the wafer transfer mechanism 24 in the resist coating and developing processing system of FIG.
- FIG. 8 is a diagram showing an example of a transport control table used for the control of FIGS.
- FIG. 9A is a diagram showing a transport flow of an embodiment applied to a case where a plurality of different lots are continuously processed.
- 9B and 9C are conceptual diagrams showing a transfer schedule for performing the transfer flow of FIG. 9A.
- FIG. 10 is a flow chart for realizing the transfer schedules of FIGS. 9B and 9C.
- FIG. 11A is a diagram showing a transfer flow that embodies the transfer flow of FIG. 9A.
- Figures 11B and 11C are based on the transport flow of Figure 11A and Figures 9B and 9C The figure which shows an example of the conveyance table which actualized the conceptual diagram of FIG.
- FIG. 12A is a diagram showing a transfer flow that embodies the transfer flow of FIG. 9A.
- FIGS. 12B and 12C are diagrams showing another example of the transport table in which the conceptual diagrams of FIGS. 9B and 9C are realized based on the transport flow of FIG. 12A.
- FIG. 13A is a diagram showing a transfer flow that embodies the transfer flow of FIG. 9A.
- FIG. 13B is a view showing still another example of the transfer table in which the conceptual diagrams of FIGS. 9B and 9C are realized based on the transfer flow of FIG. 13A.
- FIG. 1 is a schematic plan view showing a resist coating image processing system as an embodiment of the substrate processing system of the present invention
- FIG. 2 is a front view thereof
- FIG. 3 is a rear view thereof. In these figures, directions perpendicular to each other in the plane
- FIG. 4 is a conceptual diagram illustrating an example of a configuration of a control system of the resist coating and developing processing system according to the present embodiment.
- FIG. 5 is a conceptual diagram illustrating an example of a transport control table used in the present embodiment.
- the resist coating and developing system 1 includes a cassette station 10 as a transport station, a processing station 11 having a plurality of modules, and an exposure apparatus (not shown) provided adjacent to the processing station 11. And an interface face 12 for transferring the wafer W between them.
- the cassette station 10 is used to load a plurality of wafers W as objects to be processed, for example, in units of 25 wafers, into the wafer cassette CR, or to load the wafers W from another system into the system or from this system to another system. Or between the wafer cassette CR and the processing station 11 This is for transporting wafers.
- the cassette station 10 As shown in FIG. 1, a plurality of (four in the figure) positioning projections 2 are placed on the mounting table 20 on which the wafer cassette CR is mounted along the X direction in the figure.
- the wafer cassette CR can be placed in a line at the position of the positioning protrusion 20a with the wafer entrance and exit facing the processing station 11 side.
- the wafers W are arranged in the vertical direction (Z direction).
- the cassette station 10 has a wafer transfer mechanism 21 located between the mounting table 20 and the processing station 11.
- the wafer transfer mechanism 21 is capable of moving in the cassette arrangement direction (X direction) and the wafer arrangement direction (Z direction) of the wafers W therein, and is capable of moving back and forth in the Y direction.
- the wafer transfer arm 21a can selectively access any of the wafer cassettes CR. Further, the wafer transfer arm 21a is configured to be rotatable in the zero direction, and is also provided to an extension unit (EXT) belonging to a third module group G3 on the processing station 11 side described later. It is accessible.
- EXT extension unit
- the processing station 11 includes a plurality of modules for performing a series of steps for performing coating and development on the wafer W, and these modules are arranged at predetermined positions in multiple stages. W is processed one by one. As shown in FIG. 1, the processing station 11 has a transfer path 22a in the center, in which a main wafer transfer mechanism 22 is provided, and all the modules around the transfer path 22a. Is arranged. These multiple modules are divided into multiple module groups, and each module group has multiple modules arranged in multiple stages along the vertical direction.
- the main wafer transfer mechanism 22 is located inside the cylindrical support 49.
- a wafer transfer device 46 is provided to be able to move up and down in the vertical direction (Z direction).
- the cylindrical support 49 is rotatable by the rotational driving force of a motor (not shown), and accordingly, the wafer transfer device 46 is also integrally rotatable.
- the wafer transfer device 46 includes a plurality of holding members 48 movable in the front-rear direction of the transfer base 47, and the transfer of the wafer W between the modules is realized by these holding members 48.
- module group G 5 is adapted to be positioned as required.
- G 2 have first and second module group G are arranged in parallel to the system a positive side, the third module group G 3 is disposed adjacent to the cassette stationing down 1 0, the fourth Module group G 4 is arranged adjacent to the interface section 12. Further, the module group G 5 of the fifth is adapted to be disposed on the back surface.
- a resist coating module for applying the resist to the wafer W by placing the wafer W on a spin chuck (not shown) in the cup CP and similarly in the cup CP
- a development module that develops the resist pattern is stacked in two layers from the bottom.
- the second module group G2 has two spinner-type modules, a resist coating module (COT) and a developing module (DEV), which are stacked in two stages from the bottom.
- the open type module are multi-tiered to perform a predetermined process placed on table SP mounting the wafer W.
- an adhesion unit AD;
- Two extension units EXT) for performing the cooling process
- a cooling unit COL
- four hot plate units for performing the heating process on the wafer W before and after the exposure process and after the current image process.
- HP are stacked in eight steps from the bottom.
- a cooling unit (COL) may be provided, and the cooling unit (COL) may have an alignment function.
- Fourth module group G 4 is also open type of module is found multi-tiered.
- a cooling unit (COL), an extension cleaning unit (EXTCOL) that is a wafer loading / unloading unit with a cooling plate, an extension unit (EXT), a cooling unit (C ⁇ L), and Four hot plate units (HP) are stacked in eight stages from the bottom.
- the interface section 12 has the same length in the depth direction (X direction) as the processing station 11, and as shown in FIGS. 1 and 2, the interface section 12 has A portable pickup cassette CR and a stationary buffer cassette BR are arranged in two stages at the front, a peripheral exposure device 23 is arranged at the rear, and a wafer transfer mechanism 24 is arranged at the center. It is arranged.
- the wafer transfer mechanism 24 has a wafer transfer arm 24a.
- the wafer transfer arm 24a moves in the X, Y, and Z directions to move the two cassettes CR and BR and the peripheral exposure light.
- Device 2 3 is accessible You.
- the wafer transfer arm 24 a is rotatable in the zero direction, and is an extension unit (EXT) belonging to the fourth module group G 4 of the processing station 11, or an adjacent exposure apparatus.
- the wafer transfer table (not shown) on the side is also accessible.
- the resist coating and developing system of the present embodiment includes a controller 50 for controlling the entire system, a program 60 for operating the controller 50, and a transport control described later.
- a control memory 51 for storing control information such as a table 70 is provided.
- the controller 5 0 is constituted by a computer system, via the input-output Intafue Ichisu 5 2, the above G, is connected to a plurality of Interview two Tsu City of ⁇ G 4 (module), the program 6 0, It controls the various processes described above in each unit.
- the wafer transfer mechanism 21, the main wafer transfer mechanism 22, and the wafer transfer mechanism 24 are also connected to the controller 50 via the input / output interface 52, and are controlled by the controller 50 by the program 60. Performs a wafer transfer operation as described below.
- An operation panel 53 having a user interface such as a display 53 a and a keyboard 53 b is connected to the controller 50, and a system administrator gives an external command to operate the controller 50. It is possible to control and input information for setting and updating control information.
- the transfer control table 70 includes a transfer flow axis on which module information 73 for specifying a plurality of units used to realize a series of processing (hereinafter, referred to as a processing recipe) for the wafer W is arranged. 7 one and individual It comprises a secondary table having a transfer timing axis 72 indicating a transfer cycle 74 for moving the wafer W between the units in a predetermined order.
- Each module information 73 of the transport flow axis 71 includes a module ID 73 a such as a module name that specifies each module, and information such as default operating conditions of the module in the processing recipe. Stores the process parameter 73 b in which is set.
- each transport cycle 74 on the transport timing axis 72 the transport cycle number 74a indicating the execution order, the cycle time 7b indicating the execution cycle of each transport cycle, the individual transport related to the transport process Information such as a running flag 74c indicating the completion of the operation of the mechanism in the transport cycle is stored.
- each of the plurality of transport cycles arranged on the transport timing axis 72 and the cell (the item separated by vertical and horizontal vertical lines) at the intersection of the module information 73 on the transport flow axis 71 is set to the transport cycle.
- wafer identification information 75 (transfer JOB) relating to wafer W to be carried into the unit is set.
- Each wafer identification information 75 includes a wafer ID 75 a such as a wafer number in each lot, completion of loading of the wafer into the module (indicating whether or not there is a wafer currently in the module, and ON: Yes, OFF: No) Transfer completion flag 7 5 b that indicates the process parameters used when setting parameters specific to the wafer in the module in place of the default process parameters described above.
- Information such as c is stored.
- Information such as the module information 73, the transfer cycle 74, and the wafer identification information 75 in the transfer control table 70 are displayed on the display 53a as needed, and edited by the operator using the keyboard 53b, etc. It is possible.
- the wafers W before processing are taken out of the wafer cassette CR one by one by the wafer transfer mechanism 21 and carried into the extension unit (EXT) at the processing station 11 I do.
- the wafer W placed here is unloaded by the main wafer transfer mechanism 22 and is loaded into an adhesion unit (AD) to perform an adhering process.
- the wafer W is unloaded by the main wafer transfer mechanism 22 and transferred to a cooling unit (COL) where it is cooled.
- AD adhesion unit
- COL cooling unit
- the wafer W is transferred to a resist coating unit (COT) for resist coating, and pre-baked by a hot plate unit (HP), and then passed through an extension cooling unit (EXTC OL).
- COT resist coating unit
- HP hot plate unit
- EXTC OL extension cooling unit
- the wafer is conveyed to an interface unit (EIS) 12, and from there, is conveyed to an adjacent exposure device (not shown) through a wafer exposure mechanism (WEE) 23 by a wafer conveyance mechanism 24.
- EIS interface unit
- WEE wafer exposure mechanism
- the wafer W subjected to the exposure processing by the exposure apparatus is transferred to the processing station 11 by the wafer transfer mechanism 24 via the interface unit (EIS) 12 and the extension unit (EXT).
- the wafer W is transferred to the hot plate unit (HP) by the main wafer transfer mechanism 22 to perform the boss exposure treatment, and then transferred to the developing unit (DEV) for developing processing.
- post-bake processing is performed in the hot plate unit (HP), cooled in the cooling unit (COL), and transported to the cassette station 10 via the extension unit (EXT).
- the wafer W subjected to the predetermined processing as described above is stored in the wafer cassette CR by the wafer transfer mechanism 21.
- FIG. 6 shows an example of a control operation of the main transport mechanism 22 and the wafer transport mechanism 24 in the transport operation of the wafer W in such a series of processing. This will be described with reference to FIG.
- FIG. 6 is a flowchart showing the control flow of the transfer operation of the main wafer transfer mechanism 22.
- FIG. 7 is a flowchart showing the control flow of the transfer operation of the wafer transfer mechanism 24.
- FIG. FIG. 8 is a diagram showing an example of a transport control table used for the control of FIGS.
- the module that takes out the wafer W by the transfer mechanism is the “From module”, and the module that inputs the wafer W held by the transfer mechanism is the “To module”. It is explained by the expression. Since the wafer transfer mechanism 21 is a simple operation of taking out the wafer W from the cassette CR and storing the wafer W after the processing is completed, the description is omitted.
- the controller 50 determines the processing recipe and the port of the lot specified in advance. Based on the number of wafers W in the slot, as shown in FIG. 8, the individual wafers W must be transferred to which module on the transfer control table 70 at which transfer cycle timing.
- the transport schedule SX that manages information such as information is developed and generated (step 102). That is, in the above example, each of Ml, M2,...
- transport flow axis 7 1 includes CR, EXT, AD, COL, COT, HP, EXTCOL, EIS, WE E, EIS Modules related to pre-processing of the exposure equipment and individual processing after exposure up to EXT, HP, DEV, COL, EXT, and CR.
- buffers that only allow wafer W to pass The transfer cycle 74 is expanded on the transfer timing axis 72, and the wafer identification information 75 (cell) in this two-dimensional space is loaded in each transfer cycle. Of cells (areas of figures enclosed by double lines in Fig. 8) that specify the module on which each wafer W is to be located. Send schedule SX to create.
- the previous lot and the next lot are defined in a transfer schedule pattern (cell group) such that the processing of the first wafer W of the next lot 1 is started after the last wafer W of the previous lot is processed. Is generated, and the start timing of each lot is optimized as described later.
- the transfer schedule SX automatically created as described above is visualized and displayed on the display 53 a of the operation panel 53 as necessary, and the system administrator can lock the entire wafer 1.
- the transport status can be visually grasped, and the transport schedule can be edited using the key board 53b.
- step 104 the next wafer to be taken out from each module in the order of transfer.
- Search for W step 104.
- the wafer identification information 75 belonging to the current transfer cycle the Flom module whose transfer completion flag 75b is ON (the module whose processing has been completed in the previous transfer cycle and the wafer can be discharged) ) Is retrieved along the transport flow axis 71, and the wafer W is taken out of the From module based on the search result, and the transport completion flag 75b of the taken-out module is turned off (step 105).
- step 109 it is checked whether or not any unexecuted transfer processing remains in the transfer cycle (step 109), and if so, the steps from step 104 onward are repeated.
- the execution flag 74c of the own wafer transfer mechanism is set to OFF, and the wafer transfer processing of all the wafer transfer mechanisms in the transfer cycle is completed (the execution flag 74 of the transfer cycle 74). Wait for all c to be ⁇ FF) (Step 110), then terminate the currently executed transfer cycle (Step 111), and check for any unexecuted transfer cycles (Step 111). 2) If there is an unexecuted transfer cycle, change the next transfer cycle to a running state (step 1 13), and repeat step 104 and subsequent steps. If there is no unexecuted transfer cycle in step 112, the transfer control ends.
- steps 101 to 103 are common, but the wafer flow is Since it is a one-way transfer operation from WEE to payout, no wafer exchange processing occurs, and the operation is the operation in which steps 106 to 108 in FIG. 6 described above are omitted. That is, in the current transfer cycle (row direction) of the transfer control table 70, a search is made for a wafer W to be taken out next from each module in the transfer order (step 1 2 1). Take out the wafer W from the module and set the transfer completion flag 7 5 b of the taken out module to OF F Then, the wafer is loaded into the To module (Step 122).
- Step 1 2 3 it is checked whether or not the unexecuted transfer J ⁇ ⁇ B remains in the relevant transfer cycle. If there is, repeat steps 1 2 1 and subsequent steps.
- the running flag 74c of the automatic transfer mechanism is turned off, and the wafer transfer processing of all the wafer transfer mechanisms in the transfer cycle is completed (transfer cycle 74). (Steps 1 2 4) until the in-progress flags 7 4 c are all turned OFF.
- Step 1 26 Check if there is any (Step 1 26), and if there is an unexecuted transfer cycle, change the next transfer cycle to the running state (Step 1 27), and repeat Step 1 2 1 and after . If there is no unexecuted transfer cycle in step 126, the transfer control ends.
- a complicated transfer recipe (Transfer flow)
- the transfer timing of individual wafers W can be determined for all wafers in the lot at the start of the lot, so that there is no problem such as disturbance in the transfer time, and stable in the resist coating and developing processing system. Wafer transfer processing can be realized.
- feed-forward control for appropriately changing the transfer schedule set in the transfer control table 70 is also possible.
- the transfer schedule can be changed.
- step 1 The transfer schedule creation process of 02 is as shown in FIG. 10 as an example. That is, first, a wafer processing recipe (transfer recipe) is specified (step 102 a), and a process (step 102 b) for automatically generating a transfer schedule for the lot on the transfer control table 70 is performed. Repeat for all lots (Step 102c).
- the creation of the transfer schedule on the transfer control table 70 described with reference to FIG. 8 is sequentially performed for the transfer flow A and the transfer flow B.
- the previous lot and the next lot are set so that the processing of the first wafer W of the next lot is started after the processing of the last wafer W of the previous lot.
- a transfer schedule pattern is generated.
- the subsequent transport schedule SB is configured by the transport schedule SB (cell group of wafer identification information ⁇ 5).
- the transfer control table 70 so that the outline of the figure that does not interfere with the transfer schedule SA (the outline of the figure composed of the cell group of the wafer identification information 75) in the time axis direction.
- the entire cell group of the transfer schedule SB is moved (step 102d).
- the start timing of the subsequent transfer schedule SB is advanced, and the overall processing time is shorter than the simple sum of the individual processing times for starting the processing of the B lot after the processing of the A lot is completed.
- FIGS. 11A to 11C illustrate this more specifically.
- Fig. 11A A lot (transfer flow A: continuous processing of modules M1 to M8) consisting of a plurality of wafers W of A1 to A5 and B1 to B5
- transfer control table 70 for continuous processing of the B lot transfer flow B: processing of modules M1 to M4 and M7, M8) consisting of multiple wafers W
- the A lot and B lot are serially
- the total processing time is the total processing time of the sum of the A lot and the B lot, as shown in Fig. 11B.
- the transfer schedule SB of the B-lot does not interfere with the transfer schedule SA of the A-port preceding in the time axis direction.
- Wafer B 1 of B lot the transfer process starts in parallel with the preceding A lot in the same transfer cycle from transfer cycle 7 before transfer cycle 11 where A lot ends. Is done.
- the start timing of the subsequent B lot is advanced and the total processing time of the A lot and the B lot is greatly reduced without causing a problem such as the overtaking of the wafer W between the lots. And the throughput is improved.
- Fig. 13B shows an example in which this embodiment is applied to a transport flow example that uses the same type of module and uses differently in the preceding A lot and the subsequent B lot shown in Fig. 13A. Show. In other words, both use the modules Ml to M8 in common, but in the transport flow A, in a Shirepi including a specific process in which the required time is longer than the cycle time, a plurality of modules M each having the same function are used. 4 and M5, the wafer W is sorted to these M4 and M5, and the specific processing is performed in parallel. In the transfer flow B, the required time is longer than the cycle time. A single flow is performed in which the processing is divided into two modules M4 and M5 having the same function and processed serially. In the flow of Fig. 13A, as shown in Fig. 13B, the transfer start timing of the subsequent port B is shifted to the left (in this case, shifted from transfer cycle 13 to transfer cycle 7). By setting, you can expect an improvement in throughput.
- the substrate is not limited to a semiconductor wafer, and can be widely applied to a general substrate transfer process such as a photomask substrate and a liquid crystal display substrate.
- various transport controls can be realized by feed-forward control in the substrate transport process.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/551,225 US7729798B2 (en) | 2003-04-02 | 2004-03-26 | Substrate processing system, and method of control therefor, control program, and storage medium |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003099350A JP4233908B2 (ja) | 2003-04-02 | 2003-04-02 | 基板処理システム |
JP2003-099350 | 2003-04-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004090972A1 true WO2004090972A1 (ja) | 2004-10-21 |
Family
ID=33156695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/004383 WO2004090972A1 (ja) | 2003-04-02 | 2004-03-26 | 基板処理システムおよびその制御方法、制御プログラム、記憶媒体 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7729798B2 (ja) |
JP (1) | JP4233908B2 (ja) |
KR (1) | KR100994856B1 (ja) |
CN (1) | CN100539064C (ja) |
WO (1) | WO2004090972A1 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8078311B2 (en) * | 2004-12-06 | 2011-12-13 | Tokyo Electron Limited | Substrate processing apparatus and substrate transfer method adopted in substrate processing apparatus |
JP2008034746A (ja) * | 2006-07-31 | 2008-02-14 | Tokyo Electron Ltd | 塗布、現像装置、その方法及び記憶媒体 |
KR100887011B1 (ko) * | 2007-06-25 | 2009-03-04 | 주식회사 동부하이텍 | 반도체 제조 공정에서의 수율 분석 시스템 및 방법 |
JP5006122B2 (ja) | 2007-06-29 | 2012-08-22 | 株式会社Sokudo | 基板処理装置 |
KR101012249B1 (ko) * | 2007-07-10 | 2011-02-08 | 다이닛뽕스크린 세이조오 가부시키가이샤 | 기판처리장치의 스케줄작성방법 및 그 프로그램 |
JP5022302B2 (ja) * | 2007-07-10 | 2012-09-12 | 大日本スクリーン製造株式会社 | 基板処理装置のスケジュール作成方法及びそのプログラム |
JP5318403B2 (ja) | 2007-11-30 | 2013-10-16 | 株式会社Sokudo | 基板処理装置 |
JP5128918B2 (ja) | 2007-11-30 | 2013-01-23 | 株式会社Sokudo | 基板処理装置 |
JP4886669B2 (ja) * | 2007-12-12 | 2012-02-29 | 大日本スクリーン製造株式会社 | 基板処理装置 |
JP5179170B2 (ja) * | 2007-12-28 | 2013-04-10 | 株式会社Sokudo | 基板処理装置 |
JP5001828B2 (ja) | 2007-12-28 | 2012-08-15 | 株式会社Sokudo | 基板処理装置 |
JP5294681B2 (ja) * | 2008-04-28 | 2013-09-18 | 東京エレクトロン株式会社 | 基板処理装置及びその基板搬送方法 |
JP4640469B2 (ja) | 2008-08-11 | 2011-03-02 | 東京エレクトロン株式会社 | 塗布、現像装置、その方法及び記憶媒体 |
JP2010045190A (ja) * | 2008-08-12 | 2010-02-25 | Tokyo Electron Ltd | 加熱システム、塗布、現像装置及び塗布、現像方法並びに記憶媒体 |
DE102009013353B3 (de) * | 2009-03-16 | 2010-10-07 | Siemens Aktiengesellschaft | Verfahren zur Bestimmung von Rüstungen für konstante Tische von Bestückautomaten |
US8655472B2 (en) * | 2010-01-12 | 2014-02-18 | Ebara Corporation | Scheduler, substrate processing apparatus, and method of transferring substrates in substrate processing apparatus |
JP2014067910A (ja) * | 2012-09-26 | 2014-04-17 | Tokyo Electron Ltd | 塗布膜形成装置、塗布膜形成方法、塗布、現像装置、塗布、現像方法及び記憶媒体 |
JP6003859B2 (ja) | 2013-09-18 | 2016-10-05 | 東京エレクトロン株式会社 | 塗布、現像装置、塗布、現像方法及び記憶媒体 |
WO2017026928A1 (en) | 2015-08-07 | 2017-02-16 | Telefonaktiebolaget Lm Ericsson (Publ) | Differentiated positioning |
US10698392B2 (en) * | 2018-06-22 | 2020-06-30 | Applied Materials, Inc. | Using graphics processing unit for substrate routing and throughput modeling |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08153765A (ja) * | 1994-04-08 | 1996-06-11 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JPH09181143A (ja) * | 1995-12-26 | 1997-07-11 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JPH1145926A (ja) * | 1997-07-25 | 1999-02-16 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JP2001345241A (ja) * | 2000-05-31 | 2001-12-14 | Tokyo Electron Ltd | 基板処理システム及び基板処理方法 |
JP2002506285A (ja) * | 1998-03-03 | 2002-02-26 | アプライド マテリアルズ インコーポレイテッド | マルチチャンバ半導体ウェハ加工システムでウェハを順序付けるための方法および装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100198477B1 (ko) | 1994-04-08 | 1999-06-15 | 이시다 아키라 | 기판처리장치 및 방법 |
JP2001351848A (ja) * | 2000-06-07 | 2001-12-21 | Tokyo Electron Ltd | 基板処理システム及び基板処理方法 |
US6535784B2 (en) * | 2001-04-26 | 2003-03-18 | Tokyo Electron, Ltd. | System and method for scheduling the movement of wafers in a wafer-processing tool |
-
2003
- 2003-04-02 JP JP2003099350A patent/JP4233908B2/ja not_active Expired - Lifetime
-
2004
- 2004-03-26 KR KR1020057018481A patent/KR100994856B1/ko active IP Right Grant
- 2004-03-26 US US10/551,225 patent/US7729798B2/en active Active
- 2004-03-26 CN CNB2004800153980A patent/CN100539064C/zh not_active Expired - Lifetime
- 2004-03-26 WO PCT/JP2004/004383 patent/WO2004090972A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08153765A (ja) * | 1994-04-08 | 1996-06-11 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JPH09181143A (ja) * | 1995-12-26 | 1997-07-11 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JPH1145926A (ja) * | 1997-07-25 | 1999-02-16 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JP2002506285A (ja) * | 1998-03-03 | 2002-02-26 | アプライド マテリアルズ インコーポレイテッド | マルチチャンバ半導体ウェハ加工システムでウェハを順序付けるための方法および装置 |
JP2001345241A (ja) * | 2000-05-31 | 2001-12-14 | Tokyo Electron Ltd | 基板処理システム及び基板処理方法 |
Also Published As
Publication number | Publication date |
---|---|
US7729798B2 (en) | 2010-06-01 |
JP4233908B2 (ja) | 2009-03-04 |
JP2004311511A (ja) | 2004-11-04 |
KR20060002894A (ko) | 2006-01-09 |
US20060228195A1 (en) | 2006-10-12 |
CN1799135A (zh) | 2006-07-05 |
CN100539064C (zh) | 2009-09-09 |
KR100994856B1 (ko) | 2010-11-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2004090972A1 (ja) | 基板処理システムおよびその制御方法、制御プログラム、記憶媒体 | |
JP4087328B2 (ja) | 塗布、現像装置及び塗布、現像装置の運転方法 | |
KR100300614B1 (ko) | 레지스트도포/현상장치및피처리체의처리장치 | |
US8702370B2 (en) | Substrate transfer method for performing processes including photolithography sequence | |
TWI416593B (zh) | 塗布顯影裝置及塗布顯影裝置之控制方法與記憶媒體 | |
US7880859B2 (en) | Substrate processing system and substrate processing method | |
WO2004049408A1 (ja) | 基板処理システム、塗布現像装置及び基板処理装置 | |
JP5223778B2 (ja) | 基板処理装置、基板処理方法及び記憶媒体 | |
JP2009021275A (ja) | 基板処理装置 | |
US8046095B2 (en) | Substrate processing system and substrate transfer method | |
WO2005101485A1 (ja) | 基板処理装置及び基板処理方法 | |
JP4957426B2 (ja) | 塗布、現像装置及び塗布、現像装置の運転方法並びに記憶媒体 | |
JP2007266050A (ja) | 基板処理装置のスケジュール実行方法及びそのプログラム | |
JP4018965B2 (ja) | 基板処理装置 | |
JP2982038B2 (ja) | 被処理体の処理のスケジューリング方法及びその装置 | |
US7191033B2 (en) | Substrate processing apparatus and substrate processing method | |
JP2019021934A (ja) | 基板搬送方法 | |
JP4496073B2 (ja) | 基板処理装置及び基板処理方法 | |
JP5348290B2 (ja) | 基板処理装置、基板処理方法及び記憶媒体 | |
JP4640469B2 (ja) | 塗布、現像装置、その方法及び記憶媒体 | |
JP4606159B2 (ja) | 基板処理装置、基板処理方法、コンピュータプログラム及び記憶媒体 | |
JP2982039B2 (ja) | 処理方法及びその処理装置 | |
JP2022029637A (ja) | 基板処理装置及び搬送スケジュール作成方法 | |
JP2004319768A (ja) | 基板処理装置 | |
JP2003031453A (ja) | 基板処理装置のスケジュール作成方法及びそのプログラム |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2006228195 Country of ref document: US Ref document number: 10551225 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020057018481 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 20048153980 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 1020057018481 Country of ref document: KR |
|
DPEN | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed from 20040101) | ||
122 | Ep: pct application non-entry in european phase | ||
WWP | Wipo information: published in national office |
Ref document number: 10551225 Country of ref document: US |