WO2005101485A1 - 基板処理装置及び基板処理方法 - Google Patents
基板処理装置及び基板処理方法 Download PDFInfo
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- WO2005101485A1 WO2005101485A1 PCT/JP2005/001484 JP2005001484W WO2005101485A1 WO 2005101485 A1 WO2005101485 A1 WO 2005101485A1 JP 2005001484 W JP2005001484 W JP 2005001484W WO 2005101485 A1 WO2005101485 A1 WO 2005101485A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67276—Production flow monitoring, e.g. for increasing throughput
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM]
- G05B19/41815—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS], computer integrated manufacturing [CIM] characterised by the cooperation between machine tools, manipulators and conveyor or other workpiece supply system, workcell
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67742—Mechanical parts of transfer devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/31—From computer integrated manufacturing till monitoring
- G05B2219/31002—Computer controlled agv conveys workpieces between buffer and cell
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/45—Nc applications
- G05B2219/45031—Manufacturing semiconductor wafers
Definitions
- the present invention relates to a substrate processing apparatus and a substrate processing method for applying a resist to a semiconductor wafer or a glass substrate (LCD substrate) for a liquid crystal display and performing a development process after exposure.
- Japanese Patent Application Laid-Open No. 2002-217264 discloses a system in which an exposure apparatus is combined with a coating and developing apparatus for performing a photolithography process on a semiconductor device.
- Figure 14 shows an overview of the conventional system.
- the coating and developing apparatus 1 includes a carrier mounting section 1A, a processing block 1B, and an interface section 1C.
- the exposure device 1D is connected to the coating and developing device 1 via an interface 1C.
- a transfer arm 11 for transferring the wafer W to the processing block 1B is provided in the carrier mounting section 1A.
- Main transfer arms 12-1 and 12-2 are provided inside the processing block 1B.
- the main transfer arms 12-1 and 12-2 are provided with, for example, three arm holders that can move forward and backward, move up and down, and can rotate in the horizontal direction.
- a heating unit, a shelf unit 13 and a liquid processing unit 14 are arranged around each of the main transfer arms 12-1 and 12-2.
- the liquid processing unit 14 includes an antireflection film coating unit, a resist coating unit, and a developing unit.
- the shelf unit 13 is formed by stacking cooling units, which are high-precision temperature control units, in multiple stages.
- the shelf unit 13 includes, between the transfer arm 11 and the main transfer arm 12-1, between the main transfer arms 12-1 and 12-2, between the main transfer arm 12-2 and the interface section 1C.
- a transfer unit for transferring a substrate to and from a transfer arm (not shown) is provided.
- a path from the wafer C is unloaded to the exposure apparatus 1D until it is carried out by the carrier C is referred to as "outbound path", and the reverse path is referred to as "return path”.
- return path Various processes for forming a resist film are performed on the wafer W on the outward pass, and a process for developing the exposed resist film on the return pass is performed.
- the transfer route of the wafer W for performing the photolithography process Carrier C ⁇ Anti-reflective coating unit (liquid processing unit 14) ⁇ Cooling unit (shelf cutout 14) ⁇ Resist coating unit (liquid processing unit 14) ⁇ Heating unit ⁇ Cooling unit ⁇ Interface block 1C ⁇ Exposure unit 1D ⁇ interface block 1C ⁇ heating unit ⁇ cooling unit ⁇ developing unit (liquid processing unit 14) ⁇ cooling unit ⁇ carrier C.
- the computer In order to carry out such a transfer of the wafer W, when a transfer recipe defining the order in which the wafer W is transferred is input, the computer creates a transfer schedule based on the transfer recipe. .
- each unit or stage on which the wafer W is placed is referred to as a “module”.
- the “transfer recipe” refers to an assignment table in which the transfer order of the wafer w is assigned to each module.
- the “transport schedule” is, for example, a time table in which transport cycles (phases) are arranged in time series as shown in FIG. ⁇ Phase '' defines which wafer W is located in which module in order to transfer wafer W between modules along the transport path including the outward path and the return path from upstream to downstream.
- the computer refers to this phase and is described in the phase!
- the transfer arm 11, the main transfer arm 12-1, the 1-22, and the interface so that the positional relationship between the wafer W and the module is established.
- a transfer arm (not shown) in block 1C is driven, one phase is executed, and then the next phase is executed.Thus, the phases are sequentially executed, so that the wafer W sequentially moves along the above-described transfer path. It will be.
- One phase includes transfer by the first main transfer arm 12-1 and transfer by the second main transfer arm 12-2.
- the main transfer arms 12-1 and 12-2 return to their original initial positions when the transfer of the wafer W to the modules within their area of responsibility in one phase is completed, and the next phase is started. Wait until.
- the throughput of the exposure apparatus 1D has tended to improve, and accordingly, the coating and developing apparatus has been increasing.
- the coating and developing apparatus has been increasing.
- the throughput of the conventional coating and developing apparatus 1 is not sufficiently high, the improvement of the throughput of the entire system is hindered by the coating and developing apparatus 1.
- An object of the present invention is to provide a substrate processing apparatus and a substrate processing method that can improve throughput.
- the transfer order is specified! A group of modules for processing a plurality of substrates in parallel, and a plurality of substrate transport mechanisms for transporting the substrates to each module of the module group, respectively.
- One transfer cycle is executed by sharing the operation of transferring the board to the next module, and after executing the one transfer cycle, the process proceeds to the next transfer cycle, and the next transfer cycle is performed. Executing the module, the module order is small in the module group, the module force is large in the order, and the substrate is sequentially conveyed toward the module.
- An order is assigned to each of a plurality of substrates according to a predetermined transfer recipe, a transfer cycle is specified by associating the assigned order of the substrates with each of the modules, and the data of the specified transfer cycle is arranged in chronological order to set a transfer schedule.
- the board transfer mechanism is written in the data of the transfer cycle, and controls the substrate transfer mechanism to transfer the substrate to a module corresponding to the board.
- the transfer control unit (45) for executing the transfer schedule and the transfer schedule stored in the transfer schedule storage unit, and one of the plurality of substrate transfer mechanisms takes charge of itself in one transfer cycle. After the transfer is completed, while the one transfer cycle is being executed by another substrate transfer mechanism, the first substrate transfer mechanism is moved, and the first module for transferring the substrate in the next transfer cycle is moved to the first module.
- the transfer control unit may be configured to, in the one transfer cycle, cause the one substrate transfer mechanism to sequentially transfer the substrates to a plurality of modules in the area covered by the one substrate transfer mechanism. Then, the substrate is sequentially transported to a plurality of modules in the coverage area, and the standby position control unit determines, during the one transport cycle, that the board to be transported first within the coverage area of the one substrate transport mechanism is to be transferred first.
- the one substrate transfer mechanism is moved to a module, the one substrate transfer mechanism is made to wait until the next transfer cycle starts, and the transfer control unit performs the first substrate transfer in the next transfer cycle.
- the mechanism sequentially transports the substrate again to a plurality of modules in its area of responsibility.
- another substrate transport mechanism is provided between a carrier accommodating a plurality of substrates and a delivery unit, and the one substrate transport mechanism is a module of the module group. It is provided between each module and the delivery unit.
- one substrate transfer mechanism is provided between the modules of the module group, and the other substrate transfer mechanism is also provided between the modules of the module group.
- the substrate transport mechanism may also take out the first substrate with one module force of the module group and receive the second substrate with the next module force of the module group. To the first substrate.
- the substrate transfer mechanism transfers the substrate force of the lot previously loaded into the modules in the transfer coverage area.
- the module group includes a module for applying a resist to a substrate, a module for using a developer for the substrate, a module for heating the substrate, and a module for cooling the substrate.
- a development process is performed on the substrate.
- the substrate processing method of the present invention is characterized in that, when a plurality of substrates for which a transfer order is specified are transported to each module of a module group by a plurality of substrate transport mechanisms, the substrate transport method is used. Each mechanism performs one transfer cycle by sharing the operation of transferring a board from the previous module to one module in the next order, and after executing the one transfer cycle, moves to the next transfer cycle Then, the next transfer cycle is executed, whereby a substrate processing method in which a substrate is sequentially transferred from a module having a smaller order to a module having a larger order in the module group is described.
- the one transfer cycle is executed by another substrate transfer mechanism.
- one board transfer mechanism is positioned in front of the first module related to the transfer in charge of its own in the next transfer cycle with reference to the transfer schedule, and is on standby. Therefore, each transfer cycle can be executed quickly, and a high throughput can be obtained.
- FIG. 1 is a schematic plan view showing a substrate processing apparatus (including a coating and developing apparatus) according to the present invention.
- FIG. 2 is a schematic perspective view showing a coating and developing apparatus.
- FIG. 3 is an exploded perspective view showing a main transport mechanism used in the coating and developing apparatus.
- FIG. 4 is a side view showing a structure of a shelf unit in the coating and developing apparatus.
- FIG. 5A is a longitudinal sectional view showing a heating unit (PEB) of the shelf units.
- FIG. 5B is a plan view of the heating unit (PEB) in FIG. 5A.
- FIG. 6 is a plan view showing a wafer transfer path in a coating and developing apparatus.
- FIG. 7 is a control block diagram of a coating and developing apparatus.
- FIG. 8 is a diagram showing an example of a transfer schedule.
- FIG. 9 is a flowchart showing the operation of the main transport mechanism.
- FIG. 10 is a schematic plan view showing a positional relationship between each transfer mechanism and a wafer in a state in the middle of a transfer cycle.
- FIG. 11 is a schematic plan view showing a positional relationship between each transfer mechanism and a wafer in a state near the end of a transfer cycle.
- FIG. 12 is a schematic plan view showing the positional relationship between each transfer mechanism and a wafer in a state in the middle of another transfer cycle.
- FIG. 13 is a schematic plan view showing a positional relationship between each transfer mechanism and a wafer in a state near the end of another transfer cycle.
- FIG. 14 is a schematic plan view showing a conventional coating and developing apparatus.
- reference numeral B1 denotes a carrier mounting portion for carrying in and out a carrier C in which, for example, 13 semiconductor wafers W are hermetically stored.
- the carrier mounting section B1 includes a mounting table 21 on which a plurality of carriers C can be mounted, an opening / closing section 22 provided on a front wall of the mounting table 21, and a transfer arm 23 (substrate transfer mechanism). ing.
- the transfer arm 23 takes out the wafer W from the carrier C via the opening / closing section 22!
- a processing block B2 which is surrounded by a housing 24, is connected to the rear side of the carrier mounting portion B1, and the heating / cooling system is sequentially connected to the processing block B2 from the near side to the back.
- a main unit that can move up and down, move up and down, and rotate around a vertical axis to transfer wafers W between units including three shelf units Ul, U2, and U3, each of which includes multiple units.
- the transport mechanisms 25-1, 25-2 are arranged alternately. That is, the shelf units Ul, U2, U3 and the main transport mechanism 25-1, 25-2 are the carrier mounting sections.
- the wafer W is arranged in a line in front and back as viewed from the Bl side, and an opening for carrying a wafer (not shown) is formed at each connection portion. From the other end to the shelf unit U3 on the other end!
- the main transport mechanisms 25-1 and 25-2 include a shelf unit Ul, U2, and U3 side disposed in the front-rear direction when viewed from the carrier receiver B1, and a liquid processing unit U4 and U5 on the right side. It is placed in a space surrounded by a partition wall 26 composed of one side portion on the side and a back portion forming one side on the left side.
- FIG. 3 is an exploded view showing a part of the main transport mechanisms 25-1 and 25-2.
- Reference numeral 101 denotes a column, and a column is actually provided on the right side in FIG. 3, and an elevating bar 102 is provided between the columns 101.
- a base 103 is fixed to the elevating bar 102, and an arm mechanism 104 is attached to the base 103 so as to be rotatable (vertically rotatable) around a vertical axis.
- the arm mechanism 104 has three independently movable arms 105-107, so that the main transport mechanism 25-1 (25-2) has a shelf unit Ul, U2 and a liquid processing unit U4 (shelf unit U2, The wafer W can be transferred between the units U3 and the liquid processing unit U5).
- reference numerals 27 and 28 denote temperature and humidity control units provided with a temperature control device for the processing solution used in each unit and a duct for temperature and humidity control.
- the liquid processing units U4 and U5 are provided with an anti-reflection film chemical solution, a resist solution, and a developing solution, and a storage portion 29 that forms a space for supplying a chemical solution.
- BARC coating unit
- COT resist coating unit
- DEV developing unit
- the coating unit of the anti-reflection film will be called the anti-reflection coating unit
- the coating unit of the resist will be called the coating unit.
- cooling unit (CPL1) adjusts the temperature of the wafer W processed by the anti-reflection film unit (BARC) to a predetermined temperature before applying the resist liquid.
- BARC anti-reflection film unit
- POST post-baking unit
- CPL4 cooling unit Unit
- the cooling unit (CPL1) adjusts the temperature of the wafer W processed by the anti-reflection film unit (BARC) to a predetermined temperature before applying the resist liquid.
- BARC anti-reflection film unit
- PAB heats the wafer after applying the resist solution.
- the post-eta exposure baking unit (PEB) heats the exposed wafer W.
- the cooling unit (CPL3) adjusts the temperature of the wafer W heated by the unit (PEB) to a predetermined temperature before the development processing.
- the post baking unit (POST) heats the developed wafer W.
- the cooling unit (CPL4) cools the wafer W heated by the unit (POST).
- FIG. 4 shows an example of the layout of these units, and the heating unit (PEB)
- the shelf cutouts U1 to U3 include, for example, transfer units (TRS1 to TRS3 and TRS5) having transfer stages for transferring the wafer W as shown in FIG.
- the heating units (PAB) and (POST) are also provided with a heating plate for displacement, so that both powers of the main transfer mechanisms 25-1, 25-2 can be accessed! Puru.
- each unit on which the wafer W is mounted has an opening for loading and unloading the wafer W, a transfer arm 23 for mounting the wafer W in the unit, and a main transfer mechanism 25 — Equipped with lifting pins for transferring wafers W to and from transfer mechanisms such as 1, 25-2.
- Reference numeral 201 denotes a housing
- 202 denotes a stage
- 203 denotes a cooling window plate
- 204 denotes a calorie heat plate
- the cooling plate 203 is provided above the stage 202 so as to be movable in the horizontal direction, and has a slit 200 formed so as not to interfere with the elevating pins 209 and 210.
- the shirts 207 and 208 are provided so as to open and close the entrances 205 and 206, respectively.
- the elevating pins 209 and 210 are provided so as to be able to ascend and descend in sets of three.
- the main transport mechanism 25-2 can be accessed through a loading / unloading port 205, and a transfer arm 31 described later in the interface unit # 3 can be accessed through the loading / unloading port 206 into the housing 201. That is, in this heating unit ( ⁇ ), when the transfer arm 31 enters through the loading / unloading port 206, the wafer W on the transfer arm 31 is cooled through the lifting pins 209. Delivered to plate 203. Then, the wafer W is transferred between the cooling plate 203 and the heating plate 204 by moving the cooling plate 203 and elevating the elevating pins 210. The heated wafer W is unloaded by the main transfer mechanism 25-2 via the loading / unloading port 205.
- an exposure apparatus B 4 is connected to the inner side of the shelf unit U 3 in the processing block B 2 via an interface section B 3.
- the interface section B3 is provided with a main transfer arm 31A and an auxiliary transfer arm 31B.
- transfer arms 31A and 31B are collectively referred to as a transfer arm 31 for convenience of description, the transfer arm 31 is configured to be able to move up and down, rotate around a vertical axis, and move forward and backward. Te ru.
- the interface section B3 includes a peripheral edge exposure device (WEE) for selectively exposing only the edge portion of the wafer W, a transfer unit (TRS4), and a high-precision temperature control unit having a cooling plate. (CPL2). These are provided in the shelf units U6 and U7, respectively, in the force diagram described in the drawings for describing the operation described later. In practice, a buffer cassette for temporarily accommodating a plurality of, for example, 25 wafers W is provided, but the description is omitted to avoid complicating the description.
- WEE peripheral edge exposure device
- TRS4 transfer unit
- CPL2 high-precision temperature control unit having a cooling plate.
- the transfer arm 23 transports the unprocessed wafer and W in the carrier C placed on the carrier receiver B1 to the transfer unit (TRS1), completes the development, and after the process is placed on the transfer unit (TRS6). And transports the wafer W to the carrier C.
- the main transfer mechanism 25-1 transfers the wafer W on the transfer unit (TRS1) to the antireflection film unit (BARC), the cooling unit (CPL1), the coating unit (COT), and the transfer cut (TRS1). TRS2), and after the development process, the wafer W placed on the transfer unit (TRS5) is transferred in the order of the heating unit (POST), cooling unit (CPL4), and transfer unit (TRS6).
- the other main transfer mechanism 25-2 transfers the wafer W placed on the transfer unit (TRS2) after the resist coating process to the heating unit (P AB) and the transfer unit (TRS3), and further performs exposure.
- interface section B3 It has a role to transport the wafer W carried out and placed in the heating unit (PEB) in the order of the cooling unit (CPL3), the developing unit (DEV), and the delivery unit (TRS5).
- the transfer arm 31 uses the wafer W before exposure mounted on the transfer unit (TRS3) for the peripheral exposure device (WEE), the high-precision temperature control unit (CPL2), and the exposure device.
- WEE peripheral exposure device
- CPL2 high-precision temperature control unit
- PEB heating unit
- these transfer steps are performed by the transfer arms 31A and 3IB.
- the resist pattern forming apparatus performs drive control of the transfer arm 23, the main transport mechanisms 25-1, 25-2, and the transfer arms 31A and 31B, and controls other processing units.
- the control unit 4 is provided.
- FIG. 7 shows the configuration of the control unit 4.
- the power consisting of a CPU (Central Processing Unit), programs and memories, etc. will be described here with some of the components being described as blocks. I do.
- CPU Central Processing Unit
- reference numeral 40 denotes a system bus.
- a transfer recipe creation unit 41, a transfer recipe storage unit 42, a transfer schedule creation unit 43, a transfer schedule storage unit 44, a transfer control unit 45, and a standby position control unit 46 are connected to the system bus 40.
- a transfer arm 23, main transport mechanisms 25-1, 25-2, and a transfer arm 31 are connected to the control section 4 via controllers 51-54, respectively.
- the transfer recipe creation unit 41 creates a transfer recipe that associates the module with the transfer order of the wafer W when the operator specifies the transfer order of the wafer W for each module, and transfers the transfer recipe. It has a function of storing in the recipe storage unit 42.
- the module is a portion where the wafer W is placed, and indicates the transfer unit TRS1 and the antireflection film unit BARC which is a processing unit for performing a predetermined process. Looking at the order of flow in the coating and developing units, focusing on one wafer and W, the cassette C starts, the transfer stage TRS 1 and the anti-reflection coating unit BARC inter-module. And finally returned to the original cassette C, for example.
- the transfer schedule creation unit 43 has a function of creating a transfer schedule with reference to the transfer recipe and storing the transfer schedule in the transfer schedule storage unit 44.
- the transfer schedule is created by assembling the transfer cycle data specifying the transfer cycle in chronological order by associating the order of wafer W with each module, and is represented, for example, as shown in Fig. 8. .
- A1, A2 ??, Bl, B2 ?? represent wafers W, A1 is the first gen of lot A, A2 is the second wafer of lot A, and B1 is the second wafer of lot B. Indicate the wafer and the number of the wafer in which lot!
- the transport system of the coating and developing apparatus is configured to perform tasks for each transport cycle (also referred to as a phase).
- the transfer cycle defines the transfer operation of moving wafers one by one from the upstream side of the module group to the downstream module one by one and reaching the downstream end module. This specifies the number of the wafer to be placed.
- the downstream module is the module where the first Ueno and W are located.
- executing the transfer cycle 2 in FIG. 8 means executing a transfer operation for positioning the wafers Al and A2 in the transfer cut TRS1 and the antireflection film unit BARC, respectively.
- a transfer schedule is one in which such transfer cycles are arranged in chronological order.
- the first module is shown as the transfer unit TRS1 for convenience.
- the transfer control unit 45 controls the transfer system, in this example, the transfer arm 23, the main transfer mechanisms 25-1, 25-2, and the transfer arm 31, while referring to the transfer schedule.
- the standby position control unit 46 determines that each of the transfer arm 23, the main transfer mechanisms 25-1, 25-2, and the transfer arm 31 is called a substrate transfer mechanism. After completing the work (transport) in charge during the transfer cycle, the one substrate transfer mechanism refers to the transfer schedule while the one transfer cycle is being performed, and the one substrate transfer mechanism performs the next transfer cycle. It has a function to control it to move before the module that will perform the transport operation first.
- the module in which one substrate transfer mechanism performs the transfer operation first in the next transfer cycle is, in principle, the area covered by the one substrate transfer mechanism. And the module on the most upstream side of the module in which the wafer W exists. If there are wafers W of different lots within the area of responsibility, the module where the wafers W loaded into the coating / developing apparatus are placed is the target. Become.
- the lot means, for example, a wafer W for each carrier C.
- the transfer control unit 45 sequentially executes the transfer cycle in the first order with reference to the transfer schedule shown in FIG. First, referring to the transfer cycle 1, the transfer arm 23 takes out the wafer A1 from the carrier C and transfers it to the transfer unit TRS1. This completes the transfer cycle 1.
- the wafer A1 is taken out of the transfer unit TRS1 by one arm of the main transfer mechanism 25-1, then moved to the front of the anti-reflection film unit BARC and transferred here. Then, the next ueno and A2 are taken out from the carrier by the delivery arm 23 and delivered to the delivery unit TRS1.
- the wafer A2 is taken out from the transfer unit TRS1 by one arm of the main transfer mechanism 25-1, then moved to the front of the anti-reflection film unit BARC, and moved by the other arm.
- the wafer A1 is taken out from this, and the wafer A2 is transferred to the antireflection film unit BARC by the one arm.
- the main transfer mechanism 25-1 moves in front of the cooling unit CPL1, moves the other arm forward, and carries the wafer A1 into the cooling unit CPL1.
- each wafer flows between the modules.
- the force wafer which is also schematically shown in FIG. 6, is transferred to the transfer unit TRS2, the main transfer mechanism 25-2 also participates in the transfer.
- the main transfer mechanism 25-1 completes transfer from the coating unit COT to the transfer unit TRS2.
- the transfer from the transfer unit TRS5 to the heating unit POST is also performed.
- the feature of this embodiment is that in a system in which a plurality of substrate transfer mechanisms are provided as a transfer system and work in a transfer cycle is shared by the respective substrate transfer mechanisms.
- one main transport mechanism 25-1 operates according to the transport flow shown in FIG. 9, and upon receiving a transport instruction in step S1, performs a transport operation in step S2. If the main transfer mechanism 25-1 transfers wafer A6 from the transfer unit TRS1 to the anti-reflection coating unit BARC, the transfer operation still remains, so "NO" in step S3, returning to step S1, and returning to step S1. Is carried out. As a result, the wafers are sequentially transferred from the upstream to the downstream modules of the module group.
- step S4 in the next transfer cycle, which is the transfer cycle 8, the wafer is moved to the front of the module relating to the transfer of the last wafer of the earliest lot, ie, the antireflection film unit BARC, and waits.
- the data of the transfer cycle 7 in which the transfer is completed the data is moved to the module where the last wafer of the first lot is placed and waits.
- FIG. 11 shows this state.
- the arm 105-107 faces the transfer port of the module, and if the arm is advanced, the arm is ready to enter the transfer port of the module.
- the transfer cycle 7 the transfer of the wafer by the other main transfer mechanism 25-2 is performed, and the transfer cycle 7 ends when the wafer A1 is transferred to the transfer unit TRS3.
- the transfer cycle 8 is started, and one main transfer mechanism 25-1 goes to pick up the wafer A6 in the anti-reflection film unit BARC, while the other main transfer mechanism 25-1. Since the transfer is carried out according to -2, the transfer is performed in front of the antireflection film unit BARC during this time, so that the transfer operation can be performed promptly.
- the transfer operation of the one main transfer mechanism 25-1 ends with the operation force for taking out the wafer B4 from the cooling unit CPL1 and the transfer operation of the wafer B2 to the transfer unit TRS2 as shown in FIG. Subsequently, the transfer operation is continued by the other main transfer mechanism 25-2. During this time, the one main transfer mechanism 25-1 transfers the last wafer of the earliest lot in the transfer cycle 17, which is the next transfer cycle. Moves in front of the module involved in the transport of and waits. In this case, since the lot A is loaded into the apparatus earlier than the lot B, the earliest lot becomes the lot A, and the last wafer corresponds to the wafer A1 as shown in FIG.
- the module related to the transfer of the last wafer of the earliest lot in the next transfer cycle is the transfer unit TRS5, and one main transfer mechanism 25-1 receives the transfer as shown in FIG. It will move and wait before the transfer unit TRS5.
- the transfer cycle 17 starts, the wafer corresponding to the lot A is sequentially transferred from the upstream side to the next succeeding module, and the one main transfer mechanism 25-1 transfers the wafer to the next module.
- the wafer A1 is taken out from the transfer unit TRS5 as its first transfer operation, and transferred to the heating unit POST.
- this transfer operation corresponds to the last transfer operation of Lot A.
- the transfer of the wafers of the lot B is performed in the order of the downstream power.
- the main transport mechanism 25-1 corresponds to the substrate transport mechanism, and the standby control is performed. Focusing on the transport mechanism 25-2, this main transport mechanism 25-2 is equivalent to the substrate transport mechanism Then, the standby control is performed.
- each processing unit is described as being one. Actually, as shown in FIGS. 2 and 4, a plurality of processing units of the same type are provided. In that case, the number of transport cycles simply increases by that number, and the explanation of the present invention does not hinder the explanation even if the simplified illustration is performed as shown in FIG.
- the transport schedule is referred to and the first transport Because each module is set to wait in front of the module, when each transfer cycle is started, the wafer can be transferred simply by extending the arm. Therefore, the transfer cycle can be executed more quickly than in the case where the main transfer mechanisms 25-1, 25-2 are placed at the initial position and moved from there to the module, so that a high throughput can be obtained.
- the present invention is not limited to a coating and developing apparatus.
- a unit for coating a substrate with a chemical solution in which a precursor of an insulating film is dissolved may be applied to an insulating film forming apparatus incorporating a unit for performing curing, a unit for performing cooling, and the like.
- the substrate is not limited to a wafer, but may be a flat panel such as a glass substrate for a liquid crystal display.
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US11/525,854 US7383093B2 (en) | 2004-03-31 | 2006-09-25 | Substrate processing apparatus and substrate processing method |
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EP1965381B1 (en) * | 2007-03-02 | 2010-08-04 | Singulus Mastering B.V. | Control Method for Integrated Mastering System |
JP4894674B2 (ja) * | 2007-08-08 | 2012-03-14 | 東京エレクトロン株式会社 | 塗布、現像装置及び塗布、現像方法並びに記憶媒体 |
KR101005882B1 (ko) * | 2008-10-14 | 2011-01-06 | 세메스 주식회사 | 반도체 제조 설비 및 이의 제어 방법 |
JP2010177673A (ja) * | 2009-01-30 | 2010-08-12 | Semes Co Ltd | 基板処理設備及び基板処理方法 |
JP5181306B2 (ja) * | 2009-01-30 | 2013-04-10 | セメス株式会社 | 基板処理システム、露光前後処理ユニット及び基板処理方法 |
JP5392190B2 (ja) * | 2010-06-01 | 2014-01-22 | 東京エレクトロン株式会社 | 基板処理システム及び基板処理方法 |
JP5852908B2 (ja) * | 2011-09-16 | 2016-02-03 | 株式会社Screenホールディングス | 基板処理装置のためのスケジュール作成方法およびスケジュール作成プログラム |
KR102180468B1 (ko) * | 2019-07-08 | 2020-11-18 | 세메스 주식회사 | 반송 로봇의 운행 제어 방법 및 운행 제어 시스템 |
Citations (2)
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JPH10335416A (ja) * | 1997-05-30 | 1998-12-18 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JP2003324059A (ja) * | 2002-05-01 | 2003-11-14 | Tokyo Electron Ltd | 基板処理方法 |
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EP0915507B1 (en) * | 1996-06-07 | 2008-03-12 | Tokyo Electron Limited | Device for controlling treating station |
JP3995478B2 (ja) * | 2000-01-17 | 2007-10-24 | 株式会社荏原製作所 | 基板搬送制御装置及び基板搬送方法 |
US20020045967A1 (en) * | 2000-10-17 | 2002-04-18 | Masayuki Nakano | Substrate processing system |
JP3950299B2 (ja) | 2001-01-15 | 2007-07-25 | 東京エレクトロン株式会社 | 基板処理装置及びその方法 |
US20040026036A1 (en) * | 2001-02-23 | 2004-02-12 | Hitachi Kokusai Electric Inc. | Substrate processing apparatus and substrate processing method |
JP4076762B2 (ja) * | 2001-11-29 | 2008-04-16 | 東京エレクトロン株式会社 | 半導体ウエハ処理装置 |
JP4170864B2 (ja) * | 2003-02-03 | 2008-10-22 | 大日本スクリーン製造株式会社 | 基板処理装置および基板処理装置における基板搬送方法および基板処理方法 |
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Patent Citations (2)
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JPH10335416A (ja) * | 1997-05-30 | 1998-12-18 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JP2003324059A (ja) * | 2002-05-01 | 2003-11-14 | Tokyo Electron Ltd | 基板処理方法 |
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US20070016320A1 (en) | 2007-01-18 |
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US7383093B2 (en) | 2008-06-03 |
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