WO2004034422A2 - Wafer coating and singulation method - Google Patents

Wafer coating and singulation method Download PDF

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Publication number
WO2004034422A2
WO2004034422A2 PCT/US2003/027964 US0327964W WO2004034422A2 WO 2004034422 A2 WO2004034422 A2 WO 2004034422A2 US 0327964 W US0327964 W US 0327964W WO 2004034422 A2 WO2004034422 A2 WO 2004034422A2
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WO
WIPO (PCT)
Prior art keywords
wafer
integrated circuit
recited
coating
underfill material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/027964
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English (en)
French (fr)
Other versions
WO2004034422A3 (en
Inventor
Jing Qi
Janice Danvir
Tomasz Klosowiak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Motorola Inc filed Critical Freescale Semiconductor Inc
Priority to JP2004543275A priority Critical patent/JP2005538572A/ja
Priority to AU2003296904A priority patent/AU2003296904A1/en
Priority to KR1020057004220A priority patent/KR101054238B1/ko
Publication of WO2004034422A2 publication Critical patent/WO2004034422A2/en
Publication of WO2004034422A3 publication Critical patent/WO2004034422A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Definitions

  • This invention relates generally to a wafer-level method of providing an underfill material on flip chip integrated circuits. More particularly, the present invention relates to a method in which a bumped wafer is partially diced prior to the application of a polymeric underfill material.
  • flip chip packaging generally contemplates forming solder bumps (or other suitable contacts) directly on the contact pads formed on an integrated circuit die.
  • the die is then typically attached to a substrate such as a printed circuit board so that the die contacts directly connect to corresponding contacts on the substrate.
  • the solder bumps are then reflowed to electrically connect the die to the substrate.
  • an air gap typically remains between flip chip and substrate. This gap is commonly filled with material that is flowed into the gap in liquid form and then solidified. This material is typically a mixture of a resin and small silica spheres and is generally referred to as underfill, as it fills the gap under the chip.
  • the underfill material is applied in liquid form from a dispenser at one edge of the flip chip.
  • the underfill material then flows into the air gap and spreads across the flip chip until finally the entire area of the gap between flip chip and substrate is filled.
  • There are problems associated with underfill For example, the application of underfill must be repeated for each flip chip, and repeating this operation many times adds to the cost of manufacture.
  • separation of glass from resin may occur. This segregation of silica and resin alters the mechanical properties of the filled region and thereby negates the mechanical function of the underfill.
  • the method includes the steps of adhering a bumped wafer to an expandable carrier substrate, sawing the wafer to form individual chips, stretching the carrier substrate in a bidirectional manner to form channels between each of the individual chips, applying an underfill material to the bumped surfaces of the chips and around the edges of the chips, cutting the underfill material in the channels between the chips and removing the individual, underfill coated chips from the carrier.
  • This method suffers from the need to precisely control the bidirectional stretching of the carrier film, which is difficult to implement, and introduces new issues such as out of plane die.
  • FIG. 1 is a plan view of a wafer containing one or more integrated circuit flip chips in accordance with the present invention.
  • FIG. 2 is a flowchart detailing the process for providing an underfill material on an integrated circuit chip in accordance with certain embodiments of the present invention.
  • FIG. 3-11 are cross-sectional views of a portion of the wafer depicted in FIG. 1, in accordance with the present invention.
  • a novel method is described for providing an underfill material on an integrated circuit chip at the wafer level.
  • the wafer typically contains one or more integrated circuit chips, and each integrated circuit chip typically has a plurality of solder bumps on its active surface.
  • the wafer is first diced on the active surface side to form channels that will ultimately define the edges of each individual integrated circuit chip, the dicing being of such a depth that it only cuts part-way through the wafer.
  • the front side of the wafer is then coated with an underfill material. Generally, a portion of each solder bump remains uncoated, but in certain cases the bumps can be completely covered.
  • the back side of the wafer is then lapped, ground, polished or otherwise treated so as to remove material down to the level of the previously diced channels.
  • This reduction in the thickness of the wafer causes the original diced channels to now extend completely from the front side to the back side of the thinned wafer.
  • the wafer is then singulated by cutting the underfill material that was deposited in the channels during the coating step, so that the integrated circuit chip is released from the wafer, and the underfill material that was coated on the active side remains affixed to the active surface of each individual integrated circuit chip.
  • a wafer 10 contains one or more integrated circuit (IC) chips 12 patterned on a front or active side 36 thereof.
  • the wafer is typically a silicon wafer, but can also consist of other materials used to make ICs, such as gallium arsenide.
  • the IC chips are patterned in an array, typically orthogonal, and each of the ICs is pre-bumped. That is, a bump 34, typically a solder ball, has been applied to at least some of the contact pads on the IC.
  • the process and nomenclature of bumping wafers is well known to those of ordinary skill in the art of flip chip packaging, and will not be further elaborated upon here for sake of brevity. In the flowchart of FIG.
  • the first step 20 is that of providing the wafer just described.
  • the wafer is diced or sawn on the front or active side, as depicted in FIG. 3.
  • the wafer is not cut completely through, and the step of sawing 22 is performed so that the depth of the channels or grooves 38 formed in the wafer is such that they only extend part- way through the thickness of the wafer. Since the cuts formed by the dicing step do not extend completely through the thickness of the wafer, this leaves the wafer intact and in one piece, with the channels 38 defining what will ultimately become the edges or sides 39 of each individual flip chip 12.
  • an underfill material 40 is applied to the active surface 36 of each IC on the wafer in step 24.
  • underfill can be provided in a myriad of ways that are common to the art of coating and semiconductor processing. For example, one can dip, spray, flood coat, spin coat, or curtain coat a liquid solution of the underfill material onto the wafer, or the underfill material can be selectively applied by stenciling or printing. After applying a liquid solution of underfill, it obviously must be treated in such a way as to render it at least semi-solid, for example, by heating to remove residual solvents, or if it is a high solids material, by partially curing it to convert it from a liquid to a solid.
  • Some underfill materials that we find useful are epoxies, polyimides, and silicone-polyimide copolymers.
  • the underfill material is mass coated onto the surface of the wafer, as in dipping, spraying, flood coating, spin coating, or curtain coating liquid solutions, then it will at least partially fill 42 the channels that were cut in the wafer surface.
  • the coating 42 in the channels serves to also coat all the edges of each IC.
  • the underfill material 40 can be applied as a solid film, laminated onto the active surface of the wafer. Normally, the underfill material is applied such that at least a portion 45 of the surface of the bumps are left uncoated so that when the flip chip is ultimately assembled onto a printed circuit board, it will solder more easily.
  • our invention can be used in a manner where the bumps are completely covered 53 with the underfill material and the bumps 'solder through' the underfill during the flip chip assembly step.
  • an underfill material containing a fluxing agent that is useful in this embodiment is described in United States Patent No. 5,128,746 "Adhesive and Encapsulant Material With Fluxing Properties".
  • the underfill material 40 is selectively applied by stenciling or printing or laminating, then there would be little, if any, underfill material 52 in the channels, and thus there would be no underfill material on the edges 39 of the ICs.
  • An optional step 25, depicted in FIGs. 6 and 7, can be employed wherein a fluxing agent 60 is applied on top of the underfill material and the exposed portion of the solder bumps to aid in the soldering process during assembly to the printed circuit board.
  • the fluxing agent can be applied over the entire surface 60, or it can be selectively applied 70 only on the exposed portion of the solder bumps.
  • the wafer is placed active side down in a proper holding fixture 84 and the back side 80 (i.e. the side opposite the active side or the bumped side) is then lapped.
  • Lapping is a well known process of removal of some of the semiconductor wafer material to reduce the thickness of the wafer by a carefully controlled amount by moving the wafer across a flat plate 82 on which a liquid abrasive has been poured.
  • Back lapping is well known in the semiconductor industry. Other methods of material removal such as grinding or polishing are also contemplated as equivalents.
  • the lapping process continues until sufficient material has been removed from the back side of the wafer so that the channels 38 that were originally cut so as to only partially extend into the wafer, now traverse completely through the wafer from the front side to the back side as shown in FIG. 9. If one has followed the process embodiment depicted in FIG. 5 where underfill material is not deposited in the channels 38, then when the thickness of the wafer is reduced sufficiently so that the channels extend completely from front to back, the individual IC chips have been singulated by the act of lapping, as shown in FIG. 10, and no further processing is necessary. However, if underfill material has been deposited in the channels, then a step of singulating 28 is performed by cutting through the underfill material 92 remaining in the channels.
  • a laser excimer, UV, CO2 or other type
  • the individual IC chips 12 are free, and each chip has underfill material 112 on the edges that were defined during the step of dicing 22, since this secondary cut is typically narrower than the original dicing cut.
  • the underfill material 40 deposited on the active surface during step 24 remains on the active surface of the flip chip IC 112 after it has been singulated from the wafer.
  • our invention is implemented by dicing a wafer on the active surface to form channels that ultimately define the edges of each individual integrated circuit chip, the dicing being of such a depth that it only cuts part- way through the wafer.
  • the front side of the wafer is then coated with an underfill material. Generally, a portion of each solder bump remains uncoated, but in certain cases the bumps can be completely covered.
  • the back side of the wafer is then lapped, ground, polished or otherwise treated so as to remove material down to the level of the previously diced channels. This reduction in the thickness of the wafer causes the original diced channels to now extend completely from the front side to the back side of the wafer.
  • the wafer is then singulated by cutting any underfill material that was deposited in the channels during the coating step, so that the integrated circuit chip is released from the wafer, and the underfill material that was coated on the active side remains affixed to the active surface of each individual integrated circuit chip.
  • the processes described above can be implemented in any number of variations without departing from the present invention. In the illustrations above, multiple embodiments have been elucidated. Other combinations and permutations of these embodiments will occur to those skilled in the art upon consideration of the teachings herein. Those skilled in the art will also appreciate that other coating, dicing, cutting, fluxing, lapping and singulating process can be employed without departing from the present invention. Such alternative methodologies should be considered equivalents.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Wire Bonding (AREA)
PCT/US2003/027964 2002-09-11 2003-09-05 Wafer coating and singulation method Ceased WO2004034422A2 (en)

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JP2004543275A JP2005538572A (ja) 2002-09-11 2003-09-05 ウエハ被覆およびダイ分離するための切断方法
AU2003296904A AU2003296904A1 (en) 2002-09-11 2003-09-05 Wafer coating and singulation method
KR1020057004220A KR101054238B1 (ko) 2002-09-11 2003-09-05 웨이퍼 코팅 및 싱귤레이션 방법

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AU2003296904A1 (en) 2004-05-04
CN100416768C (zh) 2008-09-03
CN1682363A (zh) 2005-10-12
WO2004034422A3 (en) 2004-08-26
US6649445B1 (en) 2003-11-18
JP2005538572A (ja) 2005-12-15
AU2003296904A8 (en) 2004-05-04
KR20050054933A (ko) 2005-06-10

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