Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/319—Tester hardware, i.e. output processing circuits
  • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
  • G01R31/31932—Comparators

Definitions

• the present invention relates to a multi-strobe apparatus for generating a multi-strobe having a plurality of strobes, a test apparatus for testing an electronic device, and an adjustment method for adjusting the timing of generation of each strobe of the multi-strobe.
• the present invention relates to a multi-strobe device for controlling the generation timing of each strobe.
• one strobe is output with a delay for each cycle of the signal under measurement, and the value of the signal under measurement in each strobe is detected. A change point is detected.
• This method is used, for example, in a set-up Z-hold test of a memory to detect a change point of a value of a data signal and a DQS signal.
• a double data rate type device that outputs a data signal in synchronization with the rising or falling edge of a clock (D QS), such as DDR-SDRAM (Double Data Rate-SDRAM), requires a clock every predetermined output data width. Is output. This eases the setup Z-hold timing conditions for data transfer.
• D QS DDR-SDRAM
• Such a device needs to have a predetermined setup time and a predetermined hold time between the data signal and the clock in order to perform the data setup and hold without error.
• the value of the data signal and the value of the clock are each detected by a single slope, and the change point of each value is detected. Then, the quality of the device under test is determined based on whether or not each detected change point satisfies a predetermined setup time and hold time.
• an object of the present invention is to provide a multi-strobe device, a test device, and an adjustment method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
• the dependent claims define further advantageous embodiments of the present invention. Disclosure of the invention
• a multi-strobe apparatus for generating a multi-strobe having a plurality of strobes, the timing at which each of the plurality of strobes is to be generated.
• a clock generator that can generate an adjustment signal, a strobe generation circuit that generates multiple strobes, and an adjustment that adjusts the timing at which the strobe generation circuit generates each strobe based on the adjustment signal
• a multi-strobe device comprising:
• the crank generator sequentially generates an adjustment signal at a plurality of timings at which a plurality of strobes are to be generated, and the adjustment unit determines a slope based on the respective adjustment signals generated at a plurality of timings.
• the timing at which the generation circuit generates the corresponding strobe may be adjusted.
• the strobe generation circuit receives the strobe signal, delays the received strobe signal by a predetermined time, and sequentially outputs each as a strobe.
• the clock generator generates the adjustment signal in synchronization with the strobe signal.
• the multi-strobe device is provided corresponding to one of the variable delay circuits, and includes a plurality of timing comparators for comparing the timing of the strobe output from the corresponding variable delay circuit with the timing of the adjustment signal.
• the adjustment unit may adjust the delay time in each variable delay circuit based on a comparison result in the corresponding timing comparator.
• the adjusting unit changes the delay time in the variable delay circuit for adjusting the delay time, and determines that the timing of the slope output from the variable delay circuit to be adjusted substantially matches the timing of the adjustment signal. May be set to the delay time of the variable delay circuit to be adjusted.
• the variable delay circuit outputs a strobe multiple times for each delay time changed by the adjustment unit, and the driver comparator outputs an adjustment signal whose value changes at the time when the variable delay circuit to be adjusted outputs a strobe. Is generated multiple times, the timing comparator detects the value of the adjustment signal using the strobes output multiple times, and the adjustment unit compares the value of the adjustment signal before and after the change with the timing.
• the delay time of the variable delay circuit may be set to a delay time at which the number of times detected by the delay comparator is substantially the same.
• the adjustment unit includes a comparison result selection circuit that selects a comparison result of the timing comparator corresponding to the variable delay circuit to be adjusted among the comparison results of the plurality of timing comparators, and a comparison result selected by the comparison result selection circuit.
• a fail counter that counts the number of times the value before and after the change in the adjustment signal is detected may be provided.
• a plurality of cascaded circuits each of which is provided corresponding to one of the plurality of variable delay circuits, delays the adjustment signal by the offset delay amount of the corresponding variable delay circuit, and supplies the adjustment signal to the corresponding timing comparator. May be further provided. Late Each of the delay elements has substantially the same characteristics as the corresponding variable delay circuit, and the delay amount in the delay path that generates the minimum delay is the delay in the delay path that generates the minimum delay of the corresponding variable delay circuit.
• the adjustment variable delay circuit has substantially the same amount as that of the adjustment variable delay circuit, and the delay element delays the adjustment signal by an offset delay amount using a delay path that generates a minimum delay of the adjustment variable delay circuit.
• the cooktop generator includes an adjustment signal generation variable delay circuit that delays the adjustment signal by a desired delay amount and outputs the adjustment signal, and a linearization memory that controls the delay amount in the adjustment signal generation variable delay circuit. May have.
• a test apparatus for testing an electronic device comprising: a pattern generator for generating a test pattern for testing an electronic device; and a test pattern formed and supplied to the electronic device.
• a multi-strobe device for generating a multi-strobe having a strobe, the multi-strobe device comprising: a clock generator capable of generating an adjustment signal at a timing when each of the plurality of strobes is to be generated; A strobe generation circuit for generating a plurality of strobes, and a strobe generation circuit based on the adjustment signal.
• a test apparatus which comprises an adjusting unit for adjusting the timing of generating each of the probe. '
• the adjustment signal generation stage generates an adjustment signal
• the strobe generation stage generates a plurality of strobes.
• a multi-strobe adjustment method is provided.
• FIG. 1 is a diagram illustrating an example of a configuration of a test apparatus 100 according to an embodiment of the present invention.
• FIG. 2 is a diagram illustrating an example of a DDR-SDRAM setup test.
• FIG. 2 (a) shows an example of a timing chart of DQS and DQ
• FIG. 2 (b) shows another example of a timing chart of DQS and DQ.
• FIG. 3 is a diagram showing an example of the configuration of the clock generator 70 and the driver comparator 20.
• FIG. 4 is a diagram showing an example of the configuration of the multi-strobe device 30 and the timing comparison circuit 60.
• FIG. 5 is a diagram for explaining the timing adjustment of the strobe output from each variable delay circuit 46.
• FIG. 5 (a) is a diagram showing the timing adjustment of the slope 1
• FIG. 5 (b) is a diagram showing the timing adjustment of the slope 2.
• FIG. 6 is a flowchart showing an example of the multi-strobe timing adjustment method according to the embodiment of the present invention.
• FIG. 1 shows an example of a configuration of a test apparatus 100 according to an embodiment of the present invention.
• the test apparatus 100 tests the electronic device 200 by detecting the value of the output signal of the electronic device 200 using a multi-strobe having a plurality of strobes.
• the test apparatus 100 includes a period generator 10, a pattern generator 12, a waveform shaper 14, a peak generator 70, a driver comparator 20, and a judgment unit 16.
• the cycle generator 100 generates a timing signal for operating the test apparatus 100.
• the cycle generator 100 receives a test set signal indicating a timing for supplying a test pattern to the electronic device 200 from the pattern generator 12 and indicates a timing for supplying the test pattern to the electronic device 200.
• the signal is supplied to the waveform shaper 14.
• a reference clock for synchronizing the operation of the test apparatus 100 is generated and supplied to each component of the test apparatus 100.
• the pattern generator 12 generates a test pattern for testing the electronic device 200 and supplies it to the waveform shaper 14.
• the waveform shaper 14 and the clock generator 70 shape the received test pattern, and in accordance with the signal received from the period generator 10, convert the shaped test pattern to the electronic device 2 via the driver comparator 20. Supply to 0 0.
• the determiner 16 determines pass / fail of the electronic device 200 based on an output signal output from the electronic device 200 in accordance with a given test pattern.
• the determiner 16 generates a multi-strobe having a plurality of strobes, and a multi-strobe device 30 and a multi-strobe device 30 that detect the value of the output signal of the electronic device 200 using the generated multi-strobe.
• a logical comparator that determines pass / fail of the electronic device 200 based on the value of the detected output signal.
• the logic comparator 34 is supplied with an expected value signal to be output from the electronic device 200 from the pattern generator 12, and compares the expected value signal with the value of the output signal to obtain the electronic device 2. The quality of 0 0 is determined.
• the clock generator 70 may supply a strobe signal for causing the multi-strobe device 30 to generate a multi-strobe.
• the cycle generator 70 supplies a timing signal to the clock generator 70, and the clock generator 70 supplies a strobe signal to the multi-strobe device 30 based on the received timing signal.
• the electronic device 200 is, for example, a DDR-S DRAM, and the decision unit 16 outputs a DDDR signal, which is a data signal of the DDR-S DRAM as an output signal and a clock signal output in synchronization with the data signal. You may receive.
• the determiner 16 may perform a setup-no-hold test of the electronic device 200 based on the received data signal and DQS, and determine the quality of the electronic device 200.
• Figure 2 is the c present example is a diagram illustrating an example of setting up test DDR- SDRAM, the test device 1 00, the values of the DQS and the data signal (DQ) is detected by the multi-strobe respectively, electrons Perform device 200 setup test.
• the DDR-SDRAM outputs the DQ and DQS at almost the same rising edges, but the test equipment 100 uses the multi-slot to detect the DQ value and the multi-slot to detect the DQS value.
• the strobe occurrence timing is shifted by a predetermined offset amount, and each value is detected.
• the memory controller used when the DDR-S DRAM is actually used may shift the generation timing of the multi-strip on the DQ side by an amount that shifts the DQS with respect to the DQ.
• the test apparatus 100 determines pass / fail of the DDR-SDRAM based on whether or not the DDR-SDRAM outputs a DQ of a predetermined value at the detected change point of the value of the DQS.
• FIGS. 2 (a) and 2 (b) show an example of a timing chart of 0 ⁇ 3 and 13 (33.
• the test apparatus 100 determines that the DDR-SD RAM is a non-defective product, and in the example shown in FIG. Since the predetermined value is not shown, the test apparatus 100 determines that the DDR-SDRAM is defective.
• the test apparatus 100 in the present example detects a change point of a value for each of DQS and DQ using a multi-strobe. In other words, it is determined which of the multi-strobes has detected the change point of the DQS and DQ values. Then, based on the respective positions of the strobes at which the change points of the DQS and DQ values are detected, pass / fail of the DDR-SDRAM is determined.
• the test apparatus 100 in this example since the value is detected by a multi-strobe having a plurality of strobes for one cycle of DQ and DQS, when the delay time of DQ and DQS varies from cycle to cycle Even with this, the test can be performed with high accuracy. The same applies to the DDR-SDRAM hold test.
• FIG. 3 shows an example of the configuration of the clock generator 70 and the driver comparator 20.
• the clock generator 70 receives a set signal and a reset signal according to the test pattern from the waveform shaper 14, and generates a rising edge and a falling edge of the test pattern based on the set signal and the reset signal. I do.
• the clock generator 70 includes a variable delay circuit 22a for delaying the set signal, a variable delay circuit 22b for delaying the reset signal, and a linearization memory for controlling the delay time in the variable delay circuit 22a. 24a, a linearization memory 24b for controlling the delay time in the variable delay circuit 22b, and a set / reset latch 26.
• the linearization memory 24 a and the linearization memory 24 b control a delay time in the corresponding variable delay circuit 22 according to a test pattern to be given to the electronic device 200.
• Each linearization memory 24 stores control information for controlling the variable delay circuit 22 according to the delay setting value, and the control information is stored in accordance with the characteristic of the corresponding variable delay circuit 22. It has been calibrated in advance. As a result, the delay time in the variable delay circuit 22 can be accurately controlled.
• the set / reset latch 26 generates a rising edge and a falling edge of a test pattern to be supplied to the electronic device 200, based on the set signal and the reset signal delayed by the respective variable delay circuits 22. Then, the data is supplied to the electronic device 200 via the driver 28 of the driver comparator 20. Dry paco
• the comparator 32 of the comparator 20 compares the output signal output from the electronic device 200 with a predetermined value, and supplies the comparison result to the multi-strobe device 30.
• the output signal may be DQS and DQ described above.
• the multi-strobe device 30 detects the comparison result of the comparator 32 by using the multi-strobe, and supplies the detected comparison result to the logical comparator 34.
• FIG. 4 shows an example of the configuration of the multi-strobe device 30.
• the multi-strobe device 30 includes a strobe generation circuit 40 that generates a plurality of strobes, a timing comparison circuit 60 that detects the comparison result of the driver comparator 20 using a multi-strobe, and a strobe generation circuit 40. And an adjusting unit 50 for adjusting the timing of generating each of the above.
• the strobe generating circuit 40 is supplied with a strobe signal for generating a strobe.
• the strobe signal may be generated, for example, by the mouthpiece generator 70.
• the strobe generation circuit 40 has a plurality of variable delay circuits 46 connected in cascade. Further, the timing comparison circuit 60 has a plurality of cascade-connected delay elements 42 and a plurality of timing comparators 44.
• the plurality of variable delay circuits 46 receive the strobe signal, delay the received strobe signal by a predetermined time, and sequentially output each as a strobe to generate a multi-strobe.
• the plurality of delay elements 42 supply an output signal of the electronic device 200 to the timing comparator 44.
• each of the plurality of timing comparators 44 is provided corresponding to one of the variable delay circuits 46, and the strobe output from the corresponding variable delay circuit 46 and the output of the electronic device 200 are output. And the output signal is detected by the received strobe.
• Each of the plurality of delay elements 42 is provided corresponding to one of the plurality of variable delay circuits 46, receives the comparison result of the comparator 32, sequentially delays the received comparison result by a predetermined time, The signals are supplied to the corresponding timing comparators 4 4.
• Each delay element 42 delays the received comparison result by the offset delay amount of the corresponding variable delay circuit 46.
• the offset delay amount is a delay amount that occurs when a path that generates the minimum delay amount is selected in the variable delay circuit.
• the offset delay amount indicates a delay amount that occurs when a path that does not delay a signal is selected in the variable delay circuit. That is, the offset delay amount indicates an error between the delay set value and the delay time in the variable delay circuit 46.
• the delay element 42 reduces the delay time error in the variable delay circuit 46 by delaying the received signal by the offset delay amount of the corresponding variable delay circuit 46 and supplying it to the timing comparator 44. can do.
• Each delay element 42 has substantially the same characteristics as the corresponding variable delay circuit 46, and the delay amount of the delay path that generates the minimum delay is the minimum delay of the corresponding variable delay circuit 46.
• a variable delay circuit for adjustment that is substantially the same as the delay amount of the delay path that generates the delay signal, wherein the delay element 46 uses the delay path that generates the minimum delay of the variable delay circuit for adjustment to convert the received signal. Delay by the offset delay amount of the corresponding variable delay circuit 46.
• the delay element 42 is formed of the same material and the same process as the corresponding variable delay circuit 46.
• an adjusting variable delay circuit having the same characteristics as the corresponding variable delay circuit 46 as the delay element 42 it is possible to accurately generate the same delay amount as the offset delay amount in the variable delay circuit 46. I can do it. Further, even when the offset delay amount in the variable delay circuit 46 fluctuates due to a temperature change or the like, the fluctuation can be absorbed by using the delay elements 42 having the same characteristics.
• the timing comparator 44 detects the value of the signal output from the delay element 42 at the timing of the strobe received from the corresponding variable delay circuit 46, and logically converts the detected value via the adjustment unit 50. It is supplied to the comparator 34.
• the logical comparator 34 compares the value received from the timing comparator 44 with an expected value signal generated by the pattern generator 12.
• the determiner 16 described with reference to FIG. 1 determines pass / fail of the electronic device 200 based on the comparison result of the logical comparator 34. You.
• the test apparatus 100 detects the value of the output signal of the electronic device 200 by using the multi-strope, and determines the quality of the electronic device 200. Next, adjustment of the generation timing of a plurality of strobes in the multi-strope device 30 will be described.
• the clock generator 70 When adjusting the generation timing of a plurality of strobes in the multi-strobe device 30, the clock generator 70 outputs an adjustment signal whose value changes at the timing when each strobe of the plurality of strobes is to be generated. Output. That is, the crank generator 70 outputs an adjustment signal for setting the amount of delay in each of the variable delay circuits 46. In this case, the pattern generator 12 outputs a signal for generating the adjustment signal.
• the clock generator 70 generates an adjustment signal in synchronization with a strobe signal applied to the multi-stub device 30.
• the clock generator 70 generates the adjustment signal by using the previously calibrated linearization memory 24 and the variable delay circuit 22 (adjustment signal generation variable delay circuit) as described above.
• the clock generator 70 outputs an adjustment signal for setting the amount of delay in the first stage variable delay circuit 46-1 of the cascade-connected variable delay circuits 46. In other words, it outputs an adjustment signal whose value changes at a timing according to the delay amount to be set in the variable delay circuit 46-1.
• the adjustment signal is delayed by the plurality of delay elements 42 with a delay amount substantially equal to the offset delay amount of the variable delay circuit 46, and is supplied to the timing comparator 44.
• the timing comparator 44_1 detects the value of the adjustment signal using the strobe output from the variable delay circuit 46_1, thereby timing the change point of the adjustment signal value and strobe timing. Compare with.
• the adjusting unit 50 sets the delay time of the variable delay circuit 46-1, based on the comparison result of the timing comparator 44-1 ,.
• the cook generator 70 sequentially generates adjustment signals at a plurality of timings at which a plurality of strobes are to be generated.
• the adjusting unit 50 similarly sets the delay times of all the variable delay circuits 46 sequentially from the initial stage variable delay circuit 46 based on the respective adjustment signals generated at a plurality of timings.
• the strobe generation circuit 40 adjusts the timing at which each strobe is generated.
• the adjustment unit 50 includes a comparison result selection circuit 52, a fail counter 56, and an adjustment unit 58.
• the comparison result selection circuit 52 selects the comparison result of the timing comparator 44 corresponding to the variable delay circuit 46 whose delay time should be adjusted, from the comparison results of the plurality of timing comparators 44.
• the adjusting unit 50 adjusts the strobe timing output from the variable delay circuit 46 to be adjusted based on the selected comparison result so that the timing of the change point of the value of the adjustment signal matches the timing of the strobe timing. Adjust the delay time of the variable delay circuit 46.
• the adjusting section 50 sequentially changes the delay time of the variable delay circuit 4.6 to be adjusted, and the strobe timing output from the variable delay circuit 46 to be adjusted and the timing of the adjustment signal are adjusted.
• the delay time of the variable delay circuit 46 to be adjusted is set to the delay time determined by the timing comparator 44 to be substantially the same.
• the adjusting means 58 changes the delay time of the variable delay circuit 46 in order.
• the clock generator 70 outputs an adjustment signal each time the adjustment unit 50 changes the delay time of the variable delay circuit 46.
• the clock generator 70 may output the adjustment signal a plurality of times each time the adjusting unit 58 changes the delay time of the variable delay circuit 46 to be adjusted.
• the variable delay circuit 46 outputs a strobe a plurality of times in accordance with the adjustment signal, and the timing comparator 44 detects the value of the corresponding adjustment signal from each strobe.
• the comparison result selection circuit 52 supplies the selected plurality of comparison results to the file counter 56.
• the fail counter 56 counts, based on the received comparison result, the number of times the pre-change value in the adjustment signal is detected and / or the number of times the post-change value is detected in the adjustment signal.
• the adjusting means 58 sets a delay time in the variable delay circuit 46 to be adjusted based on the count result of the fail counter 56.
• the adjusting means 58 adjusts the delay of the variable delay circuit 46 to be adjusted to a delay time in which the number of times the value before the change in the adjustment signal is detected is substantially the same as the number of times the value after the change is detected. Set the time. Further, the adjusting means 58 determines the number of times the value before the change in the adjustment signal is detected or the number of times the value after the change is detected is an abbreviation of the number of times the variable delay circuit 46 to be adjusted outputs the strobe.
• the delay time of the variable delay circuit 46 to be adjusted may be set to be half.
• the adjusting means 58 adjusts the adjustment time to the delay time in which the difference between the number of times the value before the change in the adjustment signal is detected and the number of times the value after the change is detected in the changed delay time is the smallest.
• the delay time of the variable delay circuit 46 to be performed may be set.
• the adjusting means 58 changes the delay time in the variable delay circuit 46 to be adjusted, for example, in ascending or descending order, and adjusts the variable delay circuit 46 to be adjusted based on the counting result corresponding to each delay time.
• the adjusting means 58 may change the delay time in the variable delay circuit 46 to be adjusted based on, for example, a binary search method, and may detect the optimum delay time. . '
• each strobe interval in the multi-strobe can be accurately set to a desired interval.
• the test apparatus 100 is a variable delay circuit that uses an output signal transmission path including a driver comparator 20, a delay element 42, and a timing comparator 44, which is used when testing the electronic device 200. 4 Adjust the delay time of 6. For this reason, the influence of the timing error between the output signal and the multi-strope caused by the characteristics of the output signal transmission path can be reduced in the test of the electronic device 200. For example, the influence of the response characteristics of the timing comparator 44 can be reduced.
• the multi-strobe device 30 has a function and configuration similar to that of the clock generator 70. A lock generator may be further provided. In this case, the adjustment signal is generated by the clock generator included in the multi-stroop device 30.
• FIG. 5 is a diagram for explaining the timing adjustment of the strobe output from each variable delay circuit 46.
• the adjustment signal is a signal whose value changes from 0 to 1 at the timing when each variable delay circuit 46 should output a strobe.
• the timing comparator 44-1 detects the value of the adjustment signal in the strobe 1 a plurality of times.
• the variable delay is set so that the number of times the value 0 before the change is detected and the number of times the value 1 after the change is detected are substantially the same. Set the delay time for circuit 4 6—1.
• the mouthpiece generator 70 'generates an adjustment signal whose value changes at the timing when the slope 2 is to be generated.
• the adjustment unit 50 performs the timing adjustment of the strobe 2 in the same manner, and thereafter, similarly performs the timing adjustment of all the strobes. For example, adjust the timing so that all strobe intervals are ⁇ ⁇ .
• FIG. 6 is a flowchart illustrating an example of the method for adjusting the timing of the multi-stroke according to the embodiment of the present invention. This adjustment method adjusts the timing of each strobe of the multi-strobe generated by the multi-strobe device 30 in the same manner as the multi-strobe device 30 described with reference to FIGS.
• an adjustment signal is generated and output at a timing when each of the plurality of strobes is to be generated.
• S 300 may be performed using the clock generator 70 and the driver comparator 20 described with reference to FIG.
• a strobe generating step S302 a multi-strobe having a plurality of strobes is generated.
• S302 may be performed using the strobe generation circuit 40 described with reference to FIG.
• the delay time changing step S304 the delay time of the variable delay circuit 46 to be adjusted is changed, and the generation timing of the strobe to be adjusted is changed.
• S 304 may be performed using the adjustment unit 50 described with reference to FIG.
• a value detection step S306 the value of the adjustment signal in each strobe whose generation timing is changed is detected.
• the value of the adjustment signal may be detected a plurality of times at each generation timing as described above. S306 may be performed using the timing comparator 44 described with reference to FIG.
• a delay amount setting step S308 the delay amount of the variable delay circuit 46 to be adjusted is set based on the value detected in S306.
• S308 may be performed using the adjustment unit 50 described with reference to FIG.
• a multi-strope in which the timing of each strobe is accurately controlled can be generated. Therefore, the electronic device can be tested with high accuracy.

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• Engineering & Computer Science (AREA)
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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Tests Of Electronic Circuits (AREA)
• For Increasing The Reliability Of Semiconductor Memories (AREA)
• Dram (AREA)

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• 2002
  • 2002-10-01 JP JP2002289283A patent/JP4109951B2/ja not_active Expired - Fee Related
• 2003
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  • 2003-09-22 WO PCT/JP2003/012094 patent/WO2004031788A1/ja active Application Filing
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