TWI252626B - Multistrobe device, test device and adjustment method - Google Patents

Abstract

A multistrobe device comprises a drive comparator, a strobe forming circuit and an adjustment portion. The drive comparator is capable to produce a setting signal at the timing when each strobe of plural strobe should be formed. The strobe forming circuit is to form plural strobes. According to the setting signal the adjustment portion adjusts the occurrence timing of each strobe, which is formed by the strobe forming circuit.

Description

1252626 _ Case No. 92126784 V. INSTRUCTION DESCRIPTION (1) Technical Field of the Invention The present invention relates to a multi-trigger device and a test electronic device for generating a multi-sibebe having a complex strobe signal (strobe) The test device and the adjustment method for adjusting the timing of generating the trigger signals of the multi-trigger signals. In particular, the present invention relates to a multi-trigger device for controlling the timing of generation of each trigger signal. This application is also related to the following patent application. For those countries that have been identified as being designated by the reference document, the application is hereby incorporated by reference in its entirety to the extent of the disclosure of the application.

Japanese Patent Application No. 2 002-2 892 83; application date 2〇〇2 October 10 J 曰° [Prior Art] A conventional person, in the case of detecting a change point of a measured signal value, etc., The trigger signal is delayedly outputted by the cycle of the measured signal to detect the measured signal value of each trigger signal, and the change point of the detected value is detected. Such a method is used, for example, in a memory setting (s e t _ UP)/hod test, etc., for detecting a change point of a value of a data signal and a DQS signal. For example, DDR-SDRAM CDouble Data Rate-SDRAM), in the case of synchronous gray time: pulse: (10)), the double data rate Double Data Rate type device that outputs the data signal is matched with each output. , wide by this 'received in the data, to delay the timing conditions. In such a device, the 'Si; two relationship must be carried out without errors, between the data signal and the clock pulse.

The set time (set_up t ime) and the hold time (hW 1252626 ^ nc ^ ___92126784 - °ΪΤ year 丨 | 月丨7 g 倐正五, invention description (2) time). A trigger signal detects the data signal value and the clock pulse value. Then, by determining whether the determined set time and the holding time are satisfied by the detected change points, it is determined whether the test device is good or not. The relationship between the detected data signal and the value of each cycle of the DQS is not able to be tested with good accuracy in the case where the data signal or DQS is hopped due to various factors such as power supply fluctuations and thermal fluctuations of the device. Moreover, the relationship between scanning the data signal and the DQS by a trigger signal is time consuming in the test. The present invention therefore provides a multi-trigger device, a test device, and a tuning method for solving the above problems. This is achieved by the features described in the separate application of the scope of the application, and the dependent items are specific examples that are more advantageous. [Summary of the Invention] The triggering device is a multi-trigger device, and the characteristic trigger signal generating circuit and the signal for adjusting the complex touch can be generated. The triggering signal adjusting unit sequentially generates the number of each trigger signal clock generator according to the adjusting path. When the first embodiment of the invention is invented by the timing, the multi-trigger signal of the nominated student having the complex trigger signal includes a clock generator, a whole portion, wherein the clock generator, For the timing of each trigger signal, the production number is generated, and the signal for generating the complex trigger signal is used to adjust the timing of the trigger signal to generate electricity. The second is to name the complex trigger signal.

f The signal is used. The adjustment department can be based on the whole use of the letter iron, 丄 - to adjust the trigger signal to generate 1252626

Case No. 92126784 V. Description of the invention (3) Timing of the trigger signal corresponding to the road generation. The trigger signal generating circuit has a delay circuit to receive the trigger signal, so that the received set variable delay time 'equally outputs each trigger signal, 胄, Ί U delay adjustment signal, and sequentially adjusts the signal Corresponding to the "electricity. 夂, avoid the delay of the circuit, and the clock pulse generator is suitable for triggering the signal for the adjustment of Shanghai. In addition, the multi-trigger device is equipped with: a small port to generate a 'delay circuit' Any one, and then have a complex time series comparison crying 1 each variable delay circuit output trigger signal timing and weekly delay time, according to the corresponding time Π power circuit extension. j % 平乂,,, The result of the adjustment, the adjustment can be set in the delay time that should be added, and judged by the timing comparator; the adjustment of the variable delay circuit is triggered; the force is used by the timing of the signal, The delay time is roughly the same. The order of the variable delay circuit is to adjust the output of each trigger signal multiple times to drive the comparator (driver (r: r: r day; Γ), #在调整The variable delay circuit should output the trigger π = order: the adjustment signal will change the signal to generate a plurality of times i;: use: multiple rounds of the trigger signal 'to detect the tempo time, by ":: cry: The delay of the variable delay circuit is set--pre-order is detected by the rut before the change of the adjustment signal

1252626 Correction —— _ Case No. 92126784 V. OBJECT DESCRIPTION OF THE INVENTION (4) The number of times after the value of 14 is changed to the same time. The adjustment unit may have a comparison result selection circuit and a fail counter. Among them, the comparison result selection circuit selects the comparison result of the timing comparator corresponding to the variable delay circuit which should be adjusted, in the comparison result of the complex timing with the vehicle master. The attenuation counter counts the number of times before the change signal is changed and the changed value is compared with the result of the comparison selected by the comparison result selection circuit. Further, a plurality of delay elements connected in succession may be further provided, and each of the delay elements is configured to correspond to any of the complex variable delay circuits so as to extend only the deviation of the variable delay circuit corresponding to the adjustment signal (〇 f fset) Delay 1 ' is supplied to the corresponding timing comparator. Each delay element has substantially the same characteristics as the corresponding variable delay circuit, and is a delay amount of a delay path that generates a minimum delay, and a delay amount of a delay path that produces a minimum delay in the corresponding variable delay circuit. The variable delay circuit for adjustment is generally used, and the delay element is a delay path that generates a minimum delay by the variable delay circuit for adjustment, so that the adjustment signal is only delayed by the amount of deviation delay. The clock guard generator can have an adjustment signal to produce a variable delay circuit and a linearized s. Among them, the adjustment signal = generating a variable delay circuit, so that the adjustment signal is delayed output only by the desired delay. The linearized memory controls the amount of delay in the variable delay circuit generated by the adjustment signal. In a second embodiment of the present invention, there is provided a test apparatus which is a test apparatus for testing an electronic apparatus, characterized by comprising a patterning waveform shaper and a determiner. Wherein, the pattern generator is generated

Im Page 9 1252626 ---m 92126784 4 bucket car "month ι 7 mouth 5, invention description (5) Test the test pattern of the electronic device. The waveform is shaped to cry to form for supply to the electronic device. The determiner y = adds the test pattern to the output signal output by the electronic device, to determine f = test pattern, no. The determinator has a multi-trigger device that generates and =: a number of trigger signals for the sub-device to force the output signal value. Multi-signal pulse generator, trigger signal generation circuit and adjustment: ^ ^ contains clock generator to generate complex trigger signal; 2: clock pulse to generate adjustment signal. The trigger signal generates electricity: m timing, plus = way adjustment = according to the adjustment signal, "the circuit generates the timing of each trigger signal. ~ 砚 is produced in the third embodiment of the present invention, providing a method" Adjusting the adjustment of the timing of each trigger signal with the second trigger signal of the complex trigger signal is used as the taste = Γ transmission 唬 generation step and adjustment step. In the middle, the 娆 generation step 胄 is generated to generate a re-touch, Adjusting the complex trigger signal. The step of adjusting the step t 产生 generates a step of generating a signal in the trigger signal, and then using the signal to adjust the signal of each of the trigger signals, and the timing of each trigger signal is generated. This is not necessary to make all the features necessary for the present invention into an invention. The subcombination of the singularity group is also apparently easy to understand on the basis of the present invention, the following surnames, principles and other purposes and features. And the advantages can be described in more detail below, and a preferred embodiment, and with the accompanying drawings, [Embodiment] Page 10 1252626 Case No. 92126784 V. Invention Description (6) DETAILED DESCRIPTION OF THE INVENTION The present invention is not limited to the inventions of the claims, and the combinations of the features described in the embodiments are not necessarily limited to the means for solving the invention. An example of a configuration of a test device 关于 according to an embodiment of the present invention. The test device 100 detects the output signal value of the electronic device 200 by using a multi-trigger signal having a complex strobe signal. The electronic device 2 is tested. The test device 100 includes a cycle generator 1 , a pattern generator i 2 , a waveform shaper 14 , a clock generator (clock gene generator), a driver/comparator (driver) Comparator 20. The determiner 16 generates a timing signal for causing the test device 丨00 to operate. For example, the cycle generator 10 accepts the test pattern from the pattern generator 丨2 to the electronic device 2〇.测试The timing test setup (test “丨” signal/will, table. The signal of the timing of the test pattern supplied to the electronic device 20 is supplied to the waveform 14. Further, a quasi-crystal pulse which synchronizes the movement of the test apparatus 1 is generated and supplied to each of the constituent elements of the test apparatus 1 . Fortunately, the pattern generator 12 generates a test pattern for testing the electronic device 20 0 7 n ^ for the waveform shaper 14. The waveform shaper 14 and the clock burst generate a crying = shape the accepted test pattern, and the shaped test pattern is applied to the electronic device 200 in accordance with the apostrophe generated from the cycle. Supply Lieutenant? The 16 system determines whether the electronic device 200 is good or not according to the given test pattern according to the private signal of the electronic device. Determining the second-round trigger device 30 and the logic comparator 3 to generate a multi-trigger signal with a plurality of trigger signals by 1252626

The signal is sent to detect the output signal value of the electronic device 2〇〇. The logic comparator 3 4 determines whether the electronic device 20 is good or not based on the output signal value detected by the multi-trigger device 3 。. The logic comparator 34 supplies power from the pattern generator 12, and the device 20 outputs an expected value signal, and compares the output signal value with the expected value of 5 hai to determine whether the electronic device 2 is good or not. Further, the clock generator 7 供给 can also supply the trigger $ for generating the multi-trigger signal to the multi-trigger device 3 〇. In this case, the cycle generator 使 is supplied to the clock generator 7 〇, and the clock generator 7 supplies the trigger signal to the multi-trigger device according to the received timing signal. Further, when the electronic device 200 is, for example, a DDR-SDRAM, the determiner 16 is a data signal of a DDR-SDRAM which can also receive an output signal, and a D q S which is synchronized with a clock pulse signal output from the data k number. In this case, the determiner 16 performs a setting/holding test of the electronic device 2 based on the received data signal and DQS to determine whether the electronic device 20 is good or not. 2A and 2B are diagrams showing an example of a setting test of D D R - S D R A Μ. In this example, the test device 1 detects the D q S value and the data signal (DQ) value from the multi-trigger signals to perform the setting test of the electronic device 2 . dDR—SDRM allows the output edges of DQ and DQS to be output in a roughly uniform manner. The test device 100 is used to detect the timing of the generation of the multi-trigger signal of the DQ value, and the timing of detecting the multi-trigger signal of the DQS value. The values are detected by offsetting the amount of offset (preset) determined in advance. For example, the test device 1 can also use the memory controller used in the actual use of the DDR-SDRAM, and the DQ is only offset by the DQS, so that the timing of the multi-trigger signal on the DQ side is generated. Deviate.

Page 12 1252626 _ Case No. 92126784 - in the year of Vilg_ __ V. Invention Description (8) The test device 100 determines the DDR-SDRAM according to whether the DDR-SDRAM outputs the DQ of the fixed value at the change point of the DQS value. Good or not. The 2A and 2B drawings show an example of a timing chart of DQ and DQS. In the example shown in Fig. 2A, DQ indicates the relationship between the fixed values at the change point of the DQS value, and the test device is determined to determine that the DDR-SDRAM is a good product. Further, in the example shown in Fig. 2B, D Q does not indicate the relationship of the fixed value at the change point of the D Q S value, and the test apparatus 1 determines that the DDR-SDRAM is a defective product. In the test apparatus 100 of this example, the values of the DQS and the DQ are used to detect the change point of the value by using the multi-trigger signal. That is, in the trigger signals of the multi-trigger signal, it is determined whether the change point of the DQS and the DQ value is detected, and whether the DDR-SDRAM is good or not according to the positions of the trigger signals for detecting the change points of the dqs and _DQ values. determination. According to the test device of the present example, for one cycle of DQ and DQS, the value is detected by a multi-trigger signal having a plurality of trigger signals, and the delay time of DQ and DQS is dispersed in each cycle. It can also be tested with good precision. Also, the test can be performed in the DDR-SDRAM.

Fig. 3 shows an example of the configuration of the clock pulse generator 70 and the drive comparator 2'. The clock generator 70 receives the setting signal and the reset signal according to the measurement pattern from the waveform shaper 14 and generates a rising edge and a falling edge of the test pattern according to the setting signal and the reset signal. The clock generator 70 includes a variable delay circuit 22a, a variable delay circuit 2 2 b, a linearized memory (1 inearized mem 〇ry) 24 4 a, a linearized memory 24b, and a set reset latch. ) 26 and so on. The variable delay circuit 22a is a delay setting signal, and the variable delay circuit 22b

Page 13 1252626 Case No. 92126784 This year's q month repair" 5, invention description (9) is the delay reset signal, linearized memory 2 2 a control the delay time of the variable delay circuit 22a, linearize the memory 24b controls the delay time of the variable delay circuit 22b. The linearized memory 24a and the linearized memory 24 are controlled in accordance with the delay pattern of the corresponding variable delay circuit 2 in accordance with the test pattern 'to be given to the electronic device 200'. Each linearized memory 24 stores control information for controlling the variable delay circuit 22 in accordance with the delay set value, and the control information is previously corrected according to the characteristics of the corresponding variable delay circuit 22 ("calibration") Thereby, the delay time of the variable delay circuit 2 2 can be controlled with good precision. The reset latch 26 is set to be supplied to the electronic device 20 according to the setting signal and the reset signal delayed by each variable delay circuit 22 . The rising edge and the falling edge of the test pattern f of 0 are supplied to the electronic device 2000 via the driver 28 driven by the comparator 2, and the comparator 3 2 driving the comparator 2 is outputting the output signal and the set value. The comparison result is supplied to the second trigger device 30. Here, the 'output signal can be the above-mentioned _ and the multi-touch will be: the device 30 is detected by the multi-trigger signal in the comparator 32, and the result is ^ The comparison result is supplied to the logic comparator 34. Fig. 4 shows an example of the configuration of the multi-trigger device 3, which includes the trigger signal generating circuit 4〇, X = 5, wherein the trigger signal produce Road heart Π; :: 0 sequence comparison and adjustment section electric Du Nie r η - ^ thiophene "You sessile complex trigger signal. The signal is detected. Adjustment unit 5 匕t, ,, °, when multi-trigger each trigger signal: touch 5 „ signal generation circuit 4〇

Give trigger signal

Hi Page 14 1252626 曰 Amendment Case No. 92126784 V. Description of invention (10) = Trigger signal. The trigger signal can be generated, for example, by the clock generator 7 and the trigger signal generating circuit 40 has a plurality of delay circuits 46 connected in succession. Further, the day-to-order comparison power replies have a serial repeater comparator 44 in succession. The complex variable delay circuit 46 delays the timing of the trigger signal delay (5), and sequentially outputs each trigger signal to generate a multi-touch but the missing > Φ ^ ^9ηπ 玍 玍 触 汛唬 汛唬. The delay element 42 is such that the output signal of the sub-unit 200 is supplied to the timing comparator 44. Further, the complex timing comparator 44 is provided for each of the variable delay powers _, and receives the trigger signal output from the one-to-one/up variable delay circuit 46, and the electronic device 2 〇〇 = the outgoing signal 'accepted The trigger signal detects the output signal. The delay delay elements 42 are respectively supplied to the corresponding timing comparators 44 corresponding to the comparison result of the "comparison" of the complex variable delay circuit "accepting the comparison H32, and the received comparison result η is delayed. /, the received comparison result is only delayed by the offset delay amount of the corresponding variable delay circuit 46. The upper air' deviation delay amount is selected when the variable delay circuit 46 selects to generate the most = late path. The amount of delay generated, for example, the deviation delay = 曰 when the variable delay circuit 46 selects the path where the words are not delayed: the amount of delay generated. #, the amount of deviation delay is expressed in the variable delay delay setting The error between the value and the delay time can be reduced by the delay element 42 by delaying the signal of the f-type signal only by the delay of the variable delay circuit 46 corresponding to the delayed value to be supplied to the timing comparator 44. The error of the delay time of the circuit 46. The delay element 42 has a larger than the corresponding delay circuit 46.

IMI Page 15 1252626, tS_92126784 正条正五_, Invention Description (11) The same characteristic 'is the delay amount of each delay path that produces the smallest delay and the delay path of the corresponding variable delay circuit 46 that produces the least delay The delay amount is a substantially similar variable delay circuit for adjustment, and the delay element 42 uses a delay path for generating a minimum delay of the variable delay circuit for adjustment, and delays the received signal by delay only by the delay of the variable delay circuit 46 corresponding thereto. the amount. For example, the delay element 42 is formed of the same material and the same process as the corresponding variable delay circuit 46. With respect to the delay element 42, when the variable delay circuit is adjusted to have the same characteristics as the possible delay circuit 46, the delay amount which is the same as the deviation delay amount of the variable delay circuit 46 can be generated with good precision. Further, when the deviation delay of the variable delay circuit 46 is changed by a temperature change or the like, the variation can be absorbed by using the delay element 42' having the same characteristic. The signal comparator 34 outputted from the delay element 42 is detected from the timing comparators. The received comparator 34 is accepted from the timing comparator:: 夕立丨丨e crying 1 β 尨 从 从 从 % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % 逻辑 逻辑 逻辑 逻辑The electronic device 2 is enabled to determine the electronic device 200 for the production of the complex trigger signal by the above action, the test device 1 〇〇, the signal value is detected by the multi-trigger signal. Secondly, The multi-trigger device 30, the adjustment of the generation timing, will be described.

1252626

The timing that the number should generate is used to output an adjustment signal whose value changes. In other words, the clock pulse is generated as 70, and the relationship between the delay amounts set in the respective variable delay circuits 46 is outputted, and the adjustment signal is output. In this case, the pattern generator 12 outputs a signal for generating an adjustment signal. The clock generator 70 generates an adjustment number in synchronization with a trigger signal given to the multi-trigger device 3A. &quot; 4 button pulse generator 70, which uses the pre-corrected linearized memory 24 as described above and the variable delay circuit 22 (adjustment signal generating variable delay circuit) to generate the relationship of the adjustment signal, which can be expected The timing can produce an adjustment signal whose value changes with good precision. First, the clock burst generator 70 is in the variable delay circuit 46 which is successively connected, and the adjustment signal for the delay amount of the variable delay circuit set in the previous stage is set to be the variable delay circuit 46.丨 The adjustment signal whose value will change will be output in the order of the delay amount to be set. The adjustment signal is delayed by a delay of a predetermined amount by a delay amount from the variable delay circuit 46 to be supplied to the timing comparator 44. — 曰 Sequential comparator 44-1 detects the value of the adjustment signal by using the trigger signal of the variable delay circuit 46~ to perform the comparison, and compares the timing of the change point of the value of the signal with the trigger: (4) According to the comparison result of the timing ratio car feeder (6), the force port is set to set the delay time of the circuit circuit 46-1. </ br> </ br> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The adjustment unit 50 is based on the respective burst signals generated at the complex timing, by the same delay time of 46, from the wave on the front side. , engage in 4 two.,, late circuit Case No. 92126784 q This year, n month Ka 1252626 V. Invention Description (13) The trigger signal generating circuit 40 adjusts the timing of each trigger signal generation. The adjustment unit 50 includes a comparison result selection circuit 5, an attenuation count cry 56, and an adjustment means 58. The comparison result selection circuit 52 selects the comparison result of the timing comparator 44 corresponding to the variable delay circuit 46 to which the delay time should be adjusted, based on the comparison result of the complex number timing comparator 44. Adjustment unit = Adjusting the timing of the trigger signal outputted by the tampering delay circuit 46 to be adjusted according to the selected comparison result, and adjusting the timing of the adjustment signal value 2 to 1 point, and adjusting the variable delay The delay time of circuit 46. For example, the adjustment unit 50 sequentially changes the delay time of the variable delay circuit 46 to be adjusted, and sets the delay time of the variable delay circuit 46 to be adjusted, which is determined by the timing comparator 44. The timing of the trigger signal outputted by the variable delay circuit 46, which is adjusted, is the delay time when the timing of the signal is substantially identical. For example, the delay time of the I Γ1 variable delay circuit 46 is sequentially changed by the Uf pulse generator 7 〇, and the adjustment signal is output every time the variable delay circuit 46 L is delayed by +. If the sensitivity is changed by the adjustment means 5 8 , the delay time of the delay circuit 46 can be changed. Such a combination, variable delay circuit 4 6, output complex trigger signal, timing =:, two; = the selected complex comparison result is supplied according to the accepted comparison knot [count in the rounding page 18 1252626 Amendment No. 92126784 V. Description of the Invention (14) Two or any of the number of times the value of the signal before the change is detected and the number of times the value of the change is detected. The adjustment means 5 8 ' sets the delay time of the variable delay circuit 46 which should be adjusted based on the count result of the clothes down counter 56. For example, the adjustment means 580 sets the delay time of the variable delay circuit 46 which should be adjusted so that the number of times the detection value before the change of the adjustment signal is detected and the value after the change are substantially the same. delay. Further, the adjustment means 58 may be such that the number of times before the value of the adjustment signal is detected or the number of times the value after the change is detected is the output trigger signal of the variable delay circuit 46 which should be adjusted. In the case of roughly half of the number of times, the delay time of the variable delay circuit 4β which should be adjusted is set. Further, the adjustment means 580 can also set the delay time of the variable delay circuit 46 which should be adjusted, and the number of times the value before the change of the adjustment signal is detected during the delay time of the change The delay time when the difference between the number of times the changed value is detected is the smallest. Further, the adjusting means 528 is changed in the delay time of the variable delay circuit 46 to be adjusted, for example, in ascending order or descending order, and is set according to the counting result corresponding to each delay time. , the delay time of the variable delay circuit 46. Further, in another example, the adjustment means 58 may change the delay time of the variable delay circuit 46 which should be adjusted, for example, according to the binary search method or the like to detect the delay time. $Drawing ^ The setting of the delay time described above is set for all variable delay circuits 46 by sequentially from the front side, so that the multi-trigger signal trigger signals can be set to a desired interval. Also &quot;,

Page 19 1252626 修正 Amendment Case No. 921267W V. INSTRUCTIONS (15) Test apparatus 100 is used in , —. The output signal transmission path is used in the case where the test for driving the comparator into the electronic device 200 is included, and the delay between the processor 42 and the timing comparator 44 is used. Therefore, it is also possible to reduce the loss of the output caused by the characteristics of the delay signal of the delay::J: variable delay circuit 46 and the path of the multi-trigger signal. The influence of the error, the influence of the reaction characteristics of the electronic device 200, and j, can be reduced by the clock generator 7 of the timing comparator 44. The same can be seen: In this case, the clock generator for the transfer, the structure, and the structure is adjusted. The pulse generator generates a description of the clock 苐 5 A, 5 B of the multi-trigger device 30, and the trigger signal delay circuit 46 output by the delay circuit 46 The touch: % adjustment signal should be output, with each variable signal. First, the timing of the fifth step; the value of the delay from 0 to 1 is changed to 0, and the timing of the trigger signal 1 of the variable delay circuit of the previous stage is adjusted. Taking the variable delay circuit 46 ―1 in the direction of the trigger signal 1 the copper 敫咏 comparator 44-1 makes the trigger as illustrated in Fig. 4, the timing ratio is here, 4 ρ ρ: D旒ί The value of the adjustment signal is detected a plurality of times, and the result of the comparison of 44-1 is such that the number of times before the change of the value is changed, and the number of times after the change of the value 1 is detected is substantially the same. The delay time of the variable delay circuit 46-1 is set. The "clock pulse generator 70" is an adjustment signal that should generate a trigger signal 2 and the value will change. The whole part is 第5〇, and is the same as the timing of the trigger signal 2 Adjustment, the following, the same number of timing adjustments. For example, to make a full touch on page 20, 1252626 case number 92126784

V. INSTRUCTIONS (16) The interval is said to be the timing adjustment of T1. Fig. 6 is a flow chart showing an example of a timing adjustment method of a multi-trigger signal according to an embodiment of the present invention. The adjustment method adjusts the timing of each of the trigger signals of the multi-trigger signal generated by the multi-trigger device 3 in the same manner as the multi-trigger device 30 described in connection with the first to fifth and fifth embodiments. The 'first' is used in the adjustment signal generation step S3 00 to generate an adjustment signal at the timing at which the respective trigger signals of the complex trigger signal should be generated, and output. S3 0 0 can be performed using the clock generator 70 and the drive comparator 20 described in connection with FIG. Next, in the multi-trigger signal generating step S3 02, a multi-trigger signal having a plurality of trigger signals is generated. S 3 0 2 can be performed by the trigger δ ΤΙ 5 tiger generating circuit 40 as described in Fig. 4. Next, in the delay time changing step s 3 0 4, the delay time of the variable delay circuit 46 which should be adjusted is changed, and the timing of generating the trigger signal which should be adjusted is changed. S 3 0 4 can be performed using the adjustment unit 50 described in connection with Fig. 4. Next, in the value detecting step 306, the value of the adjustment signal for each trigger signal for changing the timing is detected. In S3 0 6, the adjustment signal value can be detected a plurality of times at the respective generation timings as described above. The S30 6 system can be implemented with a timing comparator 44 as described in connection with FIG. Next, in the delay amount setting step S308, the delay amount of the variable delay circuit 46 which should be adjusted is set in accordance with the value detected in S306. The S 3 0 8 system can be implemented by the adjustment unit 50 described in FIG.

Page 21 1252626 Revision _ Case No. 92126784 V. Description of Invention (17) Next, in decision step S 3 1 0, it is determined whether or not the delay amount of all variable delay circuits 46 is set. When the delay amount of all the variable delay circuits 46 is set, the termination processing is performed. Further, when the delay amount of all the variable delay circuits 46 has not been set, the delay amount of the adjustment signal is set in accordance with the variable delay circuit which should be adjusted next, and the processing of S 3 0 0 to S3 1 0 is repeated. . According to this adjustment method, the timing of generating the trigger signals of the multi-trigger signals can be adjusted with good precision.

While the embodiments of the present invention have been described, the technical scope of the invention of the present application is not limited to the above embodiments. The invention can be implemented in various modifications of the above-described embodiments. The invention is also subject to the technical scope of the invention relating to the scope of the patent application of the present application, which can be understood from the scope of the patent application. As apparent from the above description, according to the present invention, the timing of each trigger signal can be controlled with good precision to generate a multi-trigger signal. Therefore, the electronic device can be tested with good precision.

Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Page 22 q bucket year 1252626 曰 month Brief description of the drawings [Simplified description of the drawings] Fig. 1 is a view showing an example of the configuration of the test apparatus 1 〇 实施 according to the embodiment of the present invention. The 2A and 2B drawings are explanatory diagrams of an example of the setting of the DDR-SDRAM. Fig. 2A shows an example of a timing chart of DQS and DQ, and Fig. 2B shows another example of a timing chart of DQS and DQ. Fig. 3 is a block diagram showing an example of the configuration of the clock pulse generator 7 驱动 and the drive comparator 2 〇. Fig. 4 is a view showing a configuration of an example of a multi-trigger device 3A and a sequence comparison circuit 6〇. Figs. 5A and 5B are diagrams for timing adjustment of each variable delay circuit 4. Fig. 5A is a diagram showing the trigger signal of the table, and Fig. 5B is a timing adjustment showing the trigger signal 2. Fig. 6 is a diagram showing an example of the adjustment method. Timing of multi-trigger signal of 119 [Description of pattern] 10 cycle generator 12 pattern generator 14 waveform shaper 16 determiner 20 drive comparator 22 variable delay circuit 24 linearization memory 26 set reset latch 23 pages 1252626 / _ case number 92126784 gas this month day _ correction diagram simple description 28 driver 30 multi-trigger device 32 comparator 3 4 logic comparator 40 trigger signal generation circuit 42 delay element 44 timing comparator 46 variable delay circuit

50 Adjustment section 5 2 Comparison result selection circuit 56 Attenuation counter 58 Adjustment means 60 Timing comparison circuit 70 Clock pulse generator 100 Test device 2 0 0 Electronic device

Page 24

Claims (1)

1252626 ___MMl VI. Patent Application Range 1. A multi-trigger device is a multi-trigger device for generating a multi-signal signal with a plurality of trigger signals, and includes: a clock generator for generating the plurality of trigger signals. The timing of the trigger signal may be generated by an adjustment signal, the /trigger signal generation circuit generates the plurality of trigger signals, and the / adjustment unit adjusts the trigger signal generation circuit according to the adjustment signal. The timing of each trigger signal of the trigger signal. 2. The multi-trigger device according to claim 1, wherein the clock generator generates the sub-quantity sequence by the plurality of trigger signals, and sequentially generates the adjustment signal; And the adjusting unit adjusts the trigger signal generating circuit according to each of the adjusting numbers generated by the plurality of timings to generate a timing of the corresponding burst signal. 3. The multi-trigger device of claim 2, wherein the characteristic bee and the read trigger signal generating circuit have a plurality of variable delay delay circuits connected in succession to receive a trigger signal to accept the The trigger signal is delayed by a predetermined time, and each of the trigger signals is sequentially outputted; and the edge adjustment unit sequentially adjusts the delay time of the variable delay circuit according to each of the adjustment signals. 4. The multi-trigger device according to item 3 of the patent application, characterized in that Case No. 921 Zhou 784 1252626 VI. Patent Application Range The clock pulse generator generates the adjustment signal in synchronization with the trigger signal. 5. The multi-trigger device of claim 4, further comprising: a plurality of timing comparators each configured to correspond to any one of the variable delay circuits, wherein the comparison corresponds to the The timing of the trigger signal rotated by the variable delay circuit and the timing of the signal for adjustment; and μ are based on the corresponding time 庠th. The adjustment unit is based on the corresponding timing comparator ^ The effect of adjusting the delay time in one of the variable delay circuits is as follows: 6. The multi-touch station described in item 5 of the patent application scope.令: 裒, the characteristic of the adjustment portion is changed in the delay time of the variable delay circuit, and the delay time of the circuit that should be delayed is set by the variable delay of the &amp; i The variable delay circuit that should be adjusted = the comparator determines that the timing of the adjustment signal is substantially the same as the timing of the trigger signal. 7. The delay time is as in the sixth item of the patent application. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The timing, complex K, the variable delay circuit is generated to generate a plurality of times; the adjustment of ', ^^ is used as the dragon's timing comparator, which makes (4) some complex numbers ^ ^ &lt; 4 trigger signal page 26 The investigation unit delays the variable delay circuit by the timing comparator, and the adjustment is used as θ σ so that the set value and the changed value are substantially equal to each other before the change of t: t. The delay of the slogan 8. If the sneak peek of the scope of the stipulation of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations Selecting, in the comparison result of the complex timing comparators, a comparison result of the comparator corresponding to the 怍1 α′′ variable delay circuit that should be adjusted; and an attenuation counter, counting, in the comparison result The result of the comparison selected by the selection circuit is such that the value before the change of the adjustment signal and the number of times the value after the correction is detected. The multi-trigger device according to claim 5, characterized in that the multi-trigger device has: a plurality of delay elements, each of which is arranged in a continuous connection manner to correspond to any of the plurality of variable delay circuits, such that The adjustment signal is supplied to the corresponding timing comparator by the delay delay amount of the variable delay circuit corresponding to the delay value. ～10· The multi-trigger device according to claim 9 of the patent application, characterized in that. Each of the delay elements of the delay elements has substantially the same characteristics as the corresponding variable delay circuit, the delay amount of the delay path for generating the minimum delay, and the corresponding minimum delay of the variable delay circuit. Page 27 1252626 n / _ Case No. 92126784 C [December 丨 b曰 Amendment _ 6. The delay amount of the patent-wide delay path is a variable delay circuit that is roughly the same as the adjustment element. The delay path of the variable delay circuit that produces the minimum delay is adjusted so that the adjustment signal is delayed by only the offset delay amount. 11. The multi-trigger device of claim 1, wherein the clock generator comprises: an adjustment signal generating a variable delay circuit, wherein the adjustment signal is outputted by delaying a desired delay amount. And a linearized memory is controlled to generate a delay amount of the variable delay circuit at the adjustment signal. 1 2. A test device for testing an electronic device, which is a test device for testing an electronic device, comprising: a pattern generator for generating a test pattern for testing the electronic device; a waveform shaper, The test pattern is shaped to be supplied to the electronic device; and a determiner determines whether the electronic device is good or not according to the output pattern according to the test pattern; the determiner includes a The multi-trigger device generates a multi-trigger signal with a plurality of trigger signals to detect the output signal. The multi-trigger device includes: a clock generator that generates timings of the trigger signals of the plurality of trigger signals. Generating an adjustment signal; a trigger signal generating circuit generates the plurality of trigger signals; Page 28 1252626 Case No. 92126784 R This year's q month l $曰 Amendment 6. The patent application scope and an adjustment unit adjust the trigger signals of the trigger signal generating circuit to generate the trigger signals according to the adjustment signal. Timing. 1 3. An adjustment method for adjusting a multi-trigger device in a test device, which is an adjustment method for adjusting a timing for generating each trigger signal for a multi-trigger signal having a plurality of trigger signals, wherein The method for generating an adjustment signal is to generate an adjustment signal according to the timing of each trigger signal that should generate the plurality of trigger signals; the trigger signal generation step is to generate the plurality of trigger signals; and the adjusting step is based on The adjusting signal is used to adjust the timing of each of the trigger signals for generating the trigger signals in the trigger signal generating step. Page 29 1252626 n ^ _ Case No. 92126784 Year of the month 丨 曰 Correction VI. Designated representative map Page 4 (1), the representative figure of this case is: ____1____ diagram (2), the representative symbol of the representative diagram of the case is a simple description · 10 cycle generator 12 pattern generator 14 waveform shaper 16 determinator 20 drive comparison 3 0 multi-trigger device 34 logic comparator 7 0 clock generator 100 test device 200 electronic device