TW200406092A - Mutlistrobe device, test device and adjustment method - Google Patents

Abstract

A multistrobe device comprises a drive comparator, a strobe forming circuit and an adjustment portion. The drive comparator is capable to produce a setting signal at the timing when each strobe of plural strobe should be formed. The strobe forming circuit is to form plural strobes. According to the setting signal the adjustment portion adjusts the occurrence timing of each strobe, which is formed by the strobe forming circuit.

Description

200406092 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a test of a multi-trigger device and a test electronic device that generates a multi-trigger signal (multi si r0be) with a complex trigger signal (Strobe). A device, and an adjusting method for adjusting the timing (timi ng) of each trigger signal of a multi-trigger signal. In particular, the present invention relates to a multi-trigger device that controls the timing of the generation of each trigger signal. The present application is related to the following Japanese patent applications. For the countries designated by reference documents that can be incorporated into the designated countries, this application is incorporated as a part of this application by referring to the content of the following application. Japanese Patent Application No. 2002-289283; Chinese date of request October 1, 2002 ° [Prior art] The learner, in the case of detecting the change point of the measured signal value, etc., makes a trigger signal to be detected. Each period (cyc 1 e) of the measurement signal is delayed and output 'to detect the value of the measured signal at each trigger signal, and the change point of the detected value is added. This method is used, for example, in a set (up_up) / hold (ho 1 d) test of a memory, and is used to detect a change point in the value of a data signal and a dqs signal. For example, DDR-SDRAM (Double Data Rate-SDRAM), which is a double data rate device that outputs data signals in synchronization with the rise or fall of clock pulses (DQS), uses a predetermined output data amplitude to make the clock Pulse following output. With this, the timing of the 'set / hold' is eased when the data is given. In this kind of device, the setting / holding relationship of data should be performed without error. Between the data signal and the clock pulse,

12328pi f.ptd Page 5 200406092 V. Description of the Invention (2) It is broad, essential, and somewhat confusing. In addition, time (s e t _ u p t 丨 me) and holding time (h 〇 1 d time). Learn how to use the ancient energy ^ "^ and then send out the signal data and clock pulses of each detected data-and then 'by using the various change points detected, whether to meet the predetermined settings' time and holding time , To determine the goodness of the test device.

w ¥ but 'with support> trigger signal to detect each of the data signal and DQS: 2: 2 1 relationship,' due to device power changes, thermal changes, etc. = good =: try DQS again beating (⑽ -) Occasions, can not be equal to the DQS, during the test 3ν; \ — / trigger signal scan data signal 1 敫 in this month to provide a multi-trigger device, test device, and adjustment methods to solve the whistle The purpose of the independent project J in Yixia and Yili is to achieve this objective by combining the characteristics of the application and the special advantages. According to the attached items, the rules are changed. [Summary of the Invention] Multi-trigger device

The trigger signal is generated by the electric generator, which can produce positive π. In the eighth, the clock pulse generator is used to adjust the "signal. The timing of each trigger signal of the trigger t signal is generated. The trigger signal is adjusted to generate the electric clock pulse generator. Signal reply

200406092 V. Description of the invention (3) ----- The timing sequence is used to generate the adjustment signal in sequence. Each adjustment signal generated by the adjustment sequence is touched: Yes, the sequence of the corresponding trigger signal is generated based on the multiplexing. ^ Trigger signal generating circuit The trigger signal generating circuit is provided with vertical and continuous circuits to accept the trigger signal, so that the received trigger signal is counted for two times, and each trigger signal is sequentially output, and the adjustment signal is adjusted. Sequential adjustments can be made in accordance with the corresponding ;: 乂 = 乂 based on each room. "In the delay of the delay circuit, the two μ I m _ signals are synchronized to generate a triggering device ', which is set to correspond to each of the variable input timing comparators, so that the adjustment signal is touched at the corresponding time; the time depends on the corresponding Timing comparator power ::; Wither. Alas, it can be changed. The delay time of the delay circuit should be adjusted. The delay time of the library delay time is set by: 庠 海 :: variable delay circuit of the whole round to adjust the variable delay circuit. The “should be added” sequence is used for approximate timing and “adjusting the etch is always possible; the i-delay circuit is a gate that outputs the trigger signal multiple times for each delay time that the adjustment section changes, and drives the comparator (drivet time comparator). ), Is the timing of the adjusted number, so that its value will change. This f triggers the signal. Zhou Zheng uses k ^ tiger to generate multiple times.

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The comparator uses a trigger signal output multiple times to detect the value of the detection signal. The adjustment unit can set the delay time of the variable delay circuit, and the timing comparator detects the change in the adjustment signal. The delay time is approximately the same as the number of times of the changed value. The adjustment unit may include a comparison result selection circuit and a fail counter. Among them, the comparison result selection circuit selects the comparison result of the timing comparator corresponding to the available delay circuit which should be adjusted among the comparison results of the complex sequence comparator. The attenuation counter is a comparison result selected by the comparison result selection circuit, and counts the number of times that the value before the adjustment signal changes and the value after the change are detected. ^ It is also possible to have a plurality of delay elements connected in series. Each delay element is set to correspond to any of a plurality of variable delay circuits to delay only the deviation of the variable delay circuit corresponding to the adjustment signal (0 ff set) The amount of delay is supplied to the corresponding timing comparator. Each delay element has substantially the same characteristics as the corresponding variable delay circuit. It is the delay amount of the delay path that generates the minimum delay and the delay amount of the delay path that generates the minimum delay in the corresponding variable delay circuit. The variable delay circuit for adjustment and the delay element are roughly the delay path that generates the minimum delay using the variable delay circuit for adjustment, so that the adjustment signal should delay only the deviation delay amount. The clock-clock pulse generator 'may have an adjustable signal to generate a variable delay circuit and a linearized memory. Among them, the adjustment signal generates a variable delay circuit so that the adjustment signal is delayed and output only by a desired delay amount. Linearized memory, controlled by adjusting signal generation

12328pif.ptd Page 8 200406092 V. Description of the invention (5) ---- Delay amount of variable delay circuit. In the second embodiment of the present invention, a test device is provided, which is a test device for testing an electronic device, which is characterized by including a pattern generator, a waveform shaper, and a determiner. Among them, the pattern generator generates a test pattern for testing an electronic device. The wave shaper adds two tests to the test pattern: it is supplied to the electronic device. The judging device is to determine the output signal according to the test pattern, and set the output signal. | Zhizhiliang T-touch IK has a multi-trigger device that generates a signal with a complex Si signal to detect the output signal value. The multi-trigger device includes a clock generator, a trigger signal generating circuit, and an adjustment section. Among them, the clock pulse system is the timing of each touch signal that generates a complex trigger signal, and is added to. : i ^ k number. The trigger signal generating circuit generates a plurality of triggers and generates a channel b Ij. It adjusts the trigger signal generating circuit according to the adjustment signal to generate the timing of each trigger signal. Method In the third embodiment of this method, a multiple-trigger signal adjustment is provided. Each triggering core = t ί has a two-sequence adjustment method for generating multiple-trigger signals with a plurality of trigger signals. Signal = step by step and adjustment step ..., adjust the timing, and add: multiplex the trigger signal of each trigger signal of the f trigger signal. Lanthanum 敕 σ triggers the flood generation step, which is generated when the trigger signal is generated: two v? ′ Is adjusted according to the adjustment signal, and the above / = '/ time sequence of the signal is generated. The Ministry of Education enumerates all these special and continuous features that are necessary for the present invention, and the subcombination of the temple group.

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Become invention. In order to make the above-mentioned eyebrows of the present invention clearly understandable, the preferred and / or other features and advantages can be described in more detail as follows: The preferred embodiment is only used in conjunction with the accompanying drawings to make [embodiment] 廿Not below ^-Although the invention is described by way of an embodiment of the invention, the following embodiments are related to inventions that are in the scope of patent application, and all of the combinations of features described in the embodiments are not limited to the means required to solve the invention . FIG. 1 shows an example of the structure of the test device 00 in the embodiment of the present invention. The test device 100 is used to test the electronic device 200 by detecting the output < No. 5 value ' of the electronic device 200 with a multistrobe with a multiple trigger signal. The measurement device 1 includes a cycle generator 10, a pattern generator 1, 2, a waveform generator 14, a pulse generator (clOck, a driver comparator), and Determiner 16. The cycle generator 10 generates a timing signal for operating the measuring device 10 Q. For example, the cycle generator 10 receives a timing indicating that the test pattern is supplied to the electronic device 200 from the pattern generator 2 The test set signal provides a signal indicating the timing at which the test pattern is supplied to the electronic device 2000 to the waveform shaper 14. Further, a reference clock pulse is generated to synchronize the movement of the test device 100. Each component is supplied to the test device 丨 0 0. The pattern generator 12 generates a test pattern j for testing the electronic device 200 and supplies it to the waveform shaper 14. The waveform shaper 丨 4 and the clock punch generator 7〇 is to shape the test pattern received, according to the slave cycle generator

200406092 V. Description of the invention (7) = The shaped test pattern is given according to the pressing force provided by the drive-driven comparator 20—the test pattern is based on the input system of the electronic device and there are more than two F fV two 1 electrons. Goodness of device 200. Determiner 16 and logic comparator 34. The multi-trigger device # m has a multi-trigger signal with a digital trigger signal, and the generated multi-trigger device detects the output signal value of the electronic device 200. The value of the output signal detected by the trigger device 30 is determined by the logic comparator, and the electronic device #No is determined. The logic comparator 34 is an expected value signal that should be output from the pattern generator 12 to 200. The output signal value is compared with the expected value to determine whether the electronic device is 200 or not. The clock generator can also give the multi-trigger device 30 a touch signal for generating a multi-trigger signal. In this case, the period generator 10 is provided with the sequence k number to the clock pulse generator 70, and the clock pulse generator 70 supplies the trigger signal to the multi-trigger device 30 ° according to the received timing signal. The device 2 0 0 is, for example, the DR) SDRAM. The judging device 16 also outputs the data signal of the DDR-SDRAM and the DQS of the clock signal output in synchronization with the data signal. In this case, the judging device = performs the setting / holding test of the electronic device 2000 according to the received data signal and ㈧ ^ to determine whether the electronic device 2000 is good or not.

Figures 2A and 2B]] An illustration of an example of the setting test of D R-S D R AM. f In this example, the 'testing device 100' uses a multi-trigger signal to detect the DQS value and the data signal (DQ) value 'to perform the setting test of the electronic device 200. DDR —SDRM

200406092 V. Description of the invention (8) Although the rising edges of DQ and DQS are output in approximately the same way, the test device 100 is used to generate the timing of the detection of multiple trigger signals of DQ values and the multiple trigger signals of detecting DQS values In the timing of the generation, each value is detected by offsetting a predetermined amount of f set. For example, the test device 100 can also be a memory controller used in the actual use of DDR-SDRAM. The DQ is only offset by the amount of DQS, so that the timing of the multiple trigger signals on the DQ side is generated. To deviate. The test device 100 determines whether the DDR-SDRAM is good or not based on whether the DDR-SDRAM outputs a predetermined value of DQ at the point of change of the DQS value. Figures 2A and 2B are examples of timing diagrams showing D Q and D Q S. In the example shown in Figure 2A, at the point of change of the DQS value, DQ represents the relationship of the predetermined value, and the test device 100 is used to determine that the DDR-SDRAM is a good product. In the example shown in FIG. 2B, at the point of change of the DQS value, DQ does not show the relationship of the predetermined value, and the test apparatus 100 determines that the DDR-SDRAM is defective. In the test device 100 in this example, each value of DQS and DQ is used to detect a change point of the value using a multi-trigger signal. That is, at each trigger signal of the multi-trigger signal, it is determined whether the change points of the DQS and dq values are detected, and the goodness of the DDR-SDRAM is determined according to the positions of the trigger signals that detect the change points of the Dqs and DQ values. . According to the test device 100 in this example, for one cycle of DQ and DQS, the value is detected by multiple trigger signals with multiple trigger signals. Although the delay time of DQ and DQS is dispersed in each cycle, it is also Can be tested with good accuracy. The same holds true for the DDR_SDRAM retention test.

200406092 V. Description of the invention (9) Figure 3 shows an example of the configuration of the clock generator 70 and the driving comparator 20. The clock pulse generator 70 receives the setting signal and reset (r e s e t) signal according to the test pattern from the waveform shaper 14, and generates the rising edge and falling edge of the test pattern according to the setting signal and reset #. The clock generator 70 includes a variable delay circuit 22a, a variable delay circuit 2 2 b, a linearized memory (1 inearized memory) 2 4 a, a linearized memory 24 b, and a set reset latch. ) 26 and so on. Among them, the variable delay circuit 22a is a delay setting signal, the variable delay circuit 22b is a delay reset signal, the linearized memory 2 2 a is controlled by the delay time of the variable delay circuit 22a, and the linearized memory 24b is controlled by The delay time of the variable delay circuit 22b. The linearization memory 24a and the linearization memory 24 control the delay time of the corresponding variable delay circuit u in accordance with the test pattern to be given to the electronic device 200. Each linearization memory 24 stores control information that enables the delay circuit 22 to be controlled according to a delay set value, and the control information is corrected in advance according to the characteristics of the corresponding variable delay circuit 22 "(cal 1 brat ion). With this, the delay time in the variable delay circuit 22 can be controlled with good precision. The fixed supply of multiple fixed reset latches 26 is generated based on the set signals and reset signals delayed by the variable delay circuits 22. The test chart supplied to the electronic device 200 is a rising edge and a falling edge, and the driver of the comparator 20 is driven to the electronic device 200 via a medium. The comparator driving the comparator 20 is to compare the output signal outputted by the electronic = 0 with a predetermined value, and supply the comparison result to the touch roll I and set to 30. Here, the output signal ’may be the aforementioned _ and

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The evening trigger device 30 detects the comparison result in the comparator 32 by the multi-trigger signal, and supplies the detected comparison result to the logic comparator 34. / FIG. 4 shows an example of the configuration of the multi-trigger device 30. The multi-trigger device 30 includes a trigger trigger circuit 4 〇, a timing comparison circuit 6 〇, and an adjustment unit = ^ in the trigger signal generation circuit 4 () system. Generate a complex trigger signal. The time ratio circuit 60 is used to drive the comparison result of the comparator 2 to be detected by a multi-trigger signal. The adjusting unit 50 adjusts the timing of each trigger signal generated by the trigger signal generating circuit 40. The trigger generating circuit 40 is a trigger signal for generating a trigger signal. The trigger signal can be generated by the clock generator 70, for example. The trigger signal generating circuit 40 includes a plurality of delay circuits 46 in a series. The timing comparison circuit 60 includes a complex delay π element 42 and a complex timing comparator 44 which are successively successive. The complex variable delay circuit 46 receives a trigger signal, delays the received trigger signal by a predetermined time, and sequentially outputs each trigger A to generate a multi-trigger signal. The complex delay element "makes the output signal of the electronic device GO to a timing comparator 0. Moreover, the plural timing comparator 44 is provided for each of the corresponding variable delay circuits 46 and accepts the corresponding variable delay circuit 46 The output trigger signal and the electronic device 20 0 ^ output signal are detected by the received trigger signal. The complex delay elements 42 are each corresponding to any one of the complex variable delay circuits 46 and accept the comparator 32 For the comparison result, the received comparison result is sequentially delayed for a predetermined time and supplied to the corresponding timing comparator 44. Each delay element 4 2 causes the accepted comparison result to be delayed only by the corresponding variable delay.

200406092 V. Description of the invention (11) The deviation delay amount of the delay circuit 46. Here, the "deviation delay amount" is a delay amount generated when the variable delay circuit 46 selects a path that generates the smallest delay amount. For example, the offset delay amount refers to a delay amount generated when the variable delay circuit 46 selects a path that does not delay the signal. That is, the deviation delay amount indicates an error between the delay set value and the delay time in the variable delay circuit 46. By delaying the received signal by the delay element 42 by only delaying the offset delay amount of the variable delay circuit 46 corresponding to the delay signal to the timing comparator 44, the error in the delay time of the variable delay circuit 46 can be reduced. Each delay element 42 has substantially the same characteristics as the corresponding variable delay circuit 46. 'The delay amount of each delay path that generates the smallest delay and the delay of the corresponding delay path of the variable delay circuit 46 which produces the least delay. The variable delay circuit for adjustment is approximately the same amount, and the delay element 42 is a delay path that generates the minimum delay using the variable delay circuit for adjustment. The received signal is delayed only by the deviation delay of the corresponding variable delay circuit 46. the amount. For example, the 'delay element 42 is formed from the same material and the same process as the corresponding variable delay circuit 46. As for the delay element 42, when an adjustable variable delay circuit having the same characteristics as the corresponding variable delay circuit 46 is used, a delay amount equal to the offset delay amount of the variable delay circuit 46 can be generated with good accuracy. When the delay amount of the variation in the variable delay circuit 46 varies due to temperature changes, etc., the variation can be absorbed by using a delay element 42 having the same characteristics. The timing comparator 4 4 detects the timing of the trigger signal connected to the corresponding variable delay circuit 4 6 and detects the output of the delay element 4 2.

200406092 Invention description (12), the value L supplies the detected value to the logic comparator% via the adjustment unit 50. Logically, the comparator 34 compares the value received from the timing comparator 44 with the expected value signal generated by the pattern generator 12. The determination unit 16 described in FIG. 1 is based on the comparison result of the logic comparator 34 to determine whether the electronic device 20 is good or not. > From the above operation, the "test device 100" is to detect the output value of the electronic device 200 with multiple trigger signals to determine whether the electronic device 200 is good or not. Secondly, in the multi-trigger device 30, adjustment of the timing of generating the multiple trigger signals will be described. The stomach adjusts the timing of generating the multiple trigger signals of the multi-trigger device 30. In the occasion, the clock generator 70 outputs an adjustment signal whose value changes according to the timing of each trigger signal of the multiple trigger signal. That is, the 'clock pulse generator 70' outputs a signal for adjusting the relationship between the delay amounts set in the variable delay circuits 46. In this case, the pattern generator 12 outputs a signal for generating an adjustment signal. The clock generator 70 generates an adjustment signal in synchronization with a trigger signal given to the multi-trigger device 30. " The clock generator 7 〇 uses the previously-corrected linearized memory 24 and the variable delay circuit 22 (adjustment signal generation variable delay circuit) to generate the relationship between the adjustment signals, which can be expected. The timing can generate an adjustment signal whose value changes with good accuracy. First, the clock pulse generator 70 outputs a signal for adjusting the delay amount of the variable delay circuit 4 6-1 set in the preceding stage in the variable delay circuit 46 which is continuously connected in the vertical direction. That is, in accordance with the amount of delay that should be set in the variable delay circuit 4 6 — 丨

12328pif.ptd Page 16 200406092 V. Description of the invention (13) ------ Output the sequence whose value will change 敕 m ^ A9 ,, signal for adjustment. The adjustment signal is delayed by the plural delays of the plural certificates *, ν 〇, and the delay delay of the variable delay circuit 46, which are substantially the same, and are supplied to the timing comparator 44 by identifying A and M. The timing comparator 4 4 -1 is the triggering force used by M1 ~ 1; " Variation point of the value of the round signal of the variable delay circuit 4H " Compare the timing of the signal. The adjustment section ^ qu A 〇 之 The comparison result of state 4 4 — 1 sets the delay time of the variable delay circuit 46-1. < 庠 顺 7 ′ is used to generate the complex number of the complex trigger signal. The adjusting unit 50 is based on the use of a complex timing " using 仏 遽 ', and then all the variable delay circuits = the same time from the variable delay circuit 46 on the previous stage side ...: trigger signal generating circuit 4. To adjust the timing of each trigger signal generation, the adjustment unit 50 includes a comparison result selection circuit 52, an attenuation counter ^ shoulders & 58 ° comparison result selection circuit 52, which is selected from the comparison result of the complex timing t comparator 44. The comparison result of the timing comparator 44 corresponding to the variable delay circuit 46 whose delay time should be adjusted should be added. The adjustment side is to adjust the variable delay circuit when the timing of the trigger signal output by the variable delay circuit 46 to be adjusted is consistent with the timing of the change point of the adjustment signal value according to the selected comparison result. W delay time. For example, the entire period of 50 for 5 weeks is to change the delay time of the variable delay circuit 46 which should be adjusted in sequence.

200406092 V. Description of the invention (14) ------ The delay time of the variable delay circuit 46 is determined by the timing comparator 44 and the timing of the trigger signal output by the adjusted variable delay circuit 46 should be adjusted. The timing of the signals used is approximately the same as the delay time. For example, the adjusting means 58 changes the delay time of the variable delay circuit 46 in sequence. The clock generator 70 outputs an adjustment signal whenever the delay time of the variable delay circuit K is changed. In addition, the clock pulse generator 70 is capable of outputting an adjustment signal a plurality of times whenever the delay time of the variable delay circuit 46 to be adjusted is changed by the adjustment means 58. This frank, variable delay circuit 46 outputs a plurality of trigger signals in accordance with the adjustment signal, and the timing comparator 4 4 is an adjustment signal value corresponding to each detection signal. Select the comparison result, 52, to supply the selected complex comparison result to the attenuation counter 5 6. The attenuation counter 5 6 is based on the accepted comparison results, counting either or both of the number of times detected by the value before the change in the adjustment number and the number of times detected by the value after the change. Adjustment means 5 8 'It is the delay time of the variable delay circuit 46 that should be adjusted according to the counting result of the down counter 56. For example, the adjustment means 5 8 is the delay of the variable delay circuit 46 that should be adjusted. At time, the number of detections before the adjustment signal changes and the number of detections after the change become approximately the same delay time. The adjustment means 58 also allows the value before the adjustment signal to change. The number of detections, or the number of times the changed value is detected, is approximately half of the number of times the output trigger signal of the variable delay circuit 46 should be adjusted.

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delay. In addition, the adjusting means 58 can also set the delay time of the variable delay circuit 46 to be adjusted. The delay time of the variable delay circuit 46 can be changed, and the number of times the adjustment signal is detected before the adjustment signal is changed. The delay time when the difference between the subsequent values is the smallest. In addition, the adjustment means 58 is to add the delay time of the variable delay circuit 46 to be adjusted, for example, to change in ascending order or descending order, and set it according to the count result corresponding to each delay time. The variable delay circuit 46 has a delay time. Also, in other examples, the adjusting means 58 may also allow the initial delay time of the variable delay circuit to be adjusted, for example, to be changed based on the binary search method to detect the maximum delay time. 1: 1

By setting the delay time described above for all of the variable delay circuits 46 in sequence from the front side, the trigger signal intervals of the multi-trigger signal can be set at desired intervals with good accuracy. In addition, the test device 100 ′ is an output signal transmission path including the driving comparator 20, the delay element 42, and the timing comparator ^ used in the test of the electronic device 2000, and the variable delay circuit 46 is adjusted. Delay time two Therefore, the influence of the timing error between the output signal and the multi-trigger signal caused by the characteristics of the output signal transmission path can also be reduced during the test of the electronic device 2. For example, the influence of the response characteristics of the timing comparator 44 can be reduced, and the multi-trigger device 30 can be a clock generator having the same function and structure as the clock generator 70. In this case, the adjustment signal is generated by a multi-trigger # σ pulse generator. Clock

12328pif.ptd λ? ^ 4; · ώ4 ·

200406092 V. Description of the invention (16); f; ΐ should output the timing of the trigger signal, the value of which changes from 0 to 1: Hundred first, as shown in Figure 5A, making the variable delay circuit in the previous stage appear late. Time to time to adjust the timing of the trigger flood number 1 output by the variable delay circuit 46]. In the timing adjustment of the trigger signal, as illustrated in FIG. 4, the timing ratio 1 to 4 4 1 detects the value of the adjustment signal in the trigger signal 丨 multiple times, and the comparison result of the timing comparator 44 to 1 is In the case where the number of times of detection of the value before change is approximately the same as the number of times of detection of the value after change, the delay time of the variable delay circuit clan is set. Secondly, the clock generator 70 generates an adjustment signal whose value should change in sequence in which the trigger signal 2 should be generated. The adjustment section 50 is adjusted for the timing of the trigger signal 2 in the same manner as described in Section 5B f. Hereinafter, the timing adjustment is performed for all the trigger signals in the same manner. For example, the timing adjustment of all trigger signal intervals becomes T1. Fig. 6 is a flowchart showing an example of a timing adjustment method for a multi-trigger signal according to an embodiment of the present invention. This adjustment method is to adjust the timing of the multi-trigger signal generated by the multi-trigger device 30 in the same manner as in the multi-trigger device 30 illustrated in FIGS. 1 to 5A and 5B. First, in the adjustment signal generation step S300, an adjustment signal is generated at the timing of each trigger signal that should trigger a complex trigger flood, and output S 3 0 0, which can be generated using a clock pulse related to FIG. 3 Page 20 i2328pif.ptd 200406092 V. Description of the invention (17) -------- The device 70 and the comparator 2 are driven. Secondly, in the multi-trigger signal generating step S302, a multi-trigger signal having a retransmission signal is generated. S302 can be performed by the trigger signal generating circuit 40 related to FIG. 4. Second month, in the delay time changing step 8304, the delay time of the variable delay circuit 46 should be adjusted, and the timing of the generation of the trigger signal should be adjusted. S3 〇4 can be performed using the adjustment unit 50 shown in FIG. 4. The "human" is in the value detection step 306 to detect the value of the adjustment signal of each trigger signal that causes the timing to be changed. In S306, the adjustment signal value can be detected a plurality of times at each generation timing as described above. The M 6 series can be performed by a timing comparator 44 related to the timing chart illustrated in FIG. 4. Next, in the delay amount setting step S308, the delay amount of the variable delay circuit 46 which should be adjusted is set based on the value detected in S306. S308 can be performed by the adjustment section 50 related to the description in FIG. 4. Next, at decision step S 3 1 0, it is determined whether or not the delay amounts of all the variable delay circuits 46 are set. When the delay amounts of all the variable delay circuits 46 are set, the processing is terminated. When the delay amount of all the variable delay circuits 46 has not been set, the delay amount of the adjustment signal is set in accordance with the variable delay circuit to be adjusted next, and the processes of S30 0 to S310 are repeated. According to this adjustment method, the timing of each trigger signal of the multi-trigger signal can be adjusted with good accuracy. Although the embodiment of the above invention is described, the technical scope of the invention of the present application is not limited to the above embodiment. In the above embodiment

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5. Description of the invention (18), various changes can be made, and the invention described can also be implemented. This invention also belongs to Section B of the technical scope of the invention related to the scope of patent application for this application, which can be clarified from the contents of the patent application ®. It is clear from the above description that according to the present invention, the timing of each trigger signal can be controlled with good accuracy to generate a multi-trigger signal, and the electronic device can be tested with good accuracy. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in this art can make some changes without departing from the scope of, God, God and God. The scope of protection of 4 shall be as defined in the appendix, which shall be defined by the patent specification. 4 of the month 200406092 Brief description of the drawings [Simplified description of the drawings] Fig. 1 is a structural diagram showing an example of the structure of a test device 100 according to an embodiment of the present invention. 2A and 2B are explanatory diagrams of an example of the setting of DDR-SDRAM. FIG. 2A shows an example of timing charts of DQS and DQ, and FIG. 2B shows another example of timing charts of DQS and DQ. Fig. 3 is a configuration diagram showing an example of the configuration of the clock generator 70 and the driving comparator 20. Fig. 4 is a configuration diagram showing an example of the configuration of the multi-trigger device 30 and the timing comparison circuit 60. 5A and 5B are explanatory diagrams of adjustment of the touch timing output by each of the variable delay circuits 46. Fig. 5A is a diagram showing the touch of K 唬. Fig. 5B is a diagram showing the timing adjustment of the trigger signal 2 when the signal is adjusted. Fig. 6 is a flowchart showing an example of the method for implementing adjustment of the present invention. ? Timing of the trigger signal of the day [Illustration of the diagram] 10 Period generator 12 Pattern generator 14 Wave shaper 16 Decider 20 Drive comparator 22 Variable delay circuit 24 Linearized memory 26 Set reset latch

200406092 Brief description of drawings 28 Driver 30 Multi-trigger device 32 Comparator 34 Logic comparator 40 Trigger signal generation circuit 42 Delay element 44 Timing comparator 46 Variable delay circuit 50 Adjustment section 52 Comparison result selection circuit 56 Attenuation counter 58 Adjustment means 60 Timing comparison circuit 70 Clock generator 100 Test device 20 0 Electronic device

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Claims (1)

200406092 ^ m ^ ^ ^ ^ ^ is a multi-touch trigger device with multi-trigger trigger signals, which is characterized by a 'general clock pulse generation number, ## 本本 / 一 ^ ^ ^ system to generate the complex triggers The timing of the trigger signal can be added to each of the & ^ ^ double 峒 praise Λ number ^ J to generate a signal for adjustment; a trigger signal generation circuit, trolling — the electrical system generates some triggers The signal; and the flavor, are based on the adjustment signal to adjust the trigger signal, and the timing of each of the trigger signals that generates the trigger signals. • The multi-trigger device as described in item 1 of the scope of patent application, characterized in that: * the clock pulse generator is to generate the complex timing with the complex trigger signals, and sequentially generate the adjustment signal; and the adjustment The unit is adapted to adjust the trigger signal generating circuit to generate the corresponding timing of the trigger signal according to each of the adjustment signals generated by the plurality of timings. 3. The multi-trigger device as described in item 2 of the scope of patent application, characterized in that: the trigger signal generating circuit is provided with a plurality of continuously variable delay circuits in order to accept a trigger signal, so that the trigger is accepted. The signal is delayed for a predetermined time, and is sequentially output with the trigger signal; and the adjusting section sequentially adjusts a delay time in the corresponding variable delay circuit according to each of the adjusting signals. 4. The multi-trigger device as described in the scope of patent application: Item 3, which is characterized by: 200406092 200406092 6. The scope of the patent application is to detect the adjustment signal; and the adjustment unit is to set the delay time of the variable delay circuit to 'the timing comparator detects the value before the change of the adjustment signal and The number of times of the changed value becomes the delay time when the number of times is substantially the same. 8 · The multi-trigger device as described in item 7 of the scope of patent application, characterized in that the adjustment section has: a comparison result selection circuit, which is selected in the comparison results of the plurality of time-sequence comparators' corresponds to adjustments The comparison result of the comparator of the variable delay circuit; and a decrementer 'is counted, and the comparison result selected by the comparison result selection circuit makes the value before the adjustment signal change and The number of times the changed value was detected. 9 · The multi-trigger device as described in item 5 of the scope of the patent application, which is characterized by having a plurality of delay elements, each of which is set in a continuous manner to correspond to any of the plurality of variable delay circuits, The adjustment signal is supplied to the corresponding timing comparator only by the offset delay amount of the variable delay circuit corresponding to the delay ^. 10. The multi-trigger device as described in item 9 of the scope of patent application, characterized in that each of the delay elements of the eight-half L delay element has a special ke that is substantially the same as the variable delay circuit of the opposite ^ ^ I ζ < ^ Mindfulness, "For the delay amount of the delay path to generate the minimum delay, the amount of delay is equal to the number corresponding to the φ ^ JI 4 variable delay path. 200406092 The delay amount of the delay path is approximately the same as the variable delay circuit for adjustment. The delay element is a delay path that generates the minimum delay using the variable delay circuit for adjustment, so that the adjustment signal is delayed only by the The amount of deviation delay. 11. The multi-trigger device as described in item 1 of the scope of patent application, characterized in that the clock pulse generator includes a variable delay circuit for adjusting the signal, which causes the adjusting signal to be delayed by a desired delay amount. Output; and a linearized memory, which controls the amount of delay in the variable delay circuit generated by the adjustment signal. 1 2-A testing device for testing an electronic device 1 is characterized by comprising: < 1 a pattern generator for generating a test chart for testing one of the electronic devices-a waveform shaper electronic device; and for shaping the test Pattern to provide one of the output: 疋 屮 According to the test chart 依据, based on the judgment of the electronic device-cry / judge the goodness of the electronic device; 疋 /, dagger-multi-trigger device, which One of the plurality of touch signals is triggered multiple times.% /, Π rice doubles, one clock pulse generates the timing of each trigger signal, and one trigger signal generates. The multi-trigger device 1 'includes detecting the output signal; the device' can generate the complex trigger signals and generate an adjustment signal; the circuit 'generates the complex trigger signals; 12328pif.ptd Page 28 200406092 6. The scope of patent application and an adjustment unit adjust the timing of each trigger signal of the trigger signal generation circuit to generate the trigger signals based on the adjustment signal. 1 3. —An adjustment method is an adjustment method for adjusting the timing of generating multiple trigger signals with one of a plurality of trigger signals, which is characterized by: having an adjustment signal generating step to generate the plural triggers The timing of each trigger signal of the signal is added to generate an adjustment signal; the trigger signal generation step is to generate the plural trigger signals; and the adjustment step is to adjust the generation of the trigger signal according to the adjustment signal. The timing of each trigger signal of these trigger signals. 12328pi f.ptd Page 29