WO2003043065A1 - Masque et procédé de fabrication associé, et procédé de fabrication d'un dispositif semi-conducteur - Google Patents
Masque et procédé de fabrication associé, et procédé de fabrication d'un dispositif semi-conducteur Download PDFInfo
- Publication number
- WO2003043065A1 WO2003043065A1 PCT/JP2002/011939 JP0211939W WO03043065A1 WO 2003043065 A1 WO2003043065 A1 WO 2003043065A1 JP 0211939 W JP0211939 W JP 0211939W WO 03043065 A1 WO03043065 A1 WO 03043065A1
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- WIPO (PCT)
- Prior art keywords
- layer
- thin film
- mask
- support layer
- hole
- Prior art date
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Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/20—Masks or mask blanks for imaging by charged particle beam [CPB] radiation, e.g. by electron beam; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/30—Electron or ion beam tubes for processing objects
- H01J2237/317—Processing objects on a microscale
- H01J2237/3175—Lithography
- H01J2237/31793—Problems associated with lithography
- H01J2237/31794—Problems associated with lithography affecting masks
Definitions
- the present invention relates to a mask, a method of manufacturing the same, and a method of manufacturing a semiconductor device.
- the present invention relates to a charged particle transfer type lithography mask and a method of manufacturing the same, and a method of manufacturing a semiconductor device including a charged particle transfer type lithography step.
- EPL electron beam projection lithography
- LEEPL technology low energy electron-beam proximity projection lithography
- Ripple and Tokyo Seimitsu Sony The LEEPL technology is described, for example, in the document T. Utsumi, Journal of Vacuum Science and Technology B17 p.2897 (1999).
- Stencil masks have been proposed as masks for PREVA IL and LEE PL.
- the stencil mask has a thin film that scatters, reflects or absorbs an exposure beam such as an electron beam ion beam, and holes formed in a predetermined pattern so as to penetrate the thin film.
- the exposure beam passes through the portion of the hole penetrating the thin film, and is scattered, reflected, or absorbed by the thin film other than the hole, so that a predetermined pattern is exposed.
- a thin film in which such holes are formed is called a membrane.
- PREVAIL is usually a 4x reduction projection system, and an electron beam of about 100 keV is used.
- L E E P L is an equal magnification projection system, for example, an electron beam of 2 keV is used.
- the mask strength is reduced.
- the stencil mask for LEE PL has a thin membrane and forms a fine pattern that is the same size as the pattern to be transferred, a reduction in mask strength tends to be a problem.
- the reduction in mask strength is more remarkable than when diamond is used. If the mask strength is insufficient, the pattern is likely to be destroyed, for example, when cleaning the mask or loading the mask into an exposure machine.
- An object of the present invention is to provide a mask that can maintain the strength of the mask and a method of manufacturing the mask.
- Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a fine pattern with high precision.
- a mask of the present invention includes a thin film, a hole formed in the thin film through which a charged particle beam passes, and a support layer formed on one surface of the thin film.
- the support layer in the hole portion has an opening formed with a larger diameter than the hole.
- the charged particle beam includes an electron beam.
- the thin film (membrane) of the mask is thinned, the thin layer is reinforced by the support layer, and damage to the membrane is prevented.
- the thin film other than the holes through which the charged particle beams pass is uniformly reinforced by the support layer. Further, since the thickness of the thin film can be reduced, workability in forming the holes is improved. Therefore, holes corresponding to the mask pattern are formed with high precision in the thin film.
- a method of manufacturing a mask according to the present invention includes the steps of: forming a support layer on one surface of a substrate via an auxiliary layer; forming a thin film on the support layer; Removing a part of the substrate from the other side of the substrate to expose a part of the auxiliary layer, and forming a support frame composed of a part of the substrate around the exposed part of the auxiliary layer. Forming a hole through which a charged particle beam penetrates in a part of the thin film excluding the support frame, and supplying isotropic etching gas or gas to the support layer through the hole to perform isotropic etching. Performing a step of forming an opening with at least a large diameter in the support layer of the hole portion and a step of removing the auxiliary layer except for the support frame portion. I do.
- the method of manufacturing a mask according to the present invention includes a step of forming a thin film on one surface of the substrate, a step of forming a support layer on the thin film, and a method of forming the substrate from the other surface side of the substrate. Removing a portion to expose a part of the thin film, forming a support frame comprising a part of the substrate around the exposed portion of the thin film, and forming a trapping layer on the support layer Forming a hole through which the charged particle beam passes in a part of the thin film except for the support frame, supplying an etching liquid or an etching gas to the support layer through the hole, and the like.
- the thin film other than the holes can be reinforced with the support layer. Further, since the opening of the support layer is formed in a self-aligned manner with the hole and has a diameter larger than that of the hole, the charged particle beam is not hindered by the support layer.
- a method of manufacturing a semiconductor device includes irradiating a photosensitive surface with a charged particle beam through a mask having a predetermined mask pattern formed thereon, and transferring the mask pattern to the photosensitive surface.
- a method of manufacturing a semiconductor device comprising: forming a thin film as the mask, a hole through which the charged particle beam is formed in the thin film with the mask pattern, and a mask formed on one surface of the thin film.
- a mask having a support frame for supporting the thin film and the auxiliary layer having resistance to an etching solution or an etching gas for forming the opening in the support layer may be used. And features.
- the method of manufacturing a semiconductor device includes a semiconductor device including a step of irradiating a charged surface with a charged particle beam through a mask having a predetermined mask pattern formed thereon and transferring the mask pattern to the photosensitive surface.
- a method for manufacturing a device comprising: as a mask, a thin film; a hole formed in the thin film by the mask pattern; a hole through which a charged particle beam passes; and a support layer formed on one surface of the thin film. At least the support layer at the hole portion, an opening formed with a larger diameter than the hole, a support frame formed at least in part on the thin film excluding the hole, and supporting the thin film; Mask with Is used.
- FIG. 1 is a sectional view of a stencil mask according to Embodiment 1 of the present invention.
- FIGS. 2A to 2D are cross-sectional views illustrating manufacturing steps of a method for manufacturing a stencil mask according to Embodiment 1 of the present invention.
- FIG. 3A is a cross-sectional view of a stencil mask according to Embodiment 2 of the present invention
- FIGS. 3B to 3H show manufacturing steps of a method of manufacturing a stencil mask according to Embodiment 2 of the present invention. It is sectional drawing.
- FIG. 4 is a schematic diagram showing an example of an electron beam projection optical system according to Embodiment 3 of the present invention.
- FIG. 5 is a schematic view showing another example of the electron beam projection optical system according to the fourth embodiment of the present invention.
- FIG. 1 is a cross-sectional view of the mask of the present embodiment.
- the stencil mask 1 of the present embodiment is suitably used for LEEPL.
- the stencil mask 1 has a membrane 2, and the membrane 2 has, for example, a hole 3 in a part of a silicon layer 2a. Hole 3 penetrates membrane 2 and corresponds to the mask pattern It is formed in a shape.
- the size of the membrane 2 is several mm square to several 10 mm square, which is almost the same as the chip size.
- a material of the membrane 2 diamond or the like is used in addition to silicon.
- the thickness of the membrane 2 is, for example, 500 nm, but can be appropriately changed according to the energy of the electron beam used for EPL, the material or thickness of the support layer 4, and the like.
- a silicon oxide film having a thickness of, for example, 301 m is formed as the support layer 4.
- the portion of the support layer 4 in contact with the hole 3 is removed in a self-aligned manner with the hole 3.
- an opening 5 having a larger diameter than the hole 3 is formed in the support layer 4.
- the material of the support layer 4 can be changed to another material as long as it is resistant to an etchant used for etching for forming the holes 3 in the membrane 2 and can support the membrane 2.
- a silicon nitride film, a silicon oxynitride film, diamond, diamond-like carbon (DLC; Diamond Like Carbon) or a metal can be used as the material of the support layer 4.
- a silicon nitride film having a thickness of, for example, 100 nm is formed as the auxiliary layer 6.
- the silicon nitride film of the auxiliary layer 6 is used as, for example, an etching stopper as described later.
- the auxiliary layer 6 in the present embodiment is used as one etching stopper, but the auxiliary layer 6 is not limited to one etching stopper.
- a layer for forming the membrane 2 (the silicon layer 2a in the example of FIG. 1) or a layer laminated with the support layer 4 is an auxiliary layer. As shown in FIG. 1, the etching stopper layer 6 in the portion of the membrane 2 has been removed.
- the stencil / mask 1 has a support frame 7 surrounding the membrane 2.
- the frame 7 is provided to reinforce the mechanical strength of the membrane 2 and to prevent damage to the membrane 2 during manufacture and use of the stencil mask 1.
- Frame 7 is based on the pattern of membrane 2 on a silicon wafer, for example. It is formed by performing etching with the above-mentioned frame pattern. That is, a part of the silicon wafer can be used as the frame 7.
- the membrane 2 except for the vicinity of the hole 3 is reinforced by the support layer 4, so that the membrane 2 is prevented from being damaged.
- the support layer 4 since the support layer 4 has the opening 5 larger than the hole 3 in a self-aligned manner with the hole 3, the support layer 4 does not affect the transfer of the pattern.
- the membrane 2 since the membrane 2 is reinforced by the support layer 4, the membrane 2 can be made thinner. Therefore, the workability of the membrane 2 is improved, and it becomes easy to form a fine pattern on the membrane 2 with high accuracy.
- a silicon nitride film for example, is formed as an etching stopper layer 6 on a silicon wafer 7a by chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- a silicon oxide film for example, is formed as a support layer 4 thereon by CVD. Further, a single-crystal silicon layer 2a to be the membrane 2 is formed on the support layer 4 by, for example, epitaxy. Alternatively, a polycrystalline silicon layer or an amorphous silicon layer may be formed by CVD instead of a single crystal silicon layer. However, a single crystal silicon layer is desirable from the viewpoint of mechanical strength.
- a silicon oxide film is formed as a protective layer 8 by CVD.
- a layer other than a silicon oxide film may be used as long as it has resistance to an etchant used for etching the silicon wafer 7a.
- a resist 9 is formed on the back surface of the silicon wafer 7a with a frame pattern based on the pattern of the membrane 2 (see FIG. 1).
- the silicon wafer 7a is subjected to wet etching using the resist 9 as a mask to form a frame 7.
- Etchants for this wet etching include: For example, potassium hydroxide (K OH) or tetramethylammonium hydroxide ( ⁇ ; tetrametyllammomum hydroxide) can be used.
- the resist 9 and the protective layer 8 are removed.
- the protective layer 8 can be removed by wet etching using, for example, a buffer solution (BHF solution) containing hydrofluoric acid and ammonium fluoride.
- the frame 7 can be formed by performing dry etching on the silicon wafer 7a.
- a fluorine-based gas such as SF 6 or NF 3 can be used as an etchant.
- the etching of the resist also easily proceeds, and the resist may be lost before the etching for the thickness of the silicon wafer 7a is completed.
- a thermal oxide film or the like may be formed in advance on the back surface of the silicon wafer 7a as an etching mask layer.
- etching is performed in a predetermined pattern for the thickness of the silicon wafer 7a to form a frame 7. be able to.
- a resist 10 is formed on the silicon layer 2a in a pattern of holes 3 (see FIG. 1).
- dry etching is performed on the silicon layer 2 a to form holes 3.
- the resist 10 is removed.
- an isotropic etching is performed on the support layer 4 by supplying an etchant or an etching gas from the silicon layer 2a side through the hole 3.
- a silicon oxide film is formed as the support layer 4
- an opening 5 having a larger diameter than the hole 3 is formed in the hole 3 in a self-aligning manner by using, for example, a BHF solution as an etching solution.
- the etching proceeds in the support layer 4 due to the formation of the etching stopper layer 6.
- the etching stopper layer 6 is etched using the frame 7 as a mask, and the etching stopper layer 6 in the membrane 2 is removed. I do.
- a silicon nitride film is formed as the etching stopper layer 6, for example, by etching using heated phosphoric acid, the silicon nitride film of the support layer 4 is etched with respect to the silicon layer of the membrane 2. Only selective removal is possible.
- the stencil mask 1 of the present embodiment is formed.
- the method for manufacturing a semiconductor device of the present embodiment includes the LEEPL process using the stencil mask 1 of the present embodiment.
- An arm is placed on the membrane 2 side of the stencil mask 1 in FIG. 1, and the electron beam is irradiated from the frame 7 side. The electron beam passes through the hole 3 and the mask pattern is transferred to the resist on the wafer.
- the membrane 2 is reinforced, and the membrane 2 is prevented from bending, so that pattern displacement and distortion are prevented. Therefore, a fine pattern can be transferred with high precision in electron beam exposure. (Embodiment 2)
- FIG. 3A is a cross-sectional view of the mask of the present embodiment.
- the stencil mask 11 of the present embodiment is suitably used for LEEPL.
- the stencil mask 11 has a membrane 12, and the membrane 12 is, for example, a part of the silicon layer 12a. Holes 13 corresponding to the mask pattern are formed in the membrane 12.
- the size of the membrane 12 is several mm square to several 10 mm square, which is almost the same as the chip size.
- Diamond is used as the material of the membrane 12 in addition to silicon.
- the thickness of the membrane 12 is, for example, 300 nm, but can be appropriately changed according to the energy of the electrons used for the EPL, the material or thickness of the support layer 14, and the like.
- a silicon nitride film having a thickness of 500 nm is formed as the support layer 14.
- the portion of the support layer 14 in contact with the hole 13 is removed in a self-aligned manner with the hole 13. As a result, the support layer 14 has a larger diameter than the hole 13. A large opening 15 is formed.
- the material of the support layer 14 may be any other material as long as it is resistant to etchants used for etching to form the holes 13 in the membrane 12 and can support the membrane 12. You can change it.
- a metal such as a silicon oxide film, a silicon oxynitride film, diamond, and DLC may be used as the material of the support layer 14.
- a frame 16 is formed on the stencil mask 11 so as to surround the membrane 12.
- the frame 16 is provided for the purpose of reinforcing the mechanical strength of the membrane 12 and preventing the membrane 12 from being damaged during production and use of the stencil mask 11.
- the frame 16 is formed, for example, by etching a silicon wafer with a frame pattern based on the pattern of the membrane 12. Between the silicon layer 12a and the frame 16, for example, a 100 nm thick silicon oxide film 17 is formed.
- the silicon oxide film 17 is used as an etching stopper layer when forming a frame 16 by etching a silicon wafer.
- Silicon oxide B 17 can be changed to an auxiliary layer made of another material. If the silicon oxide B 17 is between the silicon layer 12a and the frame 16, the frame 16 and the membrane are used. 12 can be made from SOI substrate.
- the membrane 12 except for the vicinity of the hole 13 is reinforced by the support layer 14, the damage of the membrane 12 is prevented. Further, since the opening 15 larger than the hole 13 is formed in the support layer 14 in a self-aligned manner with the hole 13, the support layer 14 does not affect the transfer of the pattern. . Further, since the membrane 12 is reinforced by the support layer 14, the membrane 12 can be made thinner. Therefore, the workability of the membrane 12 is improved, and it becomes easy to form a fine pattern on the membrane 12 with high accuracy.
- a silicon oxide film 17 On the SOI substrate 18 on which the layer 12a is formed for example, a silicon nitride film is formed as a support layer 14 by CVD.
- a resist 19 is formed on the back surface of the silicon wafer 16a with a frame pattern based on the pattern of the membrane 12 (see FIG. 3A). Subsequently, the silicon wafer 16a is etched using the resist 19 as a mask to form a frame 16.
- This etching is performed by wet etching or dry etching as in the first embodiment.
- the silicon oxide film 17 becomes an etching stopper layer.
- the etch duster layer is an example of an auxiliary layer, but the silicon oxide layer is not limited to silicon oxide as an etch stopper layer.
- etching is performed on the silicon oxide film 17 using the frame 16 as a mask, and the silicon oxide film 17 on the membrane 12 (see FIG. 3A) is removed.
- This etching is, for example, wet etching using a BHF solution.
- a silicon oxide film having a thickness of, for example, 100 nm is formed on the support layer 14 as an etching stopper layer 2 ° by CVD. If the material of the etch stopper layer 20 is resistant to the etchant used for etching to form the opening 15 (see FIG. 3A) in the support layer 14, change to another material. Is also good.
- a resist m 21 a is formed on the surface of the membrane 12 on the frame 16 side.
- the resist coating surface is surrounded by the frame 16, if the resist is spin-coated, the resists 1 and 6 accumulate near the frame 16 and the resist cannot be applied with a uniform thickness. There is.
- a method for applying a resist to a surface having such irregularities is described in, for example, Japanese Patent No. 3084339, Japanese Patent Application Laid-Open No. H10-321493, and Japanese Patent Application Laid-Open No. H08-306. 6 1 No. 4, No. 11-32-99-38, or in the 61st Annual Meeting of the Japan Society of Applied Physics (2000) No.2 p.593 4a-X_l.
- a resist coating solution is placed on a substrate, the coating solution is spread thinly on the substrate with a scanner plate, and a slit that follows immediately after the scan nabrate The coating is evenly pressed onto the substrate by the air pressure blown out of the nozzle.
- the method of forming a resist film described in Japanese Patent Application Laid-Open No. H10-3211493 includes a step of applying a resist on a substrate surface and, for example, heating the lower surface of the substrate and cooling the upper surface to form a resist coating film.
- the method includes a step of forming a deteriorated layer and a non-transformed layer by partially transforming, and a step of removing the non-transformed layer.
- the resist is applied to the entire surface of the substrate by moving the substrate or the nozzle and spraying the resist in a mist form from the nozzle.
- nozzles are provided at a plurality of positions separated by a predetermined distance, and while the nozzles and the substrate to be processed are relatively moved, A processing agent such as a resist coating solution is supplied from a nozzle.
- the resist coating film 21a is exposed and developed to form a resist 21 to which the mask pattern has been transferred.
- dry etching is performed on the membrane 12 from the frame 16 side using the resist 21 as a mask, Form 1 3
- a fluorine-based gas such as SF 6 or NF 3 can be used as an etchant.
- the etching of the membrane 12 is performed from the frame 16 side. Therefore, during the etching, the entire surface of the etching stopper layer 20 is in contact with the stage of the etching apparatus, and the etched surface is stably supported. Therefore, deformation of the membrane 1′2 due to, for example, heat generation during etching or the like is prevented, and the processing accuracy of the pattern can be improved. After forming the holes 13, the resist 21 is removed.
- an isotropic etching is performed by supplying an etching solution or an etching gas from the side of the membrane 12 to the support layer 14 through the hole 13.
- an opening 15 having a larger diameter than the hole 13 is self-aligned with the hole 13 by, for example, wet etching using heated phosphoric acid. It is formed.
- the etching proceeds in the support layer 14 due to the formation of the etching stopper layer 20.
- the etching stopper layer 20 is removed by, for example, wet etching using a BHF solution.
- the stencil mask 11 of the present embodiment is formed.
- the method for manufacturing a semiconductor device of the present embodiment includes the LEEPL process using the stencil mask 1 of the present embodiment.
- a wafer is placed on the support layer 14 side of the stencil mask 11 in FIG. 3A, and an electron beam is irradiated from the frame 16 side. The electron beam passes through the hole 13 and the mask pattern is transferred to the resist on the wafer.
- the membrane 12 is reinforced and the deflection of the membrane 12 is prevented, so that the displacement and distortion of the pattern are prevented. Therefore, a fine pattern can be transferred with high accuracy in electron beam exposure.
- FIG. 4 is a schematic view of an exposure apparatus used for LEEPL, and shows an electron beam projection optical system.
- the stencil mask of Embodiment 1 or 2 can be suitably used for electron beam exposure using an exposure apparatus as shown in FIG.
- the exposure device 111 shown in Fig. 4 includes an electron gun 111 that generates the electron beam 112, an aperture 114, a condenser lens 115, and a pair of main deflectors 116, 1 17 and a pair of fine adjustment deflectors 1 18 and 1 19 are provided.
- the aperture 1 1 4 restricts the electron beam 1 1 2.
- the condenser lens 115 converts the electron beam 112 into a parallel beam.
- the cross-sectional shape of the electron beam 112 condensed by the condenser lens 115 is usually circular, but may be another cross-sectional shape.
- the main deflectors 1 16 and 1 17 and the fine adjustment deflectors 1 18 and 1 19 are deflection coils, and the main deflectors 1 16 and 1 17 are electron beams 1 1 and 2 are stencil masks 1 2
- the electron beam 1 1 2 is deflected so that it is basically perpendicularly incident on the 0 surface.
- the fine adjustment deflectors 1 1 8 and 1 1 9 are set so that the electron beam 1 1 2 is incident on the surface of the stencil mask 1 20 vertically or slightly inclined from the vertical direction. To deflect.
- the incident angle of the electron beam 112 is optimally adjusted according to the pattern position on the stencil mask 120, but the incident angle of the electron beam 112 is at most about 1 O mrad. 1 2 enters the stencil mask 1 20 almost perpendicularly.
- the electron beams 1 12 a to c in FIG. 4 indicate that the electron beams 1 1 2 a to c are almost perpendicularly incident on each position on the stencil mask. This does not indicate that light is simultaneously incident on the stencil mask 120.
- the scanning of the electron beam 112 can be either raster scanning or vector scanning.
- the resist 123 on the wafer 122 is exposed by the electron beam transmitted through the hole 122 of the stencil mask 120.
- a 1: 1 mask is used for LEEPL, and the stencil mask 120 and the wafer 122 are arranged close to each other. 1939
- a stencil mask as shown in the first or second embodiment of the present invention is used as the stencil mask 120.
- the membrane is strengthened by the support layer, deflection of the membrane is prevented, and displacement of the transfer pattern in electron beam exposure is reduced.
- the opening of the support layer is formed in a self-aligned manner with the hole of the membrane, the electron beam transmitted through the hole is not blocked by the support layer. If the opening of the support layer is not formed in the hole of the membrane in a self-aligning manner, the resist patterning for forming the opening in the support layer is performed by patterning the resist for forming the hole in the membrane. Independently of Jung, an opening is formed in the support layer by etching using a resist as a mask.
- the opening of the support layer by such a method, but in this case, the alignment accuracy of the patterning of the resist 1 on the support layer and the patterning of the resist on the membrane is sufficient.
- the electron beam that passes through the hole may be blocked by a part of the support layer. Therefore, when a fine pattern having a small alignment margin is formed, it is particularly preferable to form the opening of the support layer in a self-aligned manner with the hole of the membrane as described in the first or second embodiment.
- FIG. 5 is a schematic view showing an example of a projection optical system of another electron beam exposure apparatus to which the mask of the present invention can be applied.
- the pattern of the mask 201 is reduced and transferred at a predetermined magnification to a sample 202 such as a wafer using an electron beam.
- the trajectory of the electron beam is determined by the condenser lens 203, the first projection lens 204, the second 'projection lens 205, the crossover aperture 206, the sample bottom lens 207, and the plurality of deflectors 208. Controlled.
- a plurality of deflectors are used so that the electron beam transmitted through the mask 201 passes through the crossover aperture 206 and is perpendicularly incident on the sample 202. 2 0 8 force Generates a deflection magnetic field. It is also possible to apply the mask of the present invention to the above-described projection optical system, another charged particle beam device using a laser, or the like.
- Embodiments of the mask, the method for manufacturing the same, and the method for manufacturing a semiconductor device of the present invention are not limited to the above description.
- the mask of the present invention and the method of manufacturing the same can be applied to charged particle transfer lithography other than LEEPL.
- the present invention can also be applied to a PREVAIL, a variable-shaped electron beam direct lithography machine, a stencil mask for ion beam lithography, and a method of manufacturing the same.
- the present invention can be applied to a mask for X-ray lithography and a method for manufacturing the same.
- various changes can be made without departing from the gist of the present invention.
- a pattern can be formed on the membrane with high accuracy, and damage to the membrane during mask manufacturing can be prevented.
- a fine pattern can be transferred with high accuracy in charged particle transfer lithography.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Electron Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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KR10-2003-7008897A KR20040052454A (ko) | 2001-11-16 | 2002-11-15 | 마스크 및 그 제조방법과 반도체장치의 제조방법 |
DE10295694T DE10295694T1 (de) | 2001-11-16 | 2002-11-15 | Maske, Verfahren zum Herstellen dieser Maske und Verfahren zum Herstellen eines Halbleiterbauelements |
US10/250,555 US7022607B2 (en) | 2001-11-16 | 2002-11-15 | Mask and its manufacturing method, and method for manufacturing semiconductor device |
US11/284,902 US20060079091A1 (en) | 2001-11-16 | 2005-11-23 | Mask, method of producing the same, and method of producing semiconductor device |
US11/347,205 US20060269850A1 (en) | 2001-11-16 | 2006-08-04 | Mask, method of producing the same, and method of producing semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2001-352014 | 2001-11-16 | ||
JP2001352014A JP3900901B2 (ja) | 2001-11-16 | 2001-11-16 | マスクおよびその製造方法と半導体装置の製造方法 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/284,902 Division US20060079091A1 (en) | 2001-11-16 | 2005-11-23 | Mask, method of producing the same, and method of producing semiconductor device |
US11/347,205 Continuation US20060269850A1 (en) | 2001-11-16 | 2006-08-04 | Mask, method of producing the same, and method of producing semiconductor device |
Publications (1)
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WO2003043065A1 true WO2003043065A1 (fr) | 2003-05-22 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2002/011939 WO2003043065A1 (fr) | 2001-11-16 | 2002-11-15 | Masque et procédé de fabrication associé, et procédé de fabrication d'un dispositif semi-conducteur |
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Country | Link |
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US (3) | US7022607B2 (ja) |
JP (1) | JP3900901B2 (ja) |
KR (1) | KR20040052454A (ja) |
DE (1) | DE10295694T1 (ja) |
TW (1) | TW591343B (ja) |
WO (1) | WO2003043065A1 (ja) |
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JP4346063B2 (ja) * | 2002-12-03 | 2009-10-14 | 大日本印刷株式会社 | 転写マスクブランク、転写マスク並びにその転写マスクを用いた転写方法 |
JP3842727B2 (ja) | 2002-12-26 | 2006-11-08 | 株式会社東芝 | ステンシルマスク及びその製造方法 |
JP2004207572A (ja) * | 2002-12-26 | 2004-07-22 | Toshiba Corp | ステンシルマスク及びマスク形成用基板並びにステンシルマスクの製造方法及びマスク形成用基板の製造方法 |
KR100555503B1 (ko) * | 2003-06-27 | 2006-03-03 | 삼성전자주식회사 | 메인 스트럿과 보조 스트럿을 가지는 스텐실 마스크 및 그제조 방법 |
JP2005042147A (ja) | 2003-07-25 | 2005-02-17 | Dainippon Screen Mfg Co Ltd | 蒸着用マスクの製造方法および蒸着用マスク |
JP4362350B2 (ja) * | 2003-11-12 | 2009-11-11 | ソニー株式会社 | ステンシルマスクの製造方法 |
DE102004012240B4 (de) * | 2004-03-12 | 2007-03-01 | Infineon Technologies Ag | Verfahren zur Herstellung einer Lochmaske zur lithographischen Strukturierung mittels geladener Teilchen |
JP2006295009A (ja) * | 2005-04-13 | 2006-10-26 | Dainippon Printing Co Ltd | 荷電粒子線用転写マスクの作製方法及び荷電粒子線用転写マスク |
US8881399B2 (en) * | 2006-08-31 | 2014-11-11 | Konica Minolta Holdings, Inc. | Method of manufacturing a nozzle plate for a liquid ejection head |
US10416147B2 (en) * | 2016-03-18 | 2019-09-17 | Hitachi, Ltd. | Method of manufacturing membrane device, membrane device, and nanopore device |
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2001
- 2001-11-16 JP JP2001352014A patent/JP3900901B2/ja not_active Expired - Fee Related
-
2002
- 2002-11-15 DE DE10295694T patent/DE10295694T1/de not_active Withdrawn
- 2002-11-15 KR KR10-2003-7008897A patent/KR20040052454A/ko not_active Application Discontinuation
- 2002-11-15 TW TW091133499A patent/TW591343B/zh not_active IP Right Cessation
- 2002-11-15 WO PCT/JP2002/011939 patent/WO2003043065A1/ja active Application Filing
- 2002-11-15 US US10/250,555 patent/US7022607B2/en not_active Expired - Fee Related
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2005
- 2005-11-23 US US11/284,902 patent/US20060079091A1/en not_active Abandoned
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2006
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Also Published As
Publication number | Publication date |
---|---|
KR20040052454A (ko) | 2004-06-23 |
US20060079091A1 (en) | 2006-04-13 |
US20060269850A1 (en) | 2006-11-30 |
DE10295694T1 (de) | 2003-12-18 |
TW591343B (en) | 2004-06-11 |
US20040045929A1 (en) | 2004-03-11 |
JP3900901B2 (ja) | 2007-04-04 |
US7022607B2 (en) | 2006-04-04 |
JP2003151890A (ja) | 2003-05-23 |
TW200305064A (en) | 2003-10-16 |
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