Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/80—Arrangements for protection of devices protecting against overcurrent or overload, e.g. fuses or shunts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/075—Connecting or disconnecting of bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/931—Shapes of bond pads
  • H10W72/932—Plan-view shape, i.e. in top view
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads
  • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

• the invention relates to a semiconductor component according to the features of the preamble of patent claim 1.
• Integrated circuits are supplied with external supply potentials as well as input signals to be processed and processed output signals are tapped.
• the input signal connections are very sensitive, since the conductor tracks used for feeding lead directly to a gate connection of an input switching stage.
• the human body can thus be electrostatically charged, which charges are then discharged via the outward leads of the semiconductor component containing the integrated circuit.
• Tools from placement machines or test equipment can also be electrostatically charged and discharged via the semiconductor component. With ever smaller structural widths on the semiconductor body carrying the integrated circuit, there is a need for protection against such electrostatic discharges.
• ESD protective elements electrostatic discharge
• the input connection is connected to reference potential (ground) via an ESD protection structure, which essentially has a diode characteristic.
• the ESD protection structure is completely in
• the protective structure is to be dimensioned such that it is to be processed when creating Signal does not switch within the specified specification and attenuates the signal curves as little as possible.
• the diode characteristic must therefore have a high breakdown voltage.
• the diodes used or transistors connected as diodes must be dimensioned over a large area in order to have a correspondingly high current carrying capacity. It is therefore disadvantageous that the ESD protective structures require a high area consumption in the semiconductor body in order to meet the set conditions after high breakdown voltage and high current carrying capacity.
• EP 0 736 904 AI Another semiconductor circuit with protective elements against electrostatic discharges is shown in EP 0 736 904 AI.
• Protective elements are arranged there between a connection pad and conductor tracks running on the semiconductor chip. In sections, the conductor tracks run parallel to the edge of the semiconductor chip. One of the conductor tracks forms a ring running around the semiconductor chip.
• the object of the invention is to provide a semiconductor component in which the area consumption in the semiconductor body is as small as possible, but sufficient ESD protection is nevertheless guaranteed.
• a semiconductor component comprising: a semiconductor body, in which an electronic circuit is arranged, which has a connection for a signal to be processed, to which an input stage or
• Output stage of the electronic circuit is connected, and which has a connection for a supply potential to which the input stage or the output stage is connected, each one of the interconnects assigned to one of the connections, which runs outside the semiconductor body and which is connected to the respectively assigned connection Element for dissipating electrostatic discharges, through which the working signal to the supply potential can be dissipated, in which a further conductor is also provided, which runs outside the semiconductor body and which is connected to the conductor associated with the connection for the supply potential, and in which the element for discharging electrostatic charges on the one hand with the further conductor and on the other hand, is connected to the conductor track assigned to the connection for the signal to be processed.
• the ESD elements are no longer implemented in the semiconductor body.
• an integrated design of ESD protective structures would not consume a negligible amount of space. This area consumption is saved in the semiconductor component according to the invention.
• the ESD protection elements are arranged outside the semiconductor body.
• a further conductor track is provided which leads to supply potential, preferably ground, and is guided past those conductor tracks via which the input or output signals are input or output to the functional units of the semiconductor body.
• the invention is suitable both for discrete-value, digitally operating input and output stages and for continuous-value, analogue input and output stages.
• it is advantageous that the ESD protection element arranged outside the semiconductor body can now be made larger than when it is integrated. This increases the ESD resistance.
• connection pads are provided in the integrated semiconductor chip, i.e. extensive metallizations, which the
• H P CQ pi ⁇ - • ⁇ - ⁇ ; 3 meets Mi CQ ⁇ - ⁇ N «H rt LQ. H K ⁇ H ⁇
• Pi ⁇ - P rt H ⁇ O ⁇ P ⁇ - ⁇ co P ⁇ ⁇ ⁇ * ⁇ P tr ⁇ ⁇ Pi rt rt ⁇ ! Pi PJ tr ⁇ tr ⁇ ⁇ PPH ⁇ - ii PH 0 Pi h- 1 Ü li ⁇ ⁇ ⁇ 0 ⁇ PP )
• the further conductor track can have a short section branching off from its main course direction.
• the section expediently runs in the direction of the semiconductor body or in the opposite direction away from the semiconductor body. This branch serves as a contact surface for the anode of the ESD protection diode.
• An input stage can consist of an inverter.
• the input connection of the inverter is formed by the coupled gate connections of its complementary MOS transistors and is connected to the assigned connection pad.
• the source connection of the n-channel MOS transistor of the inverter is connected to reference potential ground, that is to say it is connected to a signal line in the semiconductor body which leads to the connection pad which is supplied by the conductor track carrying the reference potential, which in turn is connected to the further conductor track crossing the conductor tracks of the lead frame is connected.
• FIG. 1 shows a semiconductor body 1 on which an integrated circuit is arranged.
• a CMOS input switching stage 13 is shown in part of the integrated circuit. It includes two with their drain-source
• the additional conductor track 3 also crosses the conductor tracks 14, 15 of the lead frame that carry the signals DQ1, DQ2.
• ESD elements 32, 33 are provided, which are connected between the conductor track 3 and the relevant one of the conductor tracks 14, 15.
• the anode of a diode 32 is connected to the conductor track 3 at the point 321 and to the conductor track 15 at the point 322.
• the diode 32 serves as an ESD protective element. It has a high breakdown voltage in order not to burden the signal DQ1 within the specification.
• the diode 32 breaks down and is dimensioned sufficiently so that sufficient charge can flow away from the conductor track 15 via the contact points 322, 321 to the conductor track 3 and further via the bonding wire 31 to the ground conductor track 16. This protects the gate oxide on transistor 131 of inverter 13 from a breakdown.
• the ESD protection diode 32 does not take up any area on the semiconductor body. The area consumption would not be negligible, since a high breakdown voltage would have to be achieved with sufficient current carrying capacity.
• the conductor track 14 for the signal DQ2 to be processed is connected to the ring conductor track 3 via another ESD protection diode 33.
• a branch 34 of the conductor track 3 is provided in the vicinity of the point of intersection of the conductor track 14 with the conductor track 3 and runs parallel to the corresponding section of the conductor track 14.
• the branch 34 is directed outwards; alternatively, it can also be directed inwards towards the semiconductor body 1.
• the branch 34 is so far away from the crossing point that the anode of the ESD protective diode contacts the branch 34 and the cathode contacts the conductor track 14.
• the signal DQ1 is one which is incorporated in the circuit on the semiconductor body 1 is to be entered.
• the signal DQ2 is, for example, one which is to be output by the circuit.
• the connecting pad 10 is connected to an output driver of the integrated circuit, for example an output of an inverter or 'a tri-state level. It is also possible that the signals DQ1, DQ2 are bidirectional signals and both serve to supply or tap data or analog signals to the integrated circuit.
• crossing locations of further metal conductor track 3 and signal-carrying conductor tracks 14, 15 are to be designed such that contact between the conductor track 3 carrying ground potential GND and the conductor tracks 14, 15 carrying an input / output signal is prevented. On the one hand, this can be achieved in that the conductor tracks are sufficiently far apart from one another at the crossings. On the other hand, insulation 36, 37 is appropriate. which is arranged between the mutually opposite surfaces of the metallic conductor tracks 3, 15 and 14.

Landscapes

• Semiconductor Integrated Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Priority Applications (5)

Applications Claiming Priority (2)

Related Child Applications (1)

Publications (2)

Family

ID=7671118

Family Applications (1)

Country Status (7)

Families Citing this family (7)

Family Cites Families (11)

• 2001
  • 2001-01-19 DE DE10102354A patent/DE10102354C1/de not_active Expired - Fee Related
• 2002
  • 2002-01-21 JP JP2002558338A patent/JP3886905B2/ja not_active Expired - Fee Related
  • 2002-01-21 WO PCT/DE2002/000175 patent/WO2002058154A2/de not_active Ceased
  • 2002-01-21 KR KR10-2003-7009295A patent/KR100530449B1/ko not_active Expired - Fee Related
  • 2002-01-21 CN CNB028039335A patent/CN1244151C/zh not_active Expired - Fee Related
  • 2002-01-21 EP EP02706607A patent/EP1360726B1/de not_active Expired - Lifetime
  • 2002-01-21 DE DE50211919T patent/DE50211919D1/de not_active Expired - Lifetime
• 2003
  • 2003-07-21 US US10/623,815 patent/US7250659B2/en not_active Expired - Fee Related

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