CN1488171A - 具esd保护之半导体组体 - Google Patents

具esd保护之半导体组体 Download PDF

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CN1488171A
CN1488171A CNA028039335A CN02803933A CN1488171A CN 1488171 A CN1488171 A CN 1488171A CN A028039335 A CNA028039335 A CN A028039335A CN 02803933 A CN02803933 A CN 02803933A CN 1488171 A CN1488171 A CN 1488171A
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M・特鲁斯特
M·特鲁斯特
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Infineon Technologies AG
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Abstract

一种半导体组件，具有ESD保护组件(32，33)，其被设置于半导体基体(1)之外部并连接一额外导体轨迹(3)，承载一参考电位(GDN)，至该连结架构之导体轨迹(14，15)。不再需要集积于半导体基体(1)中之ESD保护结构；可以避免相对应的高区域消耗。

Description

具ESD保护之半导体组件
本发明系关于依据专利范围第1项其特征在于之句子前之特征的半导体组件。
集成电路被提供外部的供应电位以及将被处理的输入讯号以及从其中被摘取之已处理的输出讯号。尤其是，输入讯号端非常的敏感，因为馈入用的导电轨迹直接连接至输入切换级(stage)的闸极端。在集成电路的人工处理或自动化的进一步处理以便将集成电路放置在电路板上并加上焊锡的情况中，存在着敏感的输入级或输出级被静电荷破坏的风险。例如，人体可能充满静电，该等电荷随后经由连接至包含集成电路之半导体组件之外部的端点而被放电。自动组件设置或测试设备也可能具有静电并经由半导体组件放电。以承载集成电路之半导体上之极小的图案线宽度，需要保护以免于静电放电。
美国第5 464 434号专利表示静电放电保护组件之实施例，已知为ESD保护组件(ESD：electrostatic discharge，静电放电)。此输入端经由一ESD保护结构连接至参考电压(地)，其实质上具有二极管特性。此ESD保护结构整个被形成于半导体基体中。此保护结构的尺寸以此方式设定，即当预先描述之规格内的被处理讯号被输入时，其不切换并将讯号波形尽可能衰减至最小因此此二极管特性必须具有一高崩溃电压。另一方面，必须保证在静电放电的情况中，电荷数量被取走至低阻抗的状态的地(ground)。所使用之二极管或被连接为二极管的晶体管必须具有大表面区域上的尺寸以便具有相对的高电流乘载能力。因此其缺点在于ESD保护结构需要半导体基体中高的区域消耗以便符合高崩溃电压及高电流承载能力之边界情况。
另一种具有防静电之保护组件之半导体电路表示于EP 0 736 904A1专利中。其中，保护组件被设置于一端点焊点与分布于半导体芯片上之导体轨迹之间。导体轨迹之特定部份与半导体芯片之边缘平行。一个导体轨迹形成环绕半导体芯片之一个环。
本发明之一目的在提供一种半导体组件，其于半导体基体中的区域消耗尽可能地小，但适当地确保ESD保护。
此目的藉由一半导体组件而达成，包括一半导体基体，于其中设置具有被处理之讯号用之一端点的电子电路且该电子电路之一输入级或一输出级连接至该端点，且其具有用以提供一电位之一端点且该电子电路之一输入级或一输出级连接至该端点，在每一情况中被指派给该等端点之一之一导体轨迹从该半导体基体流出并连接至个别指派的端点，一取走静电放电之组件，藉由该组件，施加在将被处理之讯号用之端点上之静电放电可被移动至供应电位，于该情况中更提供另一导体轨迹，其走向该半导体基体之外并被连接至指派给该供应电位之端点，且其中取走静电电荷之该组件被设置于该半导体基体之外部，且每一者一方面在半导体基体外部连接至该另一导体轨迹，另一方面连接至指派给将被处理之讯号用之端点的导体轨迹。
依据本发明之半导体组件，ESD组件不再被形成于半导体基体中。如以上所述，ESD保护结构之积体配置拿取非微不足道数量的表面区域。此区域消耗在本发明之半导体组件中是节省的。取而代之，此ESD保护组件被设置于半导体基体之外。此外，提供额外的导体轨迹，其承载供应电位，较好是地电位，并且穿过那些用以让输入或输出讯号从半导体基体之功能单元输入或从其输出讯号之导体轨迹。本发明适合在以数字为基础运作之不连续数值输入及输出级，以及以模拟为基础运作之连续输入及输出级。此外，设置于半导体外部之该ESD保护组件现在可以做得比积体配制情况中大。因此增加ESD电阻。
在积体半导体芯片上所提供的称为端点焊点，亦即代表集成电路之输入或输出端点。在半导体基体外部之金属导体轨迹承载供应电位及进入及离开的被处理讯号。这些导体轨迹也被称为引线架构(leadframe)。指派给半导体基体的引线架构之导体轨迹的端点随后藉由连接线(bonding wire)与端点焊点接触。引线架构之导体轨迹之相对端点是半导体组件之端点接脚(pin)，并且被焊接于一电路板上或插入一插槽。此半导体基体被一封装包围，通常由塑料制成，引线架构之导体轨迹被导引至外部以便建立与电路板的接触。
依据本发明额外提供的另一导体轨迹包围该半导体基体。该半导体基体通常被做成矩形。另一导体轨迹之至少一部份随后平行于半导体基体之边缘行走。其藉此跨越从端点焊点连接至外部之引线架构之导电轨迹经过该封装，用于将被处理的讯号以及用于供应电位。
依据本发明，承载供应电位(地)之引线架构之一导体轨迹与包围该半导体基体之导体轨迹之间的连接最好由一打线(bonding)连接所建立。承载地电位的额外导体轨迹经由ESD保护组件在交叉点连接至一承载将被处理之讯号之引线架构的导体轨迹。此ESD保护组件最好是一个二极管，其阳极连接至该额外导体轨迹，而其阴极连接到承载将被处理之讯号的导体轨迹。取代pn二极管，也可使用MOS二极管。于此情况中其为一MOS场效晶体管，其源极与门极端互相连接。
在该承载地电位之另一导体轨迹与承载将被处理之讯号的导体轨迹之交叉点提供隔离，因此此二导体轨迹互相被电性隔离，并且避免引线架构之讯号承载导电轨迹与该另一导电轨迹之间的短路。
在交叉点的附近，该另一导电轨迹可以具有一远离其主要行进方向的短部份分支。该部份适当地在朝向半导体基体的方向前进或在远离半导体基体的方向行进。此分支被当成ESD保护二极管之阳极用的接触区域。
在半导体基体中，例如硅基板，功能单元被设计为双极性(bipolar)，MOS或CMOS电路。输入级可能包括一反相器。反相器之输入端可以由耦合其互补MOS晶体管之闸极端而形成并被连接至指派的端点焊点。反相器之n信道MOS晶体管之源极端被连接至参考电位地，参考电位地被连接至半导体基体内之一讯号线，该讯号线连接至由承载参考电位之导体轨迹所供应之端点，该导体轨迹之一部份接着跨越引线架构之导体轨迹被连接至该另一导体轨迹。
本发明将基于表现于图式中的实施例被详细解释如下。图式表示一半导体基体1，于其上设至一集成电路。代表从集成电路之引出部的是一个CMOS输入切换级13。其包括汲-源极串连之二互补MOS晶体管131，132。p信道MOS晶体管132被提供正供应电位VINT，n信道MOS晶体管131被提供参考电位GND。参考电位GND穿过线121分布于半导体芯片上。所有的讯号及供应电位经由端点焊点10，11，12被供应给半导体基体。此等端点焊点是金属化区域。端点焊点10，11分别被当成资料讯号DQ2及DQ1之输入及输出。端点焊点12是做为地电位GND的馈入。此半导体芯片被密封于封装2之内。讯号流量及至外部之供应电压的馈送经由金属导体轨迹14，15，16发生。这些导体轨迹在芯片侧之其端点分别经由连接线17，18，19连接至被指派的端点焊点10，11，12。其从半导体芯片1离开并经过封装2。封装外部之金属导体轨迹14，15，16端点被插入，异如插槽内，或被焊接于电路板上。金属导体轨迹14，15，16被群组一起形成一引线架构，其外部端互相连接。此输入于封装2之密封之后被打断。
依据本发明，提供另一金属导体轨迹3。类似引线架构之导体轨迹14，15，16，导体轨迹3在半导体基体1外测行进。对照引线架构之导体轨迹14，15，16，导体轨迹3并未从芯片离开，而是平行于半导体基体1之侧边。导体轨迹3适当地环绕分别平行半导体基体1之侧边，如同一封闭的环。另一导体轨迹3承载地点位GND。为此目的，导体轨迹3藉由连接线31连接于引线架构之地导体轨迹16的交叉点。或者是，也可使用用以互相连接线16，3的互相相对的表面的其它连接，例如藉由一导电黏胶。地电压GND经由包围半导体芯片1之线3提供。
额外的导体轨迹3也跨越承载讯号DQ1，DQ2之引线架构之导体轨迹14，15在交叉位置所提供的是ESD组件32，33，其被连接于该导体轨迹3与相关的导体轨迹14，15之一。例如，二极管32的阳极在点321连接至导体轨迹3，并在点321连接至导体轨迹15。二极管32被当成一ESD保护组件其具有一高崩溃电压以便不影响规格内之讯号DQ1的负载。然而，在高静电电压的情况中，二极管32崩溃且具有必要电荷用之足够的额定(rating)以便能够经由接触点322，321从导体轨迹15流动至导电轨迹3并进一步经由连接线31流至地导体轨迹16。因此，反相器13的晶体管的闸氧化物被保护免于崩溃。与设置于半导体基体上之ESD保护结构相较之下，其为地电位GND必须被设置于输入线131与线121之间，ESD保护二极管32不需要占用半导体基体上的任何区域。区域消耗是微不足道的因为将达成高崩溃电压以及适合的电流承载能力。
将被处理之讯号DQ2用之导体轨迹14经由另一ESD保护二极管33被连接至环导体轨迹3。在导体轨迹14与导体轨迹3之交叉点附近提供导电轨迹3之一分支，其与导电轨迹14之对应部份平行。在所示之实施例中，分支34被导引至外部；其也可以被导引至朝向半导体基体1之内部。分支34如此远离交叉点，ESD保护二极管之阳极接触分支34而其阴极接触导体轨迹14。
在所示的实施例中，讯号DQ1将被输入半导体基体1上之电路。讯号DQ2是，例如，来自电路之输出。于此情况中，端点焊点10被连接至集成电路之输出驱动器，例如反相器或三态级(tristate)之输出。讯号DQ1及DQ2也有可能是双向讯号并被用来输入资料或模拟讯号至集成电路内或从其中取出。
另一金属导体轨迹3及讯号承载导体轨迹14，15被配置为避免承载地电位GND之导体轨迹3与承载输入/输出讯号之导电轨迹14，15之间的接触。一方面，这可藉由导体轨迹在交叉口互相分离而达成。另一方面，设置于金属导体轨迹3，15，14之相对表面之间的隔离36，37也是适合的。
在藉由联机17，18，19之金属导体轨迹14，15，16至端点焊点10，11，12的打线之后，经由联机31的导体轨迹3，16的连接以及ESD保护组件32，33的接触，所有导体轨迹被固定，因此引线架构之导体轨迹在外部端点的连接可由打孔被移除。
因为区域限制不需要被施加至保护组件32，33，它们的尺寸可被设计为较高电流承载能力，与积体形式情况相较下。因此，与半导体基体上的形式相较可以增加ESD电阻。
参考标号表
1                         半导体基体
2                         封装
3                         导体轨迹
10，11，12                端点焊点
121                       线
13                        输入级
131，132                  晶体管
133                       输入
14，15，16                导体轨迹
17，18，19，31            连接线
32，33                    ESD保护组件
321                       阳极端
322                       阴极端
34                        导体轨迹分支
35                        交叉
36，37                    隔离
DQ1，DQ2                  将被处理的处讯号
GND                       供应电位
VINT                      供应电位

Claims (10)

1.一种半导体组件，包括
一半导体基体(1)，于其中设置具有被处理之讯号(DQ1)用之一端点(11)的电子电路(13)且该电子电路之一输入级或一输出级(13)连接至该端点，并具有一供应电位GND用之一端点(12)，且该输入级(13)或输出级连接至该端点，
在每一情况中被指派给该端点(11，12)之一之一导体轨迹(15，16)行进至该半导体基体(1)外部并连接至个别指派的端点(11，12)，
一组件(32)用以取走静电放电，藉由该组件使将被处理的讯号(DQ1)可被取走至供应电位(GND)，
特征在于
提供另一导体轨迹(3)，其走向该半导体基体(1)之外部并被连接至指派给该供应电位之端点(12)之导体轨迹(16)，且其中
用以取走静电电荷之该组件(32)被设置于该半导体基体(1)之外部，且每一者一方面在半导体基体(1)外部连接至该另一导体轨迹(3)，另一方面连接至指派给将被处理之讯号(dq1)用之端点(11)的导体轨迹(15)。
2.如申专利范围第1项之半导体组件，特征在于一封装(2)，其包围该半导体基体(1)及该另一导体轨迹(3)，且其部份包围被指派给端点(11，12)之导体轨迹(15，16)，因此面向该半导体基体(1)之这些导体轨迹(15，16)之一部份行进至该封装(2)内部，而面离该半导体基体(1)之一部份行进至该封装(2)之外部。
3.如申专利范围第1或2项之半导体组件，特征在于取走静电放电之组件(32)系一二极管，其阳极连接至该另一导体轨迹(3)，而其阴极连接至指派给该将被处理之讯号(DQ1)用之该端点(11)之导体轨迹(15)。
4.如申专利范围第1至3项任一项之半导体组件，特征在于该另一导体轨迹(3)包围该半导体基体(1)，且其中指派给该端点(10，11，12)之导体轨迹(14，15，16)与该另一导体轨迹交叉。
5.如申专利范围第4项之半导体组件，特征在于，在该另一导体轨迹(3)与被指派给该将被处理之讯号(DQ1)用之该端点(11)之导体轨迹(15)交叉的位置，一隔离(36)被提供于交叉导体轨迹(3，15)之间。
6.如申请专利范围第1-5项任一项之半导体组件，特征在于该另一导体轨迹(3)在其与指派给将被处理之讯号(DQ1)用之端点(10)用之导体轨迹(14)交叉之位置附近具有一导体轨迹部份(34)从其主要行进方向向外分叉，至该分叉连接用以取走静电放电之该组件(33)，其另一方面被连接至该交叉的导体轨迹(15)。
7.如申请专利范围第1-6项任一项之半导体组件，特征在于用以将该导体轨迹(14，15，16)指派给该端点(10，11，12)之连接线(17，18，19)被连接至个别的端点(10，11，12)。
8.如申请专利范围第7项之半导体组件，特征在于将被处理之讯号(DQ1，DQ2)用之该端点(10，11，12)以及该供应电位(GND)被设置为该半导体基体(1)中之金属化区域。
9.如申请专利范围第1-7项任一项之半导体组件，特征在于该输入级(13)具有至少一晶体管(131，132)，其闸极连接至将被处理之讯号(DQ1)之端点(11)，而其汲极及源极连接至该供应电位(GND)用之端点。
10.如申请专利范围第9项之半导体组件，特征在于该输入级(13)系一反相器。
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