WO2001045256A1 - Filtre numerique acyclique et radio-recepteur equipe de ce filtre - Google Patents
Filtre numerique acyclique et radio-recepteur equipe de ce filtre Download PDFInfo
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- WO2001045256A1 WO2001045256A1 PCT/JP2000/008980 JP0008980W WO0145256A1 WO 2001045256 A1 WO2001045256 A1 WO 2001045256A1 JP 0008980 W JP0008980 W JP 0008980W WO 0145256 A1 WO0145256 A1 WO 0145256A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/709—Correlator structure
- H04B1/7093—Matched filter type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
Definitions
- the present invention relates to a non-recursive digital filter using a shift register such as a matched filter used for cell synchronization acquisition and demodulation synchronization acquisition in a spread spectrum communication system or a CDMA communication system, and using the same.
- a shift register such as a matched filter used for cell synchronization acquisition and demodulation synchronization acquisition in a spread spectrum communication system or a CDMA communication system
- a matched filter constituting a non-recursive digital filter used in the conventional CDMA system for example, a matched filter described in Japanese Patent Application Laid-Open No. 10-178386 is known.
- the received signal demodulated by the reception demodulation unit is received by the antenna after receiving the packet which is spread modulated by the spread code and transmitted, and is in the state of being spread modulated by the spread code.
- the signal is supplied at the matched fill evening.
- This multi-filtration is performed by, for example, a shift register having a 64-bit configuration in which a received signal is input and shifting, a register configuration for setting a spreading code sequence having the same bit configuration as the shift-register configuration, and a shift configuration.
- a multiplier that multiplies the bits between the register and the register, and an adder that adds the output signal of the multiplier. It is sampled at the chip period of the spread code, for example, and converted into a digital value between 11.0 and 101.0 by AD conversion.
- the shift register shifts the received signal every one chip cycle according to the sampling cycle of the received signal.
- the received signal is oversampled, that is, sampled at a period shorter than one chip period of the spreading code and subjected to A / D conversion, and the shift register shifts the received signal in accordance with the sampling period. Is generally raised.
- the present invention has been made by focusing on the unsolved problems of the above conventional example, and provides a non-recursive digital filter capable of saving power and a radio receiving device using the same. It is intended to be.
- a non-recursive digital filter includes an n-stage shift register that sequentially shifts a predetermined number of n-bit input data;
- the n-stage shift register is divided into a plurality of shift registers.
- the shift register is characterized in that it is driven in a time-division manner in synchronization with the input data.
- the divided shift registers are time-divisionally shifted in synchronization with the input data, high-speed switching of the shift registers can be eased.
- the shift register is composed of n stages, the clock rate of the shift clock can be shortened to save power.
- the acyclic digital filter according to claim 2 includes an n-stage shift register that sequentially shifts a predetermined number of n-bit input data, and an output of each output stage of the shift register.
- the n-stage shift register is provided with n / 2 stages of first and second shift registers, respectively.
- the first and second shift registers are shifted at the rising edge of the shift register, and the other shift operation is performed at the falling edge of the shift register.
- the n-stage shift register is divided into half stages of shift registers, one of which stores the odd number of the spread code sequence at the rising edge of the shift clock and shifts the shift register.
- the shift register operates at the falling edge of the shift clock and performs the shift operation by storing the even-numbered sequence of the spread code sequence, thereby halving the clock rate of the shift clock when the shift register is composed of n stages. Power savings can be achieved.
- the non-recursive digital filter according to claim 3 includes an n-stage shift register for sequentially shifting a predetermined number of n bits of input data, and a filter for an output of each output stage of the shift register.
- the n-stage shift register is divided into n / 2 stages each of which receives a spread code sequence and a shift clock.
- first multiplication means for multiplying the output of each stage of the first shift register by the output of the first selection means; and each stage of the second shift register.
- Output and the A second multiplying means for multiplying an output of the second selecting means, and a correlation strength calculating means for adding a multiplication result of the first multiplying means and the second multiplying means to output a correlation strength
- the first and second shift registers are configured such that one of them performs a shift operation at the rising edge of the shift clock, and the other performs a shift operation at the falling edge of the shift clock.
- the first and second selecting means are configured such that one of the first and second multiplying circuits sets the even-numbered stage of the reference code register to the first multiplying device and the other sets the odd-numbered stage to the second multiplying stage.
- the invention according to claim 3 has a multi-filter configuration. For example, the first shift register sequentially shifts an odd-numbered code sequence input to the first shift register at the rising edge of the shift clock.
- the even-numbered code sequence is sequentially shifted at the falling edge of the shift clock.
- an even number of the reference code register is used as the first multiplication means by the first selection means
- an odd number stage of the reference code register is used by the second selection means in the second selection means.
- the first selecting means outputs the odd-numbered stages of the reference code register to the first multiplying means
- the second selecting means outputs the reference code.
- the even stage of the register is output to the second multiplication means.
- the correlation output is output by multiplying the output and the result of the multiplication by the correlation strength calculation means.
- the non-recursive digital filter according to claim 4 is the invention according to claim 3, wherein the first and second selecting means are provided for every two stages of the reference code register.
- the first and second multiplying means are constituted by an exclusive OR circuit, and the correlation strength calculating means is constituted by an adding circuit. .
- each of the multiple breakers is referred to by a reference numeral in accordance with the ON / OFF state of the shift clock.
- a switching operation for alternately selecting the odd-numbered stages and the plurality of stages is performed, and the reference code is output to the exclusive OR circuit to which the output of each stage in the first and second shift registers is input, so that the shift clock
- the correlation output of an 8-bit code sequence can be obtained with the four pulses.
- the wireless receiving device is a wireless receiving device adopting a CDMA system that performs an operation including maintaining a path synchronization by receiving a spectrum spread signal from a base station.
- An RF receiver that converts the received signal to a base-span signal, and holds the input digital signal and uses the spreading code as a reference.
- a correlation section that performs inverse spectrum transform while taking these correlations and outputs received data, and a spanned demodulation section that demodulates the received data.
- an input side of one of a baseband demodulation unit and the other side connected to the RF reception unit, and the correlation unit is connected to the output side of the RF reception unit according to any one of claims 1 to 4. It is characterized by having a matched filter consisting of the described acyclic digital filter.
- the base span signal output from the RF receiving section is subjected to spectrum despreading in the inter-phase section, and the received data is demodulated by the base span demodulating section.
- the baseband signal output from the RF receiving unit is demodulated by the baseband demodulating unit, and then the spectrum is despread by the correlating unit to receive the data of the CDMA system.
- a matched filter comprising the non-recursive digital filter according to any one of the above items 4 to 4.
- the wireless receiving device according to claim 6 is a spread spectrum communication device that forms a wireless access local area network with another wireless communication terminal to directly spread information data.
- an RF receiving unit that converts received information data into a base-span signal, an input digital signal is held, and a spreading code is held as a reference code.
- An inter-phase unit that performs inverse spectrum transform while outputting these phases to output received data, a baseband demodulation unit that demodulates received data, and a packet that performs bucket processing based on the received data.
- a packet processing unit wherein one of the input sides of the inter-phase unit and the baseband demodulation unit is connected to the RF receiving unit, the other is connected to the output side, and the packet processing is performed on the output side.
- the phase between unit is in that it has a matched filter consisting of acyclic side digital fill evening according to any one of claims paragraphs 1 through 4, wherein the feature.
- the baseband demodulation unit demodulates the received data obtained by performing the spectrum despreading on the base span signal output from the RF reception unit in the inter-phase unit, or
- the baseband signal output from the RF receiver is demodulated by the baseband demodulator and then despread by the correlator.
- the correlator includes a matched filter configured by a non-recursive digital filter according to any one of claims 1 to 4 for performing data reception of a single-port-area network.
- FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a CDMA communication system.
- FIG. 2 is a block diagram showing a matched filter constituting a non-recursive digital filter according to the present invention. Is a time chart for explaining the operation of the matched filter,
- FIG. 4 is a block diagram showing a modification of FIG. 1, and
- FIG. 5 is an embodiment in which the present invention is applied to a wireless receiver for a wireless local area network.
- bEST mODE fOR CARRYING OUT tHE c invention illustrates
- FIG. 1 is a schematic configuration diagram showing an example of the case where the present invention is applied to a CDMA (C 0 de Division Multiple Access) communication system.
- CDMA Code Division Multiple Access
- a wireless transmitter 10 transmission data and a code generator 1 are used. Is multiplied by a multiplier 2 with a predetermined number n-bit spreading code C (t) generated in the above to form a spread data, and this spread data is converted into an analog signal by a D / A converter 3, This is modulated by the modulator 4, amplified by the transmission amplifier 5, and transmitted from the transmission antenna 6.
- the wireless receiver 20 when the spread antenna is received by the receiving antenna 11, the RF amplifier 12 performs RF amplification, and then demodulates by the demodulation unit 13, and the A / D converter 14 The signal is converted into a signal to be used for despreading, and this is input to the correlation unit 19.
- the correlator 19 supplies the despreading digital data output from the A / D converter 14 to the matched filter 15 as a non-recursive digital filter, and The sum of products (correlation output) is obtained and supplied to a peak detector 16 to obtain a synchronization acquisition signal.
- the synchronization acquisition signal is supplied to a despreading code generator 17 to obtain a despreading code C (t). Then, the despread code C (t) is multiplied by the despread data output from the A / D converter 14 by the multiplier 17 to obtain the same received data as the transmitted data. Play data.
- the matched filter 15 receives the odd-numbered bits of the spreading code string and performs four D-shift operations.
- Type flip-flops DF11 to DF14 are connected in series, and similarly, four D-type probe DFs that perform shift operation by inputting an even number of despreading data
- a second shift register 22 in which 21 to DF 24 are connected in series is connected in parallel, and a reference code register 23 storing an 8-bit despreading code is provided.
- the reference code register 23 is connected to four multiplexers MP11 to MP14 that constitute a first selection means on one output side, and constitutes a second selection means on the other output side.
- the four multiplexers MP21 to MP24 are connected.
- the outputs of the multiplexers MP 11 to 1 14 and the outputs of the 13-type free flops 0 F 11 to DF 14 form exclusive OR circuits E 01 1 to E 14 constituting the first multiplication means.
- the exclusive-OR circuits E 02 1 to E ⁇ 24 which are input and output from the multiplexers MP 21 to MP 24 and the outputs of the D-type flip-flops DF 21 to DF 24 constitute the second multiplication means.
- the outputs of these exclusive OR circuits E 01 1 to E 01 4 and E 02 1 to E 024 are input to the adder 25, and the adder 25 slightly shifts from the rising and falling points of the shift clock CK.
- the outputs of the exclusive OR circuits E ⁇ 1 to ⁇ 14 and EO21 to ⁇ 24 are added to calculate the correlation strength, which is output to the peak detector 16 as the correlation strength output.
- the first shift register 21 and the second shift register 22 receive a shift clock CK corresponding to one cycle corresponding to two bits of the reception data, and this shift clock
- each D-type flip-flop DF11 1 to DF14 of the first shift register 21 shifts and turns off from the shift clock CK on.
- each D-type flip-flop DF21 to DF24 of the second shift register 22 shifts.
- the shift clock CK is also provided to each of the multiplexers MP11 to MP14.
- the shift clock CK is on, the output of the even-numbered stage of reference register 23 is selected, and when the shift clock CK is off, the output of the odd-numbered stage of reference register 23 is selected.
- Exclusive OR circuit EO 11 Outputs to 1 to ⁇ 14.
- the shift clock CK is also input to each of the multiplexers MP21 to MP24.
- the shift clock CK is on, the output of the odd-numbered stage of the reference code register 23 is selected, and the shift clock CK is turned off. At some point, the output of the even-numbered stage of the reference code register 23 is selected and output to the exclusive OR circuits E 021 to E 024.
- the transmission data D1 and the transmission data D1 and the transmission data D8, which are represented by 8-bit spreading codes C (t), respectively, represent "1" and "0" data, respectively. It is assumed that D2 is transmitted to the receiving side in the order of the rightmost bits D11 to D12, D13, ....
- the transmission data D 1 and D 2 are received by the reception antenna 11, RF amplification is performed by the RF amplifier 12, and then demodulated by the demodulation unit 13, which is then A / D converter 1
- the data is supplied to the matched filter 15 of the correlator 19 as despreading data.
- the correlation calculation is performed and the correlation strength output is output to the beak detector 16.
- the peak detector detects the maximum and minimum peaks of the correlation intensity output, generates a corresponding synchronization acquisition signal TS, and supplies this to the despreading code generator 17.
- the despreading code generator 17 generates a despreading code sequence C (t) in synchronization with the synchronization acquisition signal TS, and supplies this to the multiplier 18.
- the received data which is the same as the transmitted data is reproduced by multiplying the received data by the despreading code sequence C (t).
- the reference symbols C 23, C 8, C 6, C 6, C 6, It is assumed that the value “000 1 1 1 0 1” of C 5, C 4, C 3, C 2, and C 1 is stored.
- the despreading data shown in FIG. 3 (a) is input, the black background appears at the rising edge of the shift clock CK shown in FIG. 3 (b) which is input in synchronization with the despreading data.
- the odd-numbered data D11, D13 to ... represented by white numbers are sequentially stored in the first shift register 21, and the falling edge of the shift clock CK is At this time, the even-numbered data D 12, D 14,... Are sequentially stored in the second shift register 22.
- the multiplexers MP11 to MP14 output the odd-numbered codes C7, C5, C3, and C1 of the reference code register 23, "0111". And the value of the code C 8, C 6, C 4, C 2 in the even number of the reference code register 23 when it is in the on state is selected, and the multiplexer MP 21 1 to MP is selected.
- Reference numeral 24 denotes a reference code when the shift clock CK is in the off state.When the value of the code C 8, C 6, C 4, and C 2 in the even-numbered register ⁇ 00 1 0 '' is selected, and when the shift clock CK is in the on state, Then, the value “0 1 1 1” of the code C 7, C 5, C 3, C l in the odd-numbered reference code register 23 is selected.
- the first 8-bit despreading data D 1 “0 00 1 1 1 0 1” shown in FIG. 3 (a) is generated at both the rising and falling edges of the shift clock CK.
- the shift register 21 and the second shift register 22 of the odd-numbered bit data D15, D13, and D11 are alternately input to the shift register 21 and the second shift register 22 as shown in FIG. 3 (c).
- 1 1 1 1 '' are stored in the D-type flip-flops DF 11 1, DF 12 and DF 13 of the first shift register 21, respectively, and at time t 0, the shift clock CK is
- the data is stored in the flip-flops DF11 to DF13 until then.
- the data of “1 1 1” was shifted to DF12 to DF14, respectively, and the D-type drive of the first shift register 21 was changed.
- the values of the odd-numbered data D17, D15, D13, and D11 in the flops DF11, DF12, DF13, and DF14 are "0 1 1 1”. Is stored.
- the values “0 10” of the even-numbered first three data D 16, D 14 and D 12 are set to the D-type flip-flops DF 21, DF 22 and DF 23 of the second shift register 22.
- the shift clock CK falls at the time t1
- the value "0" of the even-numbered last data D18 is changed to the D-type flip-flop port.
- the data “0 10” stored in the slave DFs 21 to D 23 is shifted to the slave DFs DF 22 to DF 24, respectively.
- the D-type flip-flops DF21, DF22, DF23 and DF24 of the register 22 have even-numbered data D18, D16, D14 and D12 as shown in Figure 3 (c).
- the value “00 1 0” is stored.
- the shift clock CK is in the OFF state, so that the multiplexers MP11, MP12, MP13, and MP14 as the first selection means Since the odd-numbered output of the reference code register 23 is selected, the odd-numbered output of the reference code C is obtained from these multiplexers MP11, MP12, MP13, and MP14 as shown in FIG. 3 (c). The values of C 7, C 5, C 3 and CI of “0 1 1 1” are output. Similarly, the multiplexers MP 21, MP 22, MP 23 and MP 24 as the second selecting means Since the even-numbered output of the reference code register 23 is selected, the even-numbered code C of the reference code C is obtained from these multiplexers MP 21, MP 22, MP 23 and MP 24 as shown in FIG. The value “00 1 0” of 8, C 6, C 4 and C 2 is output.
- the data stored in the first and second shift registers 21 and 22 are, as shown in the first row on the right side in FIG.
- the reference symbols selected by the multiplexers MP11 to MP14 and MP21 to MP24 are also the reference symbols shown in the second stage on the right side in FIG.
- a shift operation equivalent to the case where eight D-type flip-flops are connected in series is performed.
- the exclusive OR circuits E 01 1 to E ⁇ 14 have the same input and output, so that the outputs are all low level and the other exclusive OR circuits E ⁇ 21 to E ⁇ 14 24 also has the same input data, all become low-level outputs, and the correlation strength output calculated by the adder 25 becomes the lowest level ⁇ 0 '', which is supplied to the peak detector 16.
- the peak detector 16 determines that the peak value is the minimum peak value, and supplies a pulse-like synchronization capture signal TS to the despreading code generator 17 so that the despreading code sequence C (t) is Output is started.
- multiplexers MP11, MP12, MP13, and MP14 as the first selection means are provided.
- the multiplexers MP11, MP12, MP13, and MP14 output the even-numbered code C of the reference code C as shown in FIG. 3 (d).
- C 6, C 4, and C 2 are output as ⁇ 00 10 '', and conversely, from the multiplexers MP 21, MP 22, MP 23, and MP 24 as the second selection means, FIG.
- the value “0 1 1 1” of the codes C 7, C 5, C 3 and C 1 in the odd-numbered reference code C is output.
- the contents of the first shift register become even-numbered data when the shift is performed in the same manner as in the conventional example, and the second shift register becomes The contents of the register become odd-numbered data, and the reference code is changed accordingly.
- the same shift operation as when eight D-type flip-flops are connected in series as before is performed. Will be.
- a low-level output is obtained from the exclusive OR circuit E011-E013, a high-level output is obtained from E014, and a low-level output is obtained from E021, EO23, E ⁇ 22, Since a high-level output is obtained from E024, the correlation strength output from the adder 25 becomes "3", and the peak detection unit 16 determines that it is not the peak value, and the synchronization acquisition signal TS Is stopped.
- the first even-numbered data D22 in the despread data D2 is stored in the second shift register 22.
- the content is updated to “1001” by the shift operation, and the first shift register 21 does not perform the shift operation. Hold “00 1 1” as shown.
- the values “0 1 1 1” of the codes C 7, C 5, C 3 and C 1 in the odd-numbered reference code C are output from the multiplexers MP 11 to MP 14.
- the multiplexers MP 21 to MP 24 output the values “00 1 0” of the codes C 8, C 6, C 4 and C 2 in the even-numbered reference code C as shown in FIG. 3 (e).
- the shift operation is equivalent to an eight-stage shift operation.
- the outputs of the exclusive OR circuits EOil, E013, E014, and E022 go low, and the outputs of the remaining E012, E021, E023, and EO24 go high.
- the correlation strength output of “4” is obtained from the adder 25, which is supplied to the peak detector 16 but is determined not to be a beak value, and the output stop state of the synchronization acquisition signal TS is continued.
- the odd-numbered data D23 of the despreading data D2 becomes the first data D2 in accordance with the rising and falling edges of the shift clock CK.
- the even shift data D 24 is in the second shift register 22
- the even shift data D 25 is in the first shift register 21
- the even shift data D 25 is in the first shift register 21.
- 26 are stored in the second shift register 22 and the correlation strength outputs are "5", "4", "3", "4", and "5", respectively. It is determined that the value is not the lock value, and the output stop state of the synchronization acquisition signal TS is continued.
- the value “1” of the last even-numbered data D28 in the despreading data D2 is stored in the flip-flop DF21 of the second shift register 22.
- the content of the first shift register 21 is maintained at "1 000".
- the storage data of the first shift register 21 is odd-numbered data when the shift register is composed of eight stages of shift registers.
- the data stored in the second shift register 22 becomes even-numbered data.
- the multiplexer M Select the value “0 1 1 1” of the code C 7, C 5, C 3, and C 1 in the odd-numbered reference code C of the reference code register 23 in P 11 to MP 14, and select the multiplexer MP 21 1 to MP 24 ,
- the values “00 1 0” of the codes C 8, C 6, C4 and C 2 in the even-numbered reference code C are selected, so that the exclusive OR circuits E 01 1 to E ⁇ 14 and E02 1 To E024 are high level, and the correlation strength output calculated by the adder 25 is “8”, which is supplied to the beak detector 16, so that the maximum peak value in the beak detector 16 And a pulse-like synchronization capture signal TS is output.
- the despreading code sequence C (t) is output again from the despreading code generator 17, and the next despreading is performed by the multiplier 18.
- the received data identical to the transmitted data is reproduced by multiplying the received data D3.
- the shift register is divided into the first shift register 21 and the second shift register 22, which are half the number of bits of the spreading code, and are connected in parallel. One of them is operated at the rising edge of the shift clock CK, the other is operated at the falling edge of the shift clock CK, and the multiplexers MP11 to MP14 and MP21 to MP24 are shifted.
- the odd-numbered and even-numbered reference codes stored in the reference code register 23 are selected according to the ON / OFF state of the clock CK, and the output of each stage of each shift register and the multiplexers MP11 to MP14 and MP 21
- the outputs of MP1 to MP24 are supplied to exclusive OR circuits E011 to E014 and E021 to E024 to obtain a high-level output when they do not match, and these are added by an adder 25.
- To obtain the correlation strength output Therefore, when reproducing the 8-bit despread data, only four shift pulses CK are required and only four D-type flip-flops pass through one bit.
- the number of pulses and the number of passing flip-flops are eight half that of the eight, so the shift clock CK clock rate can be reduced by half, and significant power savings can be achieved.
- switching operations are newly performed in the multiplexers MP11 to MP14 and MP21 to MP24, but since the reference code is one bit, the number of switching operations in the multi-bit shift register is reduced. The effect is much greater. Therefore, we used matched fills 1-5 The power consumption of the entire wireless receiver 20 can be reduced, and the life of the built-in battery can be extended.
- the spreading code is 8 bits.
- the present invention is not limited to this, and can be set to any number of bits.
- the reference code corresponding to the despreading data D1 is stored in the reference code register 23 .
- the present invention is not limited to this. Even the reference code corresponding to D2 may be stored, and furthermore, the reference code in which the odd-numbered data and the even-numbered data of the despreading data are exchanged may be used.
- the selection according to the shift clocks CK of MP 14 and MP 21 to MP 2 may be reversed in the above embodiment.
- two reference code registers storing the odd-numbered and even-numbered reference codes corresponding to the despreading data D1 or D2, and these are selected by a multiplexer to obtain exclusive OR.
- the signals may be supplied to the circuits E 011 to E 014 and E 021 to E 024.
- the number of divisions of the shift register is not limited to two as in the above embodiment, but may be an arbitrary number of divisions such as three divisions, four divisions, and the like.
- the range of the number of selected bits may be increased.
- the radio receiver 20 demodulates the basic signal output from the RF amplifier 12 by the demodulator 13 and converts the demodulated signal into the digital signal by the A / D converter 14.
- the digital signal is converted to a digital signal, and supplied to a correlator 19 having a matrix filter 15 shown in FIG. 2 to perform spectrum despreading, and then demodulated by a baseband demodulator 21 for processing.
- the CDMA telephone receiver 22 may be configured by supplying the signal to the circuit 22.
- the present invention is not limited to this, and an n-stage shift register It can be applied to a non-recursive digital filter in which the output of each output stage is multiplied by a filter coefficient and added.
- the present invention is not limited to this, and as shown in FIG. 5, direct spreading (DS: Direct Sequence)
- the present invention can be applied to a wireless receiving device 30 for a wireless local area network employing a spread spectrum (SS: Spectrum Spectrum) method that performs Direct Spread). That is, the wireless receiving device 30 converts the signal received by the wireless antenna 11 by the RF amplifier 12 into a digitized signal by the A / D converter 14, which is shown in FIG.
- Spectral despreading is performed by the correlator 19 having the matched filter 15, demodulation is performed by the baseband demodulator 31, and data is extracted from the received packet by the packet processor 32, and
- the portable information terminals 33 must be supplied with the necessary power to the wireless receivers 30. It is configured.
- the power saving can be achieved by the matched filter 15 of the correlator 19, so that the power saving of the entire wireless receiving device 30 can be achieved, and the portable type device to which the wireless receiving device 30 is connected is connected.
- the life of the built-in battery of the information terminal 33 can be extended.
- the connection order of the A / D converter 14 and the correlation unit 19 and the connection order of the baseband demodulation unit 31 may be exchanged.
- the present invention can be applied to other wireless receivers using spread codes. Industrial applicability
- each of the divided shift registers is time-divisionally shifted in synchronization with the input data, high-speed switching of the shift register is performed.
- the shift rate can be reduced, and the clock rate of the shift clock when the shift register is composed of n stages can be shortened to achieve an effect of saving power.
- each of the n-stage shift registers has half Are divided into shift registers of the same number of stages, one of which stores the odd number of the spread code sequence at the rising edge of the shift clock and performs the shift operation, and the other is the spread code sequence at the falling edge of the shift clock.
- the shift operation is performed by storing an even number of the shift register, so that the clock rate of the shift clock when the shift register is composed of n stages can be halved, and power saving can be achieved.
- a matched filter configuration For example, an odd-numbered code sequence input to the first shift register is sequentially shifted at the rising edge of the shift clock. In the second shift register, the remaining even-numbered code sequence is sequentially shifted at the falling edge of the shift clock, and the first selection means is set when the shift clock is on.
- the even-numbered stage of the reference code register is output to the first multiplication means and the odd-numbered stage of the reference code register is output to the second multiplication means by the second selection means, and conversely, when the shift clock is off.
- the first selection means outputs the odd-numbered stages of the reference code register to the first multiplication means
- the second selection means outputs the even-numbered stages of the reference code register to the second multiplication means.
- the outputs are added by adding means.
- the first shift register and the second shift register are alternately shifted at both edges of the shift clock, and the shift register is used without splitting. This has the effect of reducing power consumption by halving the cut rate while ensuring the same shift operation as that of the above.
- each multiplexer is operated according to the on / off state of the shift clock.
- the RF receiver receives a signal from the RF receiver.
- the baseband signal output is subjected to spectrum despreading in the inter-phase section.Received data is demodulated by the baseband demodulation section, or the baseband signal output from the RF reception section is converted to a baseband signal.
- the correlator is configured as described in claims 1 to 4. Since it has a match filter composed of any of the acyclic digital filters described in any of the above, it is possible to reduce power consumption in the baseband chip, which consumes the most power in wireless communication equipment employing the CDMA system.
- the present invention is advantageous in that it is possible to provide a wireless receiving device suitable for a mobile information terminal or the like that requires power saving, such as a mopile device, a notebook personal computer, and the like.
- received data obtained by subjecting a base span signal output from the RF receiving section to spectrum despreading in an inter-phase section is demodulated by the base spanned demodulating section.
- the baseband signal output from the RF receiver is demodulated by the baseband demodulator, and then the spectrum is despread by the correlator.
- the correlator has a matched filter composed of a non-recursive digital filter according to any one of claims 1 to 4, each radio when configuring a wireless access point-to-car area network is provided.
- the power consumption of the baseband chip, which consumes the most power in the receiving device can be measured, and the power consumption of the entire wireless receiving device that composes the wireless communication network can be reduced. Say the effect can be obtained.
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- Synchronisation In Digital Transmission Systems (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00981820A EP1160976B1 (en) | 1999-12-16 | 2000-12-18 | Noncyclic digital filter and radio reception apparatus comprising the filter |
US09/913,791 US7061975B2 (en) | 1999-12-16 | 2000-12-18 | Noncyclic digital filter and radio reception apparatus comprising the filter |
JP2001545434A JP3991684B2 (ja) | 1999-12-16 | 2000-12-18 | 非巡回型ディジタルフィルタ及びこれを使用した無線受信機器 |
DE2000636280 DE60036280T2 (de) | 1999-12-16 | 2000-12-18 | Nichtzyklischer digitaler filter, und funkempfangsgerät mit dem filter |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35795199 | 1999-12-16 | ||
JP11-357951 | 1999-12-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001045256A1 true WO2001045256A1 (fr) | 2001-06-21 |
Family
ID=18456787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/008980 WO2001045256A1 (fr) | 1999-12-16 | 2000-12-18 | Filtre numerique acyclique et radio-recepteur equipe de ce filtre |
Country Status (5)
Country | Link |
---|---|
US (1) | US7061975B2 (ja) |
EP (1) | EP1160976B1 (ja) |
JP (1) | JP3991684B2 (ja) |
DE (1) | DE60036280T2 (ja) |
WO (1) | WO2001045256A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100895279B1 (ko) | 2001-12-28 | 2009-05-07 | 인터디지탈 테크날러지 코포레이션 | Cdma 시스템 전송 매트릭스 계수 계산을 행하는 기지국 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011058142A1 (en) * | 2009-11-13 | 2011-05-19 | St-Ericsson (Grenoble) Sas | Time-to-digital converter with successive measurements |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS63253713A (ja) * | 1987-04-09 | 1988-10-20 | Pioneer Electronic Corp | サンプリング回路 |
JPH04271507A (ja) * | 1991-02-26 | 1992-09-28 | Fujitsu Ltd | ディジタルトランスバーサルフィルタ |
JPH10190664A (ja) * | 1996-12-20 | 1998-07-21 | Oki Electric Ind Co Ltd | パケット通信装置 |
JPH11251965A (ja) * | 1998-03-05 | 1999-09-17 | Fujitsu Ltd | マッチドフィルタ及びcdma通信方式の無線受信装置 |
JPH11312952A (ja) * | 1998-02-25 | 1999-11-09 | Yozan Inc | マッチドフィルタおよび信号受信装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4369499A (en) * | 1980-09-18 | 1983-01-18 | Codex Corporation | Linear phase digital filter |
DE3484701D1 (de) * | 1983-10-05 | 1991-07-18 | Nec Corp | Digitale signalverarbeitungseinrichtung mit einem digitalen filter. |
US4817025A (en) * | 1984-02-03 | 1989-03-28 | Sharp Kabushiki Kaisha | Digital filter |
US5381455A (en) * | 1993-04-28 | 1995-01-10 | Texas Instruments Incorporated | Interleaved shift register |
JP3202125B2 (ja) * | 1994-03-10 | 2001-08-27 | 沖電気工業株式会社 | 符号分割多元接続システム |
US5493522A (en) * | 1994-09-21 | 1996-02-20 | Northrop Grumman Corporation | Fast arithmetic modulo divider |
ZA965340B (en) * | 1995-06-30 | 1997-01-27 | Interdigital Tech Corp | Code division multiple access (cdma) communication system |
JP2944492B2 (ja) | 1995-11-10 | 1999-09-06 | 国際電気株式会社 | マッチドフィルタ装置 |
JP3800363B2 (ja) | 1996-12-18 | 2006-07-26 | 富士通株式会社 | Cdmaシステム及びその送受信装置及びランダムアクセス方法 |
EP0855796A3 (en) | 1997-01-27 | 2002-07-31 | Yozan Inc. | Matched filter and filter circuit |
US5946344A (en) * | 1997-04-07 | 1999-08-31 | Intermec Ip Corp. | Multiple-rate direct sequence architecture utilizing a fixed chipping rate and variable spreading code lengths |
US6373827B1 (en) * | 1997-10-20 | 2002-04-16 | Wireless Facilities, Inc. | Wireless multimedia carrier system |
JP3557114B2 (ja) * | 1998-12-22 | 2004-08-25 | 株式会社東芝 | 半導体記憶装置 |
-
2000
- 2000-12-18 US US09/913,791 patent/US7061975B2/en not_active Expired - Fee Related
- 2000-12-18 JP JP2001545434A patent/JP3991684B2/ja not_active Expired - Fee Related
- 2000-12-18 EP EP00981820A patent/EP1160976B1/en not_active Expired - Lifetime
- 2000-12-18 DE DE2000636280 patent/DE60036280T2/de not_active Expired - Lifetime
- 2000-12-18 WO PCT/JP2000/008980 patent/WO2001045256A1/ja active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63253713A (ja) * | 1987-04-09 | 1988-10-20 | Pioneer Electronic Corp | サンプリング回路 |
JPH04271507A (ja) * | 1991-02-26 | 1992-09-28 | Fujitsu Ltd | ディジタルトランスバーサルフィルタ |
JPH10190664A (ja) * | 1996-12-20 | 1998-07-21 | Oki Electric Ind Co Ltd | パケット通信装置 |
JPH11312952A (ja) * | 1998-02-25 | 1999-11-09 | Yozan Inc | マッチドフィルタおよび信号受信装置 |
JPH11251965A (ja) * | 1998-03-05 | 1999-09-17 | Fujitsu Ltd | マッチドフィルタ及びcdma通信方式の無線受信装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100895279B1 (ko) | 2001-12-28 | 2009-05-07 | 인터디지탈 테크날러지 코포레이션 | Cdma 시스템 전송 매트릭스 계수 계산을 행하는 기지국 |
Also Published As
Publication number | Publication date |
---|---|
EP1160976A4 (en) | 2003-04-23 |
EP1160976A1 (en) | 2001-12-05 |
JP3991684B2 (ja) | 2007-10-17 |
DE60036280D1 (de) | 2007-10-18 |
US7061975B2 (en) | 2006-06-13 |
EP1160976B1 (en) | 2007-09-05 |
US20020159515A1 (en) | 2002-10-31 |
DE60036280T2 (de) | 2008-11-06 |
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