Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
  • H01L25/0657—Stacked arrangements of devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the invention relates to a semiconductor memory chip module with a plurality of memory chips of different types, in particular with a plurality of memory chips designed in different manufacturing technology.
• the invention relates to a semiconductor memory chip module suitable for chip cards and a chip card equipped with such a chip module.
• the currently available semiconductor memories can be assigned to different types depending on their manufacturing technology, their operating parameters, their capacity, etc. A distinction can be made between semiconductor memories, for example, into volatile and non-volatile memories.
• Non-volatile memories are expediently used in chip cards and in chip card terminals, but their content can also be deleted and overwritten.
• Semiconductor memories typically used for this purpose are EEPROMs.
• Such EEPROMs that is to say erasable, electrically programmable read-only memories, require some circuitry outlay for erasing and rewriting data and require a relatively long access time in comparison to volatile memories, for example a DRAM or SRAM. If such a semiconductor memory is used in the execution of software programs, only a slow execution is possible for the program. In addition, only a limited number of erase and write operations are possible with an EEPROM, typically in the order of 10,000 to 100,000.
• a non-volatile memory for example an EEPROM
• SRAM static random access memory
• non-volatile memory EEPROM
• SRAM fast volatile memory
• the invention is based on the object of specifying a semiconductor memory chip module in which the advantages of two types of memory chip can be achieved without the disadvantages mentioned, that is to say high manufacturing outlay and long conduction paths.
• a semiconductor memory chip module with different types of memory chips in that the memory chips are arranged one above the other in different levels and are connected by vertical Z-type interconnects.
• the first type of memory chip is a non-volatile memory, in particular EEPROM
• the second type is a volatile memory, for example an SRAM.
• the invention allows the production of a semiconductor memory chip module with different types of memory chips, in particular memory chips manufactured according to different manufacturing technologies.
• the chips can be manufactured separately - with the aid of the manufacturing processes typical of them.
• the finished chips each require only a relatively small chip area.
• the finished chips are then stacked on top of one another, the connections between the chips being vertical connections, ie taking up very little additional chip area.
• the chip stack is then formed as a closed unit, in particular encapsulated in a module, so that it can be installed in a chip card.
• each semiconductor memory includes a drive circuit in addition to the actual memory cells, referred to here as a decoder, these decoders can be formed together with the respective semiconductor chip.
• a further chip with decoder circuits for all memory chips of the chip module is provided in a further level.
• the chip allocation area is therefore not increased in the horizontal direction by the decoder circuits in the further chip.
• the chip with the decoder circuits is also Inter-chip connections are connected to the memory chip of the first or second type, depending on which chip is located directly below the chip with the decoder circuits.
• a special feature when using memory chips in connection with chip cards and chip card terminals is the defense against so-called power analysis attacks.
• power analysis attacks In the case of such attacks, fraudulent attempts are made to analyze current and voltage conditions on a circuit using special sensors, in order to be able to draw conclusions about protected data. If voltage and current levels are provided at all connections, which always assume one or one of several defined levels, regardless of internal switching states, then such an attack is not possible.
• the supply voltage for the chip can be smoothed to such an extent that no level changes are recognizable to the outside, which could allow conclusions to be drawn about circuit states.
• an energy buffer in particular in the form of an integrated capacitor, is formed in at least one of the levels of the chip module.
• This buffer capacitor can occupy an entire chip level, but in the case of a preferred multilayer design it can also be limited to only a partial chip area, so that the rest of this level is then available for memory cells, decoder circuits or logic circuits.
• This buffer capacitor can then be used at the end of the processing of a program, carried out with the aid of the volatile memory, to carry out the Save the results of the program and other data in the non-volatile memory.
• the data required to restart the program can be permanently stored in the non-volatile memory with the aid of the buffer capacitor.
• FIG. 1 shows a schematic vertical sectional view through a semiconductor memory chip module according to a first embodiment of the invention
• Figure 2 is a representation similar to Figure 1 of a second embodiment of the invention.
• FIG. 1 shows a semiconductor memory chip module 2 according to a first embodiment of the invention.
• the chip module 2 contains three stacked chips, namely a lower chip 4, here designed as EEPROM, ie as a non-volatile memory chip, a middle chip 6, here designed as SRAM, ie designed as a volatile memory chip, and an upper chip 8, which includes two types of decoder circuits 10 and 12.
• a predetermined number of memory cells C4 is formed in the memory chip 4, and aligned with these in the vertical direction, the memory chip 6 contains a corresponding number of volatile memory cells C6.
• the memory cells C4 and C6 in the memory chips 4 and 6 are aligned vertically, as indicated by vertical lines in FIG. 1. It is there is a direct electrical connection between the vertically assigned memory cells C4 and C6 by means of so-called vertical interchip connections, which are explained in more detail below for the exemplary embodiment shown in FIG.
• the decoder circuits 10 and 12 contained in the upper level in the upper chip 8 enable various addressing options for the memory chips 4 and 6.
• the decoder circuits 10 (only one is shown in FIG. 1) serve to control the memory cells C4 in the lower memory chip 4
• the decoder circuits 12 serve to drive the memory cells C6 in the middle memory chip 6.
• the decoder circuits 10 and 12 can also be used for both memory chips 4 and 6, respectively.
• FIG. 2 shows a second embodiment of a semiconductor memory chip module 2 ′, which is structured based on the chip module shown in FIG. 1.
• a lower memory chip 4 is designed as an EEPROM
• a memory chip 6 designed as SRAM is located above it on the next level.
• the vertically aligned memory cells C4 and C6 are electrically connected via vertical intermediate chip connections 16.
• the memory chip 6 is connected to the chip 8 via similar vertical intermediate chip connections, which contains decoding circuits (not shown in more detail) and additionally a buffer capacitor 20.
• the buffer con- The capacitor 20 is also connected to the underlying memory chip 6 via direct vertical intermediate chip connections 22a and to a further chip 16 lying above it via intermediate chip connections 22b. It is also connected to the decoder circuits contained in the chip 8 via a connection indicated at 24. Through connections (not shown), the buffer capacitor 20 is also connected to the lower memory chip 4.
• the top level of the chip 16 which contains, for example, logic circuits, has its function for all of the other chips 4, 6 and 8 is available.
• the buffer capacitor 20 is made from a plurality of alternating electrically conductive or dielectric layers.
• the buffer capacitor 20 is constantly kept at a supply voltage level by a feed line, not shown. Its capacity is dimensioned such that, in the event, for example, of an interruption of operation of the chip module 2 ′, it allows data from the SRAM of the memory chip 6 to be written into corresponding memory cells of the EEPROM of the memory chip 4.
• the invention and the embodiments of a chip module shown in FIGS. 1 and 2 are particularly suitable for installation in a chip card or a chip card terminal, although the invention is not restricted to this.
• the order of the memory chips can be changed, for example in FIG the different chips 4, 6 and 8 are exchanged in their order. The same applies to the arrangement according to FIG. 2.
• the buffer capacitor 20 can also extend over an entire chip level.
• the decoder circuits, shown in FIG. 1 in the upper chip 8 at 10 and 12, can also be distributed over different chip levels.
• the exemplary embodiments of semiconductor memory chip modules shown in FIGS. 1 and 2 contain the chips 4, 6, 8 and 16 produced in separate manufacturing processes.
• the separately manufactured chips are stacked on top of one another and connected to one another vertically by bonding.
• bonding is understood to mean the connection of the individual chips or wafers containing chips.
• the chips or wafers can be thinned. H. their thickness is reduced after manufacture.
• the actual electrical connection of the individual chips or wafers to one another takes place - as described above - by means of vertical intermediate chip connections.
• the vertical intermediate chip connections are produced by means of a metallization process which corresponds to the metallization process in the manufacture of the individual chips or wafers. This allows a high connection density to be achieved, e.g. B. allows, as described above, individual memory cells in different levels, i. H. on different chips, to be electrically connected to each other. This also results in an increase in security, since the internal vertical intermediate chip connections are not accessible from the outside and therefore cannot be accessed for
• the semiconductor memory chip module according to FIG. 1 or 2 then operates in such a way that the permanently stored data are located in the lower chip 4, that is to say in the non-volatile memory EEPROM.
• the required data is reloaded into the middle chip, i.e. the volatile memory (SRAM).
• the middle chip 6 then acts like a cache memory. Result data and, for example, data to be backed up in the event of an interruption of operation, are then reloaded from the middle memory chip 6 into the lower memory chip 4, for which purpose the energy stored in the buffer capacitor is used.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Power Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Engineering & Computer Science (AREA)
• Computer Security & Cryptography (AREA)
• Semiconductor Memories (AREA)
• Static Random-Access Memory (AREA)
• Semiconductor Integrated Circuits (AREA)
• Credit Cards Or The Like (AREA)
• Dram (AREA)
• Read Only Memory (AREA)

Priority Applications (8)

Applications Claiming Priority (2)

Publications (1)

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ID=7912247

Family Applications (1)

Country Status (12)

Families Citing this family (17)

Citations (4)

Family Cites Families (15)

• 1999
  • 1999-06-23 DE DE19928733A patent/DE19928733A1/de not_active Withdrawn
• 2000
  • 2000-06-19 DE DE50001991T patent/DE50001991D1/de not_active Expired - Lifetime
  • 2000-06-19 AT AT00942097T patent/ATE239296T1/de not_active IP Right Cessation
  • 2000-06-19 CN CNB008094365A patent/CN1203486C/zh not_active Expired - Fee Related
  • 2000-06-19 CA CA002377175A patent/CA2377175C/en not_active Expired - Fee Related
  • 2000-06-19 JP JP2001506553A patent/JP2003503834A/ja active Pending
  • 2000-06-19 US US09/926,791 patent/US6721196B1/en not_active Expired - Lifetime
  • 2000-06-19 KR KR1020017016453A patent/KR100708597B1/ko not_active Expired - Fee Related
  • 2000-06-19 ES ES00942097T patent/ES2193968T3/es not_active Expired - Lifetime
  • 2000-06-19 AU AU56835/00A patent/AU5683500A/en not_active Abandoned
  • 2000-06-19 EP EP00942097A patent/EP1198797B1/de not_active Expired - Lifetime
  • 2000-06-19 BR BR0011868-0A patent/BR0011868A/pt not_active IP Right Cessation
  • 2000-06-19 WO PCT/EP2000/005625 patent/WO2001001418A1/de not_active Ceased

Patent Citations (4)

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