WO2000051184A1 - Dispositif a circuit integre en semiconducteur - Google Patents

Dispositif a circuit integre en semiconducteur Download PDF

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Publication number
WO2000051184A1
WO2000051184A1 PCT/JP1999/006989 JP9906989W WO0051184A1 WO 2000051184 A1 WO2000051184 A1 WO 2000051184A1 JP 9906989 W JP9906989 W JP 9906989W WO 0051184 A1 WO0051184 A1 WO 0051184A1
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WIPO (PCT)
Prior art keywords
electrode
lines
line
sub
pair
Prior art date
Application number
PCT/JP1999/006989
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English (en)
Japanese (ja)
Inventor
Nobutaka Itou
Syuichi Miyaoka
Yuji Yokoyama
Michiaki Nakayama
Mitsugu Kusunoki
Kazumasa Takashima
Hideki Sakakibara
Tooru Kobayashi
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Hitachi, Ltd
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Application filed by Hitachi, Ltd filed Critical Hitachi, Ltd
Priority to TW089101516A priority Critical patent/TW594977B/zh
Publication of WO2000051184A1 publication Critical patent/WO2000051184A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective for use in a large-scale integrated circuit including a dynamic RAM (random 'access' memory) and a logic circuit for controlling the memory.
  • a dynamic RAM random 'access' memory
  • a logic circuit for controlling the memory for controlling the memory.
  • the inventors of the present application have used a dynamic memory cell as a memory to increase the storage capacity, and a buffer memory using a static memory cell has been proposed as a technique for speeding up the read operation.
  • a dynamic memory cell as a memory to increase the storage capacity
  • a buffer memory using a static memory cell has been proposed as a technique for speeding up the read operation.
  • Multi-bit data is read out from the storage unit to the above-mentioned buffer memory at a time, and data is input / output to / from external devices via the buffer memory.
  • the buffer memory as a cache memory, it is possible to increase the speed of the memory operation when viewed from the outside of the semiconductor integrated circuit device.
  • To read data it is necessary to provide a number of main amplifiers corresponding to each bit. The main amplifier widens the width signal of the sense amplifier.
  • the amplitude of the input signal that is input is larger than that of the sense amplifier, and it is necessary to perform high-speed operation. A relatively large current is required to flow. Conversely, in the sense amplifier, the operating current is narrowed down in order to stably sense the small signal read out to the bit line in accordance with the presence or absence of the information charge stored in the small storage capacity. It is necessary,:,
  • the signal read out to the bit line is a minute voltage near the center voltage of the operating voltage.
  • a minute voltage near the center voltage is input to the CM0S latch configuration sense amplifier, the N-channel type and the P-channel type Both MOSFETs are turned on. Therefore, if the current for sensing operation is increased, a large through current will be generated through the MOSFETs in the ON state. In this method, the output signal is positively fed back to the input, so that the read signal voltage fluctuates due to the influence of the through current and the possibility of malfunction is increased.
  • the main amplifier amplifies the amplified signal of the sense amplifier. Since the amplitude of the input signal input is larger than that of the sense amplifier, it is stable by allowing a larger current to flow than the above sense amplifier. In addition, it is possible to perform the width operation at high speed. However, if a batch reading of multi-bit memory cells is performed for high-speed data input / output to / from external devices, the main amplifier must be compared to a general-purpose dynamic RAM. And the number of peripheral circuits, such as address selection circuits, can cause malfunctions in the logic circuits that make up the buffer memory due to noise on the power supply lines during the operation of the main amplifier. It was found to happen.
  • a semiconductor integrated circuit device comprising a read-write section including A first electrode corresponding to a plate electrode having the same structure as that of the first embodiment, and a second electrode having a plurality of storage nodes of the storage capacity shared by a plurality of storage nodes are formed in series with each other. It is arranged adjacent to the read / write section, and the series circuit of the two capacitors is connected between the operating voltages of the read / write section.
  • FIG. 1 is a schematic layout diagram showing an embodiment of a semiconductor integrated circuit device equipped with a dynamic RAM according to the present invention
  • FIG. 2 is a layout diagram in which a part of the memory array unit of FIG. 1 is enlarged.
  • FIG. 3 is a schematic layout diagram showing one embodiment of a subarray and its peripheral circuits in a dynamic RAM according to the present invention.
  • FIG. 4 is a circuit diagram showing an embodiment simplified around the sense amplifier section of the dynamic RAM according to the present invention.
  • FIG. 5 is a schematic layout diagram showing one embodiment of a semiconductor integrated circuit device equipped with a dynamic RAM according to the present invention
  • FIG. 6 is a schematic sectional structural view showing one embodiment of a dynamic memory cell and its peripheral circuit (logic circuit) part.
  • FIG. 7 shows an embodiment of a noise suppression capacity used in the present invention.
  • FIG. 8 is a schematic plan view showing one embodiment of a noise suppression capacitor used in the present invention.
  • FIG. 9 is a schematic plan view showing one embodiment of a noise suppression capacitor used in the present invention.
  • FIG. 10 is an equivalent circuit diagram of the noise suppression capacity shown in FIG.
  • FIG. 11 is a plan view showing an embodiment of the main amplifier section of FIG. 1.
  • FIG. 12 is a plan view showing an embodiment of the main amplifier section of FIG.
  • FIG. 14 is a timing chart for explaining an example of a write operation of the dynamic RAM unit of the semiconductor integrated circuit device according to the present invention.
  • FIG. 14 is a timing chart of the dynamic RAM unit of the semiconductor integrated circuit device according to the present invention.
  • FIG. 15 is a timing chart for explaining an example of a read operation.
  • FIG. 15 is a schematic diagram showing another embodiment of a semiconductor integrated circuit device equipped with a dynamic RAM according to the present invention.
  • FIG. 16 is a schematic layout diagram showing another embodiment of a semiconductor integrated circuit device on which a dynamic RAM according to the present invention is mounted, and FIG. The semiconductor integrated circuit equipped with the dynamic RAM force according to the present invention. It is a further schematic Reiau Bok view showing another embodiment of the apparatus.
  • FIG. 1 shows a semiconductor device having a dynamic RAM according to the present invention.
  • a schematic layout diagram of one embodiment of a body integrated circuit device is shown.
  • the main part of each circuit block constituting the dynamic RAM to which the present invention is applied is shown so as to be clearly understood, and is shown by a known semiconductor integrated circuit manufacturing technology.
  • the storage unit constituted by the dynamic memory cells is divided into two parts vertically with respect to the longitudinal direction of the chip (vertical direction in FIG. 1), and two parts vertically.
  • the stored storage units are each divided into four memory array units.
  • the above four memory array units are divided into left and right with a peripheral circuit unit extending in the vertical center part as a center.
  • the peripheral circuit in the vertical center is not particularly limited, but is provided with an X-system address select circuit for performing a word line selecting operation and the like.
  • Each of the memory arrays is divided into two equal parts vertically.
  • the memory array part divided into two equal parts below S ⁇ is further divided into two equal parts by centering on the MA noise C (capacity) shown in the figure. In other words, one memory array part is divided into four equal parts up and down
  • Peripheral circuits are provided on the chip center side of the four memory array units.
  • the peripheral circuits near the chip center are provided mainly for Y-system address selection circuits that mainly perform bit line selection operations.
  • a static RAM (SRAM macro) as a buffer memory is provided on the chip center side of the above four memory array parts, that is, a total of eight memory chips divided into four at the top and bottom of the semiconductor chip.
  • a total of eight static RAMs are provided for each memory array.
  • a logic circuit for controlling input / output of data with the memory array unit is also provided.
  • the external port that constitutes the first port A first input / output circuit for inputting / outputting data to / from a terminal is provided.
  • a static RAM (RAM macro) is provided at the center of the chip. This static RAM is different from the external terminal constituting the first port, and performs input / output of data from the external terminal constituting the second port.
  • the static RAM can be exchanged with the SRAM macro as the buffer memory through the above-described internal logic circuit and the like.
  • the first and second boats are not particularly limited, but data is input and output in a unit of 16 bits.
  • FIG. 2 is a layout diagram in which a part of the memory array section of FIG. 1 is enlarged. That is, of the memory array of FIG. 1, the array power of a part indicated by a dotted line in FIG. Fig. 2 shows an enlarged view.
  • a sense amplifier area SA is formed vertically above and below a sub-array (memory cell array) SARY, and a sub-word drive area S WD is formed left and right, that is, a memory in which dynamic memory cells are arranged in a matrix.
  • the cell array is divided by the sense amplifier area SA and the sub-line area SWD.
  • the intersection between the sense amplifier area SA and the sub-word drive area SWD is an intersection area (cross area).
  • the sense amplifiers provided in the sense amplifier area SA are configured by a shared sense method and, except for the sense amplifiers SA arranged at both upper and lower ends of the array, complementary bits are provided on the left and right (up and down) around the sense amplifier SA.
  • a single sub-array SARY shown as an enlarged view, which is selectively connected to the complementary bit line of the memory cell array on either the left or right 2 5 6 and complementary bit lines (or orthogonal) Data lines) are 2 5 6 pairs.
  • eight regular subarrays SARY are provided in the bit line direction.
  • five sub-arrays SARY are provided in the word line direction.
  • One redundant sub-array is provided near the center in the bit line direction. This redundant sub-array is provided with its own sense amplifier so that it can be independently selected.
  • One sub-array has a storage capacity of 256 ⁇ 256, and 5 ⁇ 8-40 such sub-arrays are provided in one array.
  • the memory array section has eight arrays in total. Therefore, one memory array section has a storage capacity of 256 Mbits x 256 Mbits. As described above, one semiconductor integrated circuit device has a capacity of 8 Mbits. Since the number of memory array units is provided, the total memory capacity is about 160 Mbits.
  • a sub-word select driver SWD is arranged to select one sub-node line from sub-node lines assigned four by four in the complementary bit line direction.
  • the sub-word select driver SWD forms a select signal for selecting one of the four sub-code select lines extending in the arrangement direction of the sub-code drivers.
  • one main code is provided. Line selection and one of the five sub-array sub-lines are selected.
  • a total of 36 bits of data can be input / output through the main input / output lines extending vertically on the sub-word driver SWD.
  • a total of 36 main amplifiers MA and light amplifiers WA are provided below the array.
  • the main amplifier MA, the light amplifier and its control circuit RWC are arranged in two stages.
  • the two-stage main amplifier MA, light amplifier and its control circuit RWC are provided below the two-stage main amplifier MA, write amplifier and its control circuit RW C via the MA noise suppression capacitor.
  • These main amplifier MA, light amplifier and its control circuit RWC correspond to a similar array provided on the lower side not shown.
  • the array divided vertically above and below the MA noise countermeasure capacitor, the corresponding main amplifier MA, the corresponding write amplifier, and the control circuit RW C are mirror-inverted in a mirror-inverted form. Be placed. This can be easily understood from the overall layout diagram in FIG.
  • the memory array section is divided into four memory arrays vertically and horizontally, 72 bits each from the two memory arrays on the left, and 7 bits each from the two memory arrays on the right. Memory access in units of 2 bits is made possible. Therefore, memory access power in units of 288 bits in total ⁇ these 288 bits of data that can be
  • the data is transferred between the RAM macro and the RAM macro in half-144-bit units. That is, the main amplifier MA, the write amplifier, and the control circuit RWC are divided into four parts as described above.
  • the data is transferred in batches corresponding to the upper and lower memory arrays,
  • the noise suppression capacitor is provided on the power supply line of the main amplifier MA and reduces noise generated on the power supply lines (VDD, VSS) during the amplification operation.
  • Such multi-bit data reading can be performed at high speed.
  • the write amplifier performs write operations simultaneously on as many as 288 memory cells, and the parasitic capacitance of the bit line connected to the memory cells and the input / output lines leading to the memory cells is detected. An electric current flows to increase the voltage or discharge.
  • the above-mentioned noise suppression capacitor is useful in reducing the noise of the power supply lines V DD and V SS even during such writing.
  • the noise suppression capacitor is placed as control noise C between the control circuit (address selection circuit) of the DRAM section and the SRAM macro. Also, the capacitor C is arranged between the RAM and the RAM as an I / O noise C. Each of these capacitors C has the same structure as that of the MA noise C.
  • the noise generated on each power supply line is provided by arranging the noise countermeasure C at the boundary of each circuit. Can be reduced to contribute to the stabilization of the circuit.
  • FIG. 3 is a schematic layout diagram showing an embodiment of a sub-array and its peripheral circuits in the dynamic RAM according to the present invention. Same figure In FIG. 2, four sub-arrays SBARY in the memory array shown in FIG. 2 are representatively shown. In FIG. 3, the region where the sub-array S BARY is formed is shaded to distinguish a sub-pad region, a sense amplifier region and a cross area provided around the region.
  • the sub-array S BARY is not particularly limited, but is divided into the following four types. That is, assuming that the word lines extend in the horizontal direction, the first sub-array SB ARY arranged at the lower right is arranged with 256 sub-line SWL forces, and the complementary bit line pair is from 256 pairs. Be composed. Therefore, 256 sub-drivers SWD corresponding to the 256 sub-drivers SWL are divided and arranged on the left and right of the sub-array in a unit of 128.
  • the 256 sense amplifiers SA provided corresponding to the 256 pairs of complementary bit lines BL are arranged alternately in addition to the shared sense amplifier system described above, and are arranged above and below the sub-array. Are arranged in 1 2 8 pieces at
  • the second sub-array SB ARY arranged at the upper right is not particularly limited, but is provided with 256 normal (sub-word lines) SWLs and 8 spare (redundant) lines, and complementary bit line pairs. Consists of 256 pairs. Therefore, the 264 sub-drivers SWD corresponding to the above-mentioned 256.68 sub-driver lines SWL are divided and arranged on the left and right of the sub-array in a unit of 132.
  • the amplifiers are arranged vertically one by one in the same manner as described above. That is, 128 pairs of complementary bit lines out of the 156 pairs formed in the subarray S BAR Y arranged above and below the right side are shared switch switches with respect to the sense amplifier SA sandwiched therebetween. Commonly connected via S FET,-,
  • the third sub-array SB ARY arranged at the lower left is the sub-array adjacent to the right
  • the sub word line SWL is composed of 256 lines.
  • 128 sub-word drivers are divided and arranged.
  • 128 sub-word lines SWL are The sub-array S BAR Y, which is connected in common to the 128 sub-word drivers SWD formed in the sandwiched area, is arranged in the lower left as described above, and has 256 regular pairs of complementary bit lines.
  • four pairs of spare (redundant) bit lines 4 RED are provided. Therefore, 260 sense amplifiers SA corresponding to the above-mentioned 260 pairs of complementary bit lines BL are: It is divided into 130 sub-arrays above and below this sub-array.
  • the fourth sub-array S BARY arranged on the upper left has, like the right adjacent sub-array SB ARY, 256 regular sub-line SWL and eight spare sub-nodes, and the lower adjacent sub-array Similarly, four spare bit lines are provided in addition to the regular complementary bit line pairs of 256, so that the sub-driver SWDs are divided into 132 units on the left and right sides, and are SAs are divided into 130 units at the top and bottom.
  • each sub-array SB ARY has a spare sub-node line, a spare complementary bit line force, and a power that can be individually remedied. What cannot be remedied by use is remedied by the redundant sub-array.
  • the normal sub-array may include only the normal sub-word line and the complementary bit line, and the repair may be replaced with a spare sub-line and a spare complementary bit line provided in the redundant sub-array.
  • the main lead line MWL is extended in the horizontal direction as described above, one of which is exemplarily shown as a representative, and the column selection line YS is shown as one of which is exemplarily represented. Is extended vertically.
  • the above A sub-lead line SWL is arranged in parallel with the main lead line MW L, and a complementary bit line BL (shown in the figure) is arranged in parallel with the above-mentioned ram selection line YS.
  • sub-node selection lines FX 0 B to FX 7 B are used to pass through four (eight) sub-arrays in the same way as the main node line MW L Is extended to Then, four subword selection lines, FX 0 B to FX 3 B, and four sub word selection lines, FX 4 B to FX 7 B, are strongly separated and extended on the upper and lower subarrays.
  • the reason for assigning a set of sub-line selection lines FX0B to FX7B to one subarray and extending them on the subarray is to reduce the memory chip size. Is for:
  • the wiring itself is The above eight sub-node selection lines FX 0 B to FX 7 B are commonly assigned to the upper and lower two sub-arrays, and they are mixed together on the sub-array in parallel with the main sub-line. By arranging in such a manner, it can be formed without providing a special wiring-dedicated area,
  • one main line is provided for eight sub-lines, and one sub-line is selected to select one of the eight sub-lines.
  • the selection line is the key. Since the main lead line MWL is formed by dividing one of eight sub-lead lines SWL formed according to the memory cell pitch, the wiring pitch of the main lead line MWL Has become loose c, therefore, the main ⁇ -Using the same wiring layer as the MWL and forming the sub-node selection lines between the main-node lines can be made relatively easily with only a slight sacrifice of the wiring bitness. Is,
  • the sub-word driver SWD of this embodiment has a configuration in which one sub-word line SWL is selected by using a selection signal supplied through the above-mentioned sub-word selection line FX0B and the like and a selection signal obtained by inverting the selection signal. take.
  • the sub-driver SWD is configured to simultaneously select the sub-line lines SWL of the sub-arrays arranged on the left and right of the sub-driver SWD;
  • a select signal from the first sub-mode select line FX0B is provided in the upper left cross area.
  • a second sub-node selection line FX0 for supplying a selection signal to the above-mentioned 64 sub-node drivers arranged vertically through a sub-node selection line driving circuit FXD.
  • the first sub-line selection line FX 0 B is extended in parallel with the main line MWL and the sub-line SWL, whereas the second sub-line selection line is The sub-driver region is extended in parallel with the column selection line YS and the complementary bit line BL, which are orthogonal to it.
  • the second sub-word selection lines FX 0 to FX 7 also have even FX 0, 2, 4, 6 and odd FX. Divided into 1, 3, 5, and 7 and distributed to the sub-drivers SWD provided on the left and right of the sub-array S BAR Y.
  • the sub-node selection line driving circuits FXD are arranged in a two-part distribution above and below one cross area. That is, as described above, in the upper left cross area, the lower sub-selection line driving circuit arranged on the lower side corresponds to the first sub-selection line FX0B.
  • the two sub-line selection line drive circuits FXD provided in the middle middle left mouth selection line are FXD power, the first sub word selection line FX2B and FX4B are supported, and the left bottom left corner selection line
  • the sub-node selection line and the driving circuit arranged above the line correspond to the first sub-node selection line FX6B.
  • the sub-path selection iR spring drive circuit power located on the lower side ⁇ corresponding to the above-mentioned first sub-word selection line FX 1 B, and the two Sub-line select line and drive circuit FXD The first sub-line select line FX3B and the sub-line select line drive circuit corresponding to FX5B and located above the cross area in the lower center are the above-mentioned sub-line select lines and drive circuits.
  • the sub-selection line driving circuit disposed on the lower side corresponds to the first sub-selection line FX 0 B.
  • the drive circuit FXD corresponds to the first sub-node selection line FX2B and FX4B, and the right The sub-node selection line drive circuit located above the lower cross area In the sub-driver provided at the end of the memory array in this manner, which corresponds to the first sub-node selection line FX6B, there is no sub-array on the right side.
  • the sub-line selection line FXB is arranged in the gap between the bit lines of the main line MWL on the sub-array as in this embodiment, a special line channel is not required, so that eight sub-arrays can be arranged in one sub-array. Arranging the sub-line select lines does not increase the memory chip size. However, the area of the cross region increases to form the above-mentioned sub-node selection line driving circuit FXD, which hinders high integration.
  • Switch circuit provided corresponding to the main input / output line MI ⁇ and the local input / output line LI 0 as shown by the dotted line Peripheral circuits such as I OSW, power MOS SFET driving sense amplifier, shared switch M ⁇ S FET driving circuit, precharge MOS FET driving circuit and other peripheral circuits are formed.
  • the sub-selection line driving circuit FXD is shared by the two sub-arrays under the upper Z to suppress an increase in area.
  • an N-channel type MOS FET is provided to supply the ground potential VSS of the circuit to the sense amplifier.
  • This N-channel type MOSFET supplies the ground potential to the common source line (CSN) of the width M ⁇ SFET of the N-channel type MOS FET constituting the sense amplifier based on the power on both sides of the sense amplifier row. .
  • the N-channel type power MOSFET provided in the A-side cross area and the B-side cross area provided in the B-side cross area are provided.
  • the ground potential is supplied by both of the N-channel type power M 0 SFETs.
  • the sub-word line drive circuit SWD selects the sub-line lines of the left and right sides of the sub-array with the center as the center.
  • the two left and right sense amplifiers are activated corresponding to the sub-line of the two sub-arrays that have been selected:
  • the address selection M 0 SFET is turned on, and the storage capacitor is turned off. This is because the charge is combined with the bit line charge, and it is necessary to perform a rewrite operation of returning the state of the original charge after activating the sense amplifier. Therefore, except for the one corresponding to the subarray at the end of the above, the power MOSFET is used to activate the sense amplifiers on both sides of the power MOSFET. On the other hand, the power MOSFET is provided at the end of the subarray group.
  • the above-mentioned self-sense amplifier is of a shielded sense type, and among the subarrays arranged on both sides of the sense amplifier, the shared switch corresponding to the complementary bit line on the side where the above-mentioned sub-line is not selected.
  • the MOSFET When the MOSFET is turned off and disconnected, the read signal of the complementary bit line corresponding to the selected sub-node line is amplified, and the memory capacity of the memory cell is returned to the original charge state And perform a rewrite operation.
  • FIG. 4 is a circuit diagram of a simplified embodiment focusing on the sense amplifier section of the dynamic RAM according to the present invention.
  • a sense amplifier 16 sandwiched between two sub-arrays 15 from above and below and a circuit provided in the cross-over area 18 are exemplarily shown, and others are shown as block diagrams. Is
  • MOS is understood to be a simplified term for a metal 'oxide' semiconductor configuration.
  • MOS which is commonly used in recent years, is one of the essential parts of semiconductor devices. Includes those that replace mail with non-metallic electrical conductors, such as polysilicon, and those that replace oxide with other insulators.
  • CMOS has also come to be understood to have broad technical implications in response to changes in the perception of MOS as described above.
  • MOS FETs have similarly narrow implications Rather than being understood in the above, it has become meaningful to include a broadly defined configuration that can be considered as an insulated gate field effect transistor.
  • the CMOS, MOS FET, etc. of the present invention follow common names,
  • a typical example of the dynamic memory cell is one provided between the sub-line SWL provided in the one sub-array 15 and one of the complementary bit lines BL and BLB.
  • the gate of the dynamic memory cell which is composed of an address selection MOS FET Qm and a memory Cs, is connected to a sub-word line SWL.
  • the drain of ETQm is connected to bit line BL, and the storage capacitor C s is connected to the source.
  • the other electrode of the storage capacitor C s is shared and receives a plate voltage VPLT:
  • a negative back bias voltage VBB is applied to the substrate (channel) of the address selection MOSFET Qm.
  • the selection level of SWL is set to a high level 3 ⁇ 4ffV PP higher than the high level of the bit line by the threshold voltage of the address selection MOS FET Qm.
  • the sense amplifier When the sense amplifier is operated at the power supply voltage VDD such as 1.8 V, the high level amplified by the sense amplifier and given to the bit line is set to the above-mentioned internal voltage VDD level. Therefore, the high voltage VPP corresponding to the above word line selection level is set to VDD i Vth ten (:: about 3.6 V) 'A pair of sub-arrays provided on the left side of the sense amplifier
  • VDD i Vth ten (:: about 3.6 V) 'A pair of sub-arrays provided on the left side of the sense amplifier
  • the complementary bit lines BL and BLB are arranged in parallel as shown in the figure, and are appropriately crossed as necessary to balance the bit line capacity. And BLB are connected to the input / output node of the unit circuit of the sense amplifier by the shared switch M 0 SFE TQ 1 and Q 2.
  • the unit circuit of the sense amplifier is composed of N-channel type MOS FETs Q5, Q6 and P-channel type wide MOS SFETMO SF ETQ7, Q8, which have a gate and drain cross-connected to form a latch. Consists of: The sources of N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. A power switch MOSFET is connected to the common source lines CSN and CSP, respectively.
  • the common source line CSN to which the sources of the N-channel type wide MOSFETs Q5 and Q6 are connected is connected to the N-channel type bar-switch MOSFET Q14 provided in the cross area 18 described above. Operating voltage corresponding to ground potential is applied
  • the common source line CSP to which the source of the P-channel type wide MOS FETQ 7 and Q 8 is connected has the N-channel type provided in the cross area 18 above.
  • a version MO SFE TQ 15 is provided.
  • the boosted voltage VPP is applied to the gate, and the drain pump is connected to the power supply voltage VDD.
  • the voltage slightly lowered from the source with respect to the power supply voltage VDD may be used as the operating voltage of the sense amplifier.
  • the sense amplifier activation signal SAP supplied to the gate of the N-channel type power MOSFET TQ 15 is not particularly limited, but its high level is a signal of the boosted voltage VPP level.
  • the N-channel type MOSFETQ 15 can be turned on by the boosted voltage VPP to output VDD.
  • the input / output nodes of the unit circuit of the sense amplifier consist of equalizing MOSFET Q11 that shorts the complementary bit line, and switch MOSFETs Q9 and Q10 that supply the half precharge voltage VBLR to the complementary bit line.
  • Precharge circuits are provided.
  • the gates of these MOSFETs Q9 to Q11 are supplied with a precharge signal PCB in common.
  • a driver circuit for forming the precharge signal PCB is provided with an inverter circuit in the cross area so that the falling speed is high.
  • the MOSFETs Q9 to Ql1 which constitute the above-mentioned free-ranging circuit, are switched at high speed through inverter circuits provided separately in each cross area.
  • the cross area 18 includes, in addition to the circuit shown in FIG. 4, a half-precharge circuit for the common source lines CSP and CSN of the sense amplifier, a single-input / output line LI Half-precharge circuit, shared selection signal lines SHR and SHL distributed driver circuits, etc.
  • the unit circuit of the sense amplifier is connected to similar complementary bit lines BL and BLB of the sub-array 15 on the lower side of the figure via shared switch MOSFETs Q3 and Q4.
  • Switch MOSFETs Q12 and Q13 When the selection signal YS is set to a selection level (high level), the switch is turned on, and the input / output node of the unit circuit of the sense amplifier and the local input / output lines L101 and LI01 are formed. B, LI 02, LI 02 B, etc. For example, when the sub-lead line SWL of the upper sub-array is selected, the upper shield switch MOSFETs Q1 and Q2 of the sense amplifier are kept on, and the lower shared switch MOSFETs Q3 and Q4 are off. ,
  • the input / output node of the sense amplifier is connected to the complementary bit lines BL and BLB on the upper side of the sense amplifier, and widens the minute signal of the memory cell connected to the selected sub-word line SWL.
  • the signal is transmitted to the local input / output lines L101 and LI01B through the switch circuits (Q12 and Q13).
  • the local input / output lines LI 01 and LI 01 B are connected to a main input / output line MI 0 via a switch circuit I ⁇ SW composed of N-channel type MOS FETs Q 19 and Q 20 provided in the cross area 18. , MI 0 B.
  • the so-called analog gate in which a P-channel MOS FET is provided in parallel with the omitted power MOSFETs Q20 and Q20, can achieve higher speed at any time.
  • the input terminal of the main amplifier MA included in the read / write circuit 61 and the output terminal of the write amplifier WA are connected to the main input / output 10 and MIOB.
  • the column switch circuit is configured such that a plurality of pairs of complementary bit lines BL and BLB are changed to a plurality of pairs of input / output lines LI 01 and 1018 corresponding to the selection signal YS 102 and LI. 02B and so on. Therefore, in each of the sub-arrays selected by the selection operation of one main word line, the plurality of pairs of column switch circuits provided corresponding to the pair of sense amplifiers provided on both sides thereof. Selects a plurality of pairs of complementary bit lines, as shown in FIG. In each of the memory arrays divided into right and left as described above, memory access in units of 72 bits is enabled.
  • the main amplifier MA and the light amplifier WA included in the above-described re-driving circuit 61 perform data input / output between the SRAM macro and the main amplifier MA.
  • a total of 288 read-write circuits are divided into 144 upper and lower halves, each of which is divided into two halves, each with a SRAM macro. Will be forwarded,
  • FIG. 5 is a schematic layout diagram of an embodiment of a semiconductor integrated circuit device equipped with a dynamic RAM according to the present invention.
  • the memory array capacity corresponding to 1/4 of the memory array section in FIG. 1 is shown ; that is, the memory cell array is 4 ⁇ 9 as shown in an enlarged view in FIG.
  • Two memory cell arrays are formed by such a sub-array group, and a main amplifier and a noise suppression storage node area are provided at the center of the two memory cell arrays.
  • the main amplifier section shown in the figure includes the main amplifier MA, the light amplifier WA, and the read-write control circuit RWC as described above. Each of these circuits has an operating voltage VDD and a circuit ground potential VSS. A storage node region for noise suppression is provided in common between power supply lines that provide the following. In other words, the power supply voltage line V DD coupled to the main amplifier MA, the light amplifier WA, and the lead light control circuit R W C and the circuit ground line V S S are provided with noise suppression capacities.
  • the noise suppression capacitor is composed of a plurality of capacitors with the same storage node layer as the information capacity of the dynamic memory cell.
  • the storage node layer which is commonly connected by a diffusion layer formed on the surface of the semiconductor substrate via a contact portion, is similar to Ta205 formed on the surface.
  • Such an insulating film dielectric film
  • the main amplifier MA, the write amplifier WA, and the read / write control circuit RWC function to absorb noise generated when the respective circuits operate. .
  • FIG. 6 shows a schematic cross-sectional structural diagram of an embodiment of a dynamic memory cell and its peripheral circuit (logic circuit).
  • the storage capacitor of the memory cell has a so-called concave crown (CROWN) configuration, in which a storage node SN composed of a polysilicon layer and an insulating film (dielectric film) such as Ta205 are used to form a plate electrode PL.
  • the above storage node SN is connected to one of the source and drain of the address selection MOS FET via a storage controller SNCT composed of tungsten W and a plug PLUG composed of a polysilicon layer:
  • the other source and drain of the address selection MOS FET are shared for the two memory cells and connected to the bit line composed of the first metal layer M1 via the bit line connection BLCT.
  • the bit line Ml is made of a metal material such as tungsten W.
  • the gate electrode of the MOS FET is formed of the first polysilicon layer FG, and the sub-gate line as described above. Formed integrally with,
  • the MOS FET in the peripheral circuit (logic) section has a gate insulating film that is thinner than that of the MOSFET, which is not particularly limited. As a result, as described above, a high-speed operation can be performed even with a low-amplitude input signal formed by the power supply voltage VDD such as 1.8 V as described above.
  • the gate insulating film is formed to be thick, and the area where the gate insulating film is formed is formed.
  • a large threshold voltage such as about 1.8 V is provided, which reduces the leakage current when it is off and reduces the c which is adapted to increase the retention time of the memory Kyabashi evening accumulated information charges
  • FIG. 7 is a schematic cross-sectional structural view of an embodiment of a noise suppression capacitor used in the present invention.
  • the plate electrode PL, the dielectric film, and the storage node SN have the same structure as the storage capacity of the memory cell.
  • the storage control SNCT and the plug PULG have large diameters. Three examples of such large diameter storage control SNCT and PULB PULG are shown in (A) or (C).
  • a plug PULG for making an electrical connection with the diffusion layer n2 is shared by the storage nodes SN arranged in the X direction in the figure.
  • the storage controller SNCT that connects the plug PULG and the storage node SN is separated corresponding to each storage node SN.
  • the storage controller SNCT is different from the storage controller SNCT. The diameter is increased up to the size of the bottom surface of the zinc SN.
  • the storage control SNCT for connecting the plug PULG to the storage node SN also extends in the X direction in the figure. It is common to the storage nodes SN that line up. As is clear from the cross-sectional views as viewed from the Y direction in FIGS. 7 (A) and (B), the storage nodes SN arranged in the X direction, and the storage controllers SNCT and plugs provided correspondingly.
  • PULG is constructed by separating those adjacent to each other in the Y direction.
  • FIG. 7 (C) a storage node SNCT and a plug PULG are also separately formed corresponding to the storage node SN.
  • the difference from the storage capacity is that the storage node is enlarged to the size of the bottom surface of the storage node SN and the diameter is increased, and the storage controller as described in (A) to (C) above is used.
  • the bit line connection BLCT that connects to the bit line like a memory cell is not formed, so the size is increased as described above and the parasitic resistance is reduced. It is not a necessary condition when viewed as a noise countermeasure capacity according to the present invention, that is, the force is a desirable form because of simple noise absorption.
  • the structure of the memory cache as shown in FIG. A configuration in which a plurality of capacitors are connected in parallel by the diffusion layer n10 may be used as it is.
  • FIG. 8 is a schematic plan view showing an embodiment of a noise suppression calibrator used in the present invention.
  • a plan view corresponding to FIG. 7 (A) or (B) is shown.
  • Those located on the outer peripheral portion of the capacity are formed slightly larger in size.
  • the plug PULG or the storage control SNCT is shared in addition to the above, the plug PULG formed on both ends (upper and lower ends in the same figure) in the shared direction and the plug PULG or the left or right both ends are formed.
  • the storage control SNCT is designed to be large in order to correct the rounding of the element butter in semiconductor exposure technology,
  • the plurality of storage nodes SN are connected in parallel by the diffusion layer L provided on the semiconductor substrate side to form one electrode, and the
  • the other electrode is formed by forming the remote electrode PL.
  • a relatively large capacity such as a storage capacity of a dynamic memory cell, which has a small memory capacity, is used, and the power noise is absorbed by connecting them in parallel. It forms a capacitor with a capacitance value,
  • FIG. 9 shows a schematic plan view of an embodiment of a noise suppression device used in the present invention.
  • a plate electrode PL of a storage capacitor of a dynamic memory cell has a sense amplifier. Operation of 1/2 of WE voltage is supplied. For example, when operating at the power supply voltage VDD, a voltage such as VDD 2 is supplied. Therefore, the high level corresponding to the power supply voltage VDD and the low level power such as the circuit ground potential VSS and the stored information power are written. In this case, only VDD / 2 voltage is applied in any case., If such a storage capacity is used as it is as a power noise countermeasure capacitor as described above, a voltage twice as large as VDD is applied. , May cause reliability problems
  • the flat electrode PL The diffusion layer L forming the other electrode of the first capacitor in which the power supply voltage VDD is applied to the wiring layer forming the bit line BL is connected to the wiring layer forming the bit line BL by the connection portion LCNT.
  • the first metal wiring layer M 1 is connected to the first metal wiring layer M 1 through the through hole B LTH
  • the second capacity plate electrode PL is connected to the first metal wiring layer M 1 through the through hole BLTH.
  • the diffusion layer L forming the other electrode of the second capacitor is connected to the wiring layer forming the bit line BL by the connection portion LCNT, and the circuit ground is connected to the wiring layer BL. It supplies the potential VSS (GND).
  • VSS ground
  • the power supply voltage can be reduced while using a low withstand voltage device such as the storage capacity of a dynamic memory cell. It can be used as a noise countermeasure capacitor between VDD and the circuit ground potential VSS,
  • FIG. 10 shows an equivalent circuit diagram of the noise countermeasure capacitor shown in FIG. 9.
  • the sub-array has a configuration of 256 ⁇ 256 as described above, one capacitor is provided.
  • the 256 sub-line is connected to 256 memory cells. Therefore, it is possible to form a capacitor in which 256 storage capacitors are connected in parallel by using the region where the sub-word lines corresponding to the sub-arrays are formed.
  • the capacitance for noise suppression is reduced. It is formed,.
  • the capacitance value of the memory capacity is as small as about 30 fF, the large number of these capacitors are connected in parallel as described above, so that the main amplifier MA and the light amplifier WA operate. It is possible to realize a relatively large capacitance value that reduces the relatively large noise generated in the power supply lines VDD and VSS. '' In this case, the resistance R on the storage node side is the storage controller. Represents the parasitic resistance of the SNCT and the plug PULG
  • FIG. 11 is a plan view of an embodiment of the main amplifier 'section. You. In the main amplifier section, a capacitor for suppressing power supply noise is formed in the center, and the main amplifier section and the array are mirrored as shown in FIG.
  • the main amplifier consists of a main amplifier (Main Amp), a write amplifier (Write A immediately), and a control circuit (MA / WA Control) for controlling these amplifiers.
  • Main Amp Main Amp
  • write A immediately write A immediately
  • control circuit MA / WA Control
  • FIG. 12 is a plan view showing an embodiment of the main pump section.
  • a plan view centering on the power supply line is shown, and the power supply lines VDD and VSS are paired corresponding to the main amplifier and the light amplifier and the control circuit in the two-stage configuration.
  • the P-channel that constitutes the main amplifier, the light amplifier, and the control circuit is used.
  • a knock-bias voltage supply line VDBB that places the source and the well of the MOSFET in a reverse-biased state in the N-well region where the type M 0 SFET is formed and the P-well region where the N-channel MOSFET is formed And VSBB will be provided.
  • the one back bias voltage supply line V SBB is provided commonly at the center of the two-stage circuit.
  • the power supply voltage VDD is applied to the N-well region of the main embed ′.
  • a higher back bias voltage VDBB is applied, and a negative voltage VSBB lower than the circuit ground potential is applied to the P-well region.
  • VDBB higher back bias voltage
  • VSBB negative voltage VSBB lower than the circuit ground potential
  • the sub-threshold leakage current (tailing current) flowing through the P-channel MOSFET and the N-channel M0 SFET that are turned off is significantly reduced by more than one digit, and the current consumption during non-operation. Can be greatly reduced ..,
  • the main amplifier when the main amplifier operates, that is, when the read-Z write operation is performed on the dynamic RAM, the same potential as the power supply voltage VDD is supplied to the N-pole region of the main amplifier. Then, the ground potential VSS of the circuit is applied to the P-well region. As a result, the source of the P-channel MOSFET and the N-channel MOSFET have the same potential, and the threshold voltage is reduced. A large current can flow even with a small input voltage, and high-speed read / write operation can be realized.
  • Two noise suppression capacitors are provided at the center of the main amplifier, and the first capacitor is connected in series by being connected at the center.
  • the first capacitor is connected to the power supply voltage VDD and the second The capacitor is connected to the ground potential VSS of the circuit.
  • the power supply voltage VDD and the ground line VSS which are formed by connecting these two capacitors in series, are connected via wiring that extends in a direction orthogonal to the direction in which the capacitor extends.
  • the power supply voltage line VDD of the two-stage main amplifier and the ground line VSS of the circuit are interconnected.
  • the main amplifier section is formed corresponding to the array, the noise suppression capacity and the noise suppression capacity are also an array. Therefore, it is possible to arrange the main amplifier section between the arrays, and to form a noise suppression capacitor in the center using the storage capacity of the dynamic memory cell. In this case, a capacitance having a large capacitance value can be efficiently formed with a small area in the layout.
  • FIG. 13 is a timing chart for explaining an example of the write operation of the dynamic RAM unit of the semiconductor integrated circuit device according to the present invention.
  • the signal is divided into a control system and a data system.
  • the control system consists of a write amplifier clock signal CLK1, a latch signal A and a latch output B, and a write pulse C formed thereby. It consists of a clock CLK 2 to capture the data, write data D from the logic circuit (SRAM), its latch output E, and write data transmitted to the memory cells. That is, the data to be written is determined by the clock CLK2, and the write data F to be supplied to the memory cell by the write pulse C of the self-control system is output.
  • FIG. 14 is a timing chart for explaining an example of the read operation of the dynamic RAM unit of the semiconductor integrated circuit device according to the present invention.
  • the control system consists of a select clock signal CLK3, a select signal G from a logic circuit, a decoder signal H, a decoder clock signal CLK4, and a decoder latch signal I.
  • the overnight system consists of an output clock signal CLK5, main amplifier output data J, selected output data K, and output data M to the logic circuit.
  • FIG. 15 is a schematic layout diagram of another embodiment of the semiconductor integrated circuit device equipped with the dynamic RAM according to the present invention.
  • the memory units 101, 102 constituted by the dynamic memory cells are arranged with respect to the longitudinal direction of the chip 100 (vertical direction in FIG. 14) as in FIG.
  • the storage units 102, 102 divided vertically into two, and vertically divided into two, are respectively four memory array units 101A, 101B, 101C, 101 D and 102A, 102B, 102C, 102D (hereinafter referred to as DRAM macros).
  • Each DRAM macro is the same as each memory array section in Fig. 1. The description is omitted.
  • the control human input terminals and data input / output terminals TS of the DRAM macros 101A-101D and 102A-A02D are arranged on the CEN side of the chip center.
  • SRAM macros SM1 to SM8 are provided as buffer memories in the chip center part CEN; and between the storage units 101 and 102, the SRAM macros SM1 to SM8 are provided.
  • LOG1, LOG2 and LOG3 for controlling the input and output of data are arranged. That is, the above-mentioned logic part LOG2 and the above-mentioned SRAM macros SM1-SM4, and the above-mentioned logic parts LOG3 and LOG3
  • the first and second input / output circuits (I / O circuits) 1/01 and I / 02 that input / output data to / from external terminals are connected between the SRAM macro SM5 and SM8, respectively.
  • each DRAM macro 101 A 101 D, 102 A—102 D corresponds to the first and second input / output circuits I ZO 1, I / 02 are arranged almost in parallel.
  • the DRAM macro 101 A-101D, the input / output circuit I / 1 and SRAM macro SMI SM4 and DRAM macro 2 0 1 A— 201 D, I / O circuit IZO2 and SRAM macro SM5-SM8 are arranged in line symmetry.
  • the I / O circuits 1/01 and I / 2 have the same Evening C is included ;
  • the L distributed to all macros varies in the wiring length of signals aggregated from all macros.
  • the average distance between each DRAM macro 101A 101D and 102A-1102D can be reduced, and the latency can be reduced. It will be possible.
  • a pair of the DRAM macro 101A and the SRAM macro SM1 is arranged based on the pair, symmetrically with respect to the line L11, and the DRAM macros 101A, 102A, SRAM macro SMI, 3] ⁇ 5 is laid out in line symmetry with respect to 12, 2, L13, and LI4, so that the SRAM macro uses the buffer memory of the DRAM macro DRAM macros and SRAM macros (101 A and SM 1, 101 B and SM 2/101 C and SM 3/101 D and SM 4 Z 201 A, SM5Z102B, SM6 / 102C, SM7 / 102D, and SM8) can have a uniform distance, minimize signal delays, and reduce latency. be able to.;
  • FIG. 16 is a schematic layout diagram of another embodiment of the semiconductor integrated circuit device equipped with the dynamic RAM according to the present invention.
  • the SRAM port at the center is omitted in the embodiment of FIG. 1, and the input / output circuits I / 01 and I / 02 are connected to the DRAM macro 101A-1101D, 1 0 2 A-1 0 2 D Control input terminals and data input / output terminals TS are arranged in parallel and symmetrically. This makes the distance between the DRAM macro and the corresponding I / O circuit uniform.
  • FIG. 17 is a schematic layout diagram of still another embodiment of a semiconductor integrated circuit device equipped with a dynamic RAM according to the present invention.
  • a central portion of a chip is shown.
  • I / O circuits I / O 1 and I / O 2 are grouped together and the SRAM macro SM1 SM 8 is connected to the DRAM macro 10 1 A-10 1 D, 10 2 A 1 0 2 D one-to-one (or (1: N) and by symmetrically arranging the DRAM macro, the delay between the DRAM and the SRAM can be minimized.
  • Amplification MOSFET of a sense amplifier that amplifies the minute voltage read from the dynamic memory cell to the bit line, a column switch for selecting the bit line, a memory array including a MOSFET, and the column switch
  • a dynamic memory cell comprising: a read-write section including a main amplifier for reading storage information of a selected memory cell; and a logic circuit section for performing data input / output operation with the read-write section.
  • a first electrode corresponding to a plate electrode having the same structure as that of the storage cache of the first embodiment, and a second electrode having a plurality of storage nodes shared by the storage cache and a second electrode having the same structure.
  • the above-mentioned memory arrays By providing the above-mentioned memory arrays on both sides so as to sandwich the above-mentioned read / write section, there is obtained an effect that the above-mentioned cable carrier can be efficiently formed corresponding to the memory arrays.
  • (3) By providing a write amplifier and a read Z-write control circuit further in the self-reliable drive section, the layout of the memory access path to the memory array section can be rationally arranged, and the capacity for power supply noise suppression This can contribute to the reduction of noise during lighting.
  • the above-mentioned sub-line is a hierarchical one-line system, such as a plurality of sub-lines, which are commonly assigned to the main line and the main line.
  • the gate of the dynamic select memory cell is connected to the gate of the dynamic select memory cell, and the sub-driver which receives the signal of the main line and the signal of the sub-node select line is used for the above operation.
  • One of the sub word lines is selected, and the memory array is divided and configured by the sub word driver and the sense amplifier. The effect can be obtained if the operation can be stabilized and high reliability can be exhibited effectively while achieving high-speed operation.
  • a peripheral circuit constituting an address selection circuit for the bit line or word line is arranged between the memory array section and a logic circuit section, and is composed of the plate electrode having the same structure as that of the storage capacitor.
  • a first electrode, a second electrode in which a plurality of storage nodes of the storage capacitor are shared, and two capacitors each having the same are connected in series to form a connection between the peripheral circuit and the logic circuit unit.
  • the influence of noise between the peripheral circuit unit and the logic circuit unit can be reduced by connecting the series circuit of the two capacitors between the operating voltages Is obtained.
  • a data input / output circuit for inputting / outputting data to / from an external terminal of the semiconductor integrated circuit device;
  • the storage node of the storage capacitor is connected in series with the second electrode, which has a plurality of shared nodes, and two capacitors each having a second electrode.
  • the semiconductor substrate is formed in the same process as the source and drain diffusion layers of the address selection MOSFET and commonly connects a plurality of storage nodes corresponding to the plate electrodes.
  • a first electrode made of a conductive polysilicon layer formed so as to join the storage node to the dielectric film, a conductive layer having one end connected to the diffusion layer; And a contact part connecting the first electrode and the second electrode to form a capacitor for power supply noise suppression by using the same process as the memory cell.
  • connection portion and the second electrode By forming the connection portion and the second electrode to have the same size as the bottom surface of the first electrode, the internal resistance as a capacitor can be reduced, so that the noise reduction effect can be enhanced. '
  • a memory cell array including a plurality of potential lines, a plurality of bit lines, and a plurality of dynamic memory cells provided at intersections of the plurality of potential lines and the bit lines.
  • a plurality of sense amplifiers connected to the plurality of bit lines for amplifying a signal read from the dynamic memory cell, and a common data provided commonly to the plurality of bit lines.
  • a power switch for selectively transmitting signals obtained on the plurality of bit lines to the common data line; a main amplifier for amplifying a signal obtained on the common data line; A pair of power supply lines connected to the main amplifier for supplying a power supply voltage to the main amplifier; a stabilization circuit including a capacitor provided between the pair of power supply lines; Each memory cell is described
  • One electrode of the storage capacitor is connected to a corresponding bit line via a source / drain path of the selected MOS FET, and the other electrode is provided on a predetermined substrate formed on a semiconductor substrate.
  • One electrode of the capacitor is formed in the plate electrode forming step in correspondence with the shape of the plate electrode, and the one electrode is formed in the predetermined shape, thereby achieving high integration of the semiconductor integrated circuit device.
  • a memory cell array including a plurality of potential lines, a plurality of bit lines, and a plurality of dynamic memory cells provided at intersections of the plurality of potential lines and the bit lines.
  • a plurality of sense amplifiers connected to the plurality of bit lines and extending a signal read from the dynamic memory cell; and a common data line provided in common to the plurality of bit lines.
  • a power switch for selectively transmitting signals obtained on the plurality of bit lines to the common data line, a main amplifier for amplifying a signal obtained on the common data line, and a main amplifier connected to the main amplifier.
  • a pair of power supply lines for supplying a power supply voltage to the main amplifier; and a voltage stabilization provided between the pair of power supply lines.
  • a plurality of memory cells each including a storage capacity and a selection MOSFET, and one electrode of the storage capacity corresponds to a source / drain path of the selection MOSFET.
  • the other electrode is connected to a plate electrode of a predetermined shape formed on a semiconductor substrate, and the first electrode is connected in series between the pair of power supply lines as the voltage stabilizing circuit.
  • the third and fourth capacitive elements are first electrodes having the above-mentioned predetermined shapes, respectively, to achieve high integration and high-speed operation of the semiconductor integrated circuit device, thereby achieving stable operation and high reliability. Can be realized, ,
  • the first electrodes of the first and third capacitance elements are connected to one of the pair of power lines, and the second electrodes of the first and third capacitance elements are connected to the second and third electrodes.
  • the configuration of the memory array can adopt various embodiments.
  • the word line is configured by a word shut-down system in addition to the above-described hierarchical single-line system.
  • memory memory is a dynamic memory cell Anything can be used as long as it is formed in the same process as the memory capacity.
  • INDUSTRIAL APPLICABILITY The present invention can be widely used for a semiconductor integrated circuit device including a dynamic RAM, an internal logic circuit for controlling read / write operations thereof, a buffer memory, and the like. Industrial use ⁇ t raw
  • the present invention can be widely used for a semiconductor integrated circuit device having a dynamic RAM, an internal logic circuit for controlling the read / write operation of the RAM, a buffer memory, and the like.

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Abstract

L'invention concerne un dispositif à circuit intégré en semiconducteur comprenant une matrice mémoire équipée d'un transistor MOS amplificateur d'amplificateur de lecture, permettant d'amplifier une microtension lue sur une ligne de binaire depuis une cellule de mémoire dynamique, et un transistor MOS de commutation de colonne, permettant de sélectionner la ligne de binaire, ainsi qu'une unité à lecture et écriture, permettant de lire l'information enregistrée dans une cellule de mémoire sélectionnée via la commutation de colonne, ladite unité comportant un amplificateur principal. Le dispositif comprend en outre une unité de circuits logiques pour l'entrée et la sortie des données dans/depuis l'unité à lecture et écriture. Deux condensateurs présentant chacun une première électrode qui correspond à une électrode à plaque dont la structure est identique à celle d'un condensateur de mémorisation de la cellule de mémoire dynamique, et une seconde électrode comprenant plusieurs noeuds communs de mémorisation du condensateur de mémorisation, sont disposés en série et occupent une position adjacente à celle de l'unité à lecture et écriture, et le circuit série des deux condensateurs est relié de manière à recevoir une tension de fonctionnement de l'unité à lecture et écriture.
PCT/JP1999/006989 1999-02-23 1999-12-13 Dispositif a circuit integre en semiconducteur WO2000051184A1 (fr)

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JP2002176153A (ja) * 2000-12-05 2002-06-21 Fujitsu Ltd 半導体記憶装置
JP2016528727A (ja) * 2013-07-11 2016-09-15 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ ビットセルおよび論理区画を有するモノリシック３次元（３ｄ）ランダムアクセスメモリ（ｒａｍ）アレイアーキテクチャ
CN113131939A (zh) * 2021-04-22 2021-07-16 中国人民解放军国防科技大学 电流读出电路及忆阻器阵列列电流读出电路

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US6191990B1 (en) 2001-02-20
KR20010113705A (ko) 2001-12-28

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