WO1995024037A1 - Procede et appareil de codage de signaux numeriques, support d'enregistrement de signaux numeriques et procede et appareil de decodage de signaux numeriques - Google Patents
Procede et appareil de codage de signaux numeriques, support d'enregistrement de signaux numeriques et procede et appareil de decodage de signaux numeriques Download PDFInfo
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- WO1995024037A1 WO1995024037A1 PCT/JP1995/000305 JP9500305W WO9524037A1 WO 1995024037 A1 WO1995024037 A1 WO 1995024037A1 JP 9500305 W JP9500305 W JP 9500305W WO 9524037 A1 WO9524037 A1 WO 9524037A1
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- 238000012937 correction Methods 0.000 claims abstract description 78
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- 230000003111 delayed effect Effects 0.000 description 19
- 230000001934 delay Effects 0.000 description 8
- 238000001514 detection method Methods 0.000 description 8
- 238000000926 separation method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000005236 sound signal Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 1
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Definitions
- the present invention relates to a digital signal encoding method and apparatus, a digital signal recording medium, and a digital signal decoding method and apparatus.
- the present invention relates to a digital signal encoding method and apparatus, a digital signal recording medium, a digital signal decoding method and apparatus, and applies to a method for encoding and decoding a digital signal by adding an error correction code. It is suitable.
- FIG. 14 shows the CD signal format.
- One frame consists of 1 byte of subcode and 24 bytes of actual data, and 4 bytes of C1 and C2 error correction codes (CIRC (Cross Interleaved Reed-Solomon Code)), for a total of 33 bytes. Have been. Also, a frame synchronization signal is added at the beginning of one frame. As a result, the ratio of the error correction code to the total data amount excluding the subcode, that is, the redundancy is 25 bytes (8 bytes / 32 bytes).
- CIRC Cross Interleaved Reed-Solomon Code
- Figure 16 shows the configuration of this CD encoding / decoding device.
- the encoding device The digital audio data is input to the CIRC encoding circuit 1 in units of 6 samples of each of the L and R channels, ie, 24 bytes, as one unit.
- This CIRC encoding circuit 1 is configured by a circuit as shown in FIG. That is, the even-number sampler delay circuit 21 and the scrambler circuit 22 delay the data of the even-numbered samples by two frames, respectively, and rearrange the data. This is because when an uncorrectable error occurs, an uncorrectable and missing portion of the adjacent data is interpolated so as to make it inaudible.
- the C2 code encoding unit 23 calculates and adds 4 bytes of C2 parity to the original code of 24 bytes.
- Interleaver 24 applies an interleave with a maximum delay of 108 frames.
- the C1 code encoder 25 calculates and adds 4 bytes of C1 parity to 28 bytes including the original code and C2 parity, and as a result, the total data length becomes 32 bytes. become.
- the odd symbol delay circuit 26 further delays only the odd symbol by one frame. The reason for the delay is to ensure that if a random error occurs over two bytes, the effect will be limited to one symbol on one C1 code sequence.
- the inverter 27 inverts the polarity of the parity so that if all data becomes 0 due to an error, it is determined that there is no error.
- the sub-code adding circuit 2 adds a 1-byte sub-code to the CIRC encoded output obtained in this manner every 32 bytes.
- the codes S 0 and S 1 indicating the above-mentioned sector head are also added as subcodes.
- the signal is EFM-modulated by a next EFM (Eight Height Teen Modul ation) modulation circuit 3, and a frame synchronization signal is added to the beginning of the frame by a frame synchronization signal addition circuit 4, so that cutting is performed.
- the decoding device performs the reverse process of the encoding as the decoding.
- Sand The signal read from the disc 6 passes through the RF amplifier 7 and is separated by the frame synchronization signal detection / separation circuit 8 where the frame synchronization signal is detected and separated.
- EFM demodulation is performed by the EFM demodulation circuit 9
- the subcode detection / separation circuit 10 detects and separates the first subcode of one frame, and is input to the CIRC decoding circuit 11.
- the subcode detection / separation circuit 10 determines the head of the sector by detecting the codes S0 and S1.
- This CIRC decoding circuit 11 is composed of a circuit as shown in FIG. 18 and receives 32 bytes for one frame.
- the even-number symbol delay circuit 31 delays the even-numbered symbol out of 32 bytes of the] frame by one frame.
- the next parity inversion circuit 32 inverts the parity.
- the 1-code decoding unit 33 performs error correction processing using the (: 1 code. From this, 28 bytes excluding the C 1 parity ⁇
- the C2 code decoding unit 35 performs error correction processing using the C2 code, so that 24 bytes excluding the C2 parity are transferred to the next descrambling circuit.
- the data is sent to 3 and the scramble is deciphered, and the odd-sample delay circuit 37 delays the odd-numbered sample of the de-scrambled data by two frames, and thus one frame. 24-byte data is output.
- the horizontal direction is a C 1 code sequence, and error correction by the C 1 code is performed in this order.
- the even symbol delay circuit 31 has D 0, D 1, D 2. ... is input.
- the even-numbered symbols that is, D 1, D 3, D 5,... Are delayed by one frame, so that at an input of the C 1 code decoding unit 33 at a certain point in time.
- the output from the C1 code decoder 33 is delayed by up to 108 frames, so that the input of the C2 code decoder 35
- the symbol sequence extracted every four symbols of the C1 code sequence is input as a C2 code sequence. . Therefore, in order to perform error correction using the C2 code, it is necessary to read out 108 symbols of the C1 code sequence from the disk.
- the frame of the C1 code sequence required for error correction of the C2 code sequence is called an interleave constraint length, and in the case of a CD, the interleave constraint length is 108 frames. It becomes.
- CIRC used in CDs is an error correction code that is effective for both random errors and burst errors, but its correction capability is limited, and it is necessary to record digital signals at high density. Then, it is easy to get uncorrectable. Even if more data is to be recorded on the disc, the ratio of the error correction code to the total data amount, that is, the redundancy, has already been determined, so the amount of data that can be recorded is limited. There is.
- the CD standard does not have information that distinguishes the order of frames. Therefore, if several frames cannot be read continuously due to a burst error, the lost There is no way to know the number of frames, and as a result, there was a problem that the C2 code could not be corrected and eventually became uncorrectable. Disclosure of the invention
- the present invention has been made in view of the above points, and when an error correction code is added to a digital signal to encode and decode the digital signal, the error correction capability can be improved with a simple configuration and the redundancy is improved. It is intended to propose a digital signal encoding method and apparatus, a digital signal recording medium, and a digital signal decoding method and apparatus capable of reducing the degree.
- the present invention provides a digital signal encoding method for encoding a digital signal with an error correction code by using at least a first code sequence of an input digital signal. The obtained first parity is added to the input digital signal, and a second code sequence corresponding to a plurality of symbols extracted one by one from each of a plurality of adjacent first code sequences. Is added to the input digital signal, and the input digital signal to which the first and second parities have been added is used as the recording medium for the arrangement of the symbols of the second code sequence. The symbols are arranged so that they do not match the arrangement of the above symbols.
- a digital signal encoding apparatus using at least a first code sequence of an input digital signal.
- Means for adding the second parity obtained by the above to the input digital signal, and the input digital signal to which the first and second parity are added are arranged on the recording medium by the arrangement of the symbols of the second code sequence.
- a means for arranging the symbols so as not to match the arrangement of the above symbols is provided.
- the encoded digital signal is an input digital signal.
- a second code sequence corresponding to a plurality of symbols extracted by shifting one symbol each from a plurality of adjacent first code sequences is obtained.
- the second parity is added to the input digital signal, and the input digital signal to which the first and second parity are added is converted into a second code sequence symbol sequence on the digital signal recording medium. It is generated by ffi-array so that it does not match the arrangement of symbols.
- At least a first parity obtained using the first code sequence of the input digital signal is added to the input digital signal, and a plurality of adjacent first code sequences are added.
- the second parity obtained by using the second code sequence corresponding to a plurality of symbols shifted by one symbol from the input digital signal is added to the input digital signal, and the first and second The coded digital signal generated by arranging the input digital signal to which the parity is added so that the arrangement of the symbols of the second code sequence does not match the arrangement of the symbols on the recording medium is decoded.
- the coded digital signal supplied from the transmission path is rearranged, and the rearranged coded digital signal is rewritten using a first parity. Performs the first error correction in the direction of the first code sequence, and converts the rearranged coded digital signal in the direction of the second code sequence using the second parity. To be performed.
- At least a first parity obtained using the first code sequence of the input digital signal is added to the input digital signal, and a plurality of adjacent first digital signals are added.
- a second parity calculated using a second code sequence corresponding to a plurality of symbols shifted by one symbol from the code sequence is added to the input digital signal, and the first parity is calculated.
- a code generated by arranging the input digital signal to which the second parity is added so that the sequence of the symbols of the second code sequence does not match the sequence of the symbols on the recording medium.
- a means for rearranging the coded digital signal provided from a transmission path, and No pa Te Means for performing the first error correction in the direction of the first code sequence using the parity, and reordering the coded digital signal in the direction of the second code sequence using the second parity. Means for performing error correction of item 2 are provided.
- the code length, the number of correction variances, and the length of the interleave constraint are increased from those of the compact disc standard.
- the redundancy can be reduced as compared with the compact disc standard, and the amount of recordable data can be increased.
- the error correction capability can be improved with a simple configuration, and the redundancy can be reduced.
- FIG. 1 shows the C 1 code by the digital signal encoding and decoding method according to the present invention.
- FIG. 3 is a schematic diagram illustrating a configuration of one code length.
- FIG. 2 is a schematic diagram for explaining an L-format interleave.
- FIG. 3 is a schematic diagram used for explaining the S format interleave.
- FIG. 4 is a schematic diagram for explaining a sector structure according to the digital signal encoding and decoding method according to the present invention.
- FIGS. 5A and 5B are schematic diagrams showing the recording order on the disc and the order of the C1 code.
- FIG. 6 is a schematic diagram showing the recording order on the disc and the order of the C1 code.
- FIG. 7 is a block diagram showing an embodiment of a digital signal encoding device according to the present invention.
- FIG. 8 is a block diagram showing a configuration of an L-format error correction code encoding processing unit in the digital signal encoding device of FIG.
- FIG. 9 is a block diagram showing the configuration of an S-format error correction code encoder in the digital signal encoder of FIG.
- FIG. 10 is a block diagram showing an embodiment of a digital signal decoding apparatus according to the present invention. It is.
- Fig. 11 is a schematic diagram used to explain the Basteller's correction process.
- FIG. 12 is a block diagram showing a configuration of an L-format error correction code decoding processing unit in the digital signal decoding device of FIG.
- FIG. 13 is a block diagram showing a configuration of an S-format error correction code decoding processing unit in the digital signal decoding device of FIG.
- FIG. 14 is a schematic diagram showing the configuration of one code length of the C1 code in a conventional compact disk.
- FIG. 15 is a schematic diagram showing a sector structure of a conventional compact disc.
- FIG. 16 is a block diagram showing a conventional compact disc encoding and decoding apparatus.
- FIG. 17 is a block diagram showing a configuration of an error correction code encoding processing unit of a conventional compact disk encoding device.
- FIG. 18 is a block diagram showing a configuration of an error correction code decoding processing unit of a conventional compact disk decoding device.
- FIG. 19 is a schematic diagram showing the order of recording on a disc and the order of C1 codes in a conventional compact disc.
- the interleave distributes a burst error of several symbols on the disk so that it appears as a random error in the C2 direction.
- the length of the C1 code sequence is set to 1 36 symbols which is considerably longer than 32 symbols of CD.
- the C1 code sequence is as short as 32 symbols, in order to achieve the above object, as described above, a symbol is taken out every four frames of the C1 code sequence and the C2 code sequence is used. are doing.
- the angle between the C 1 code sequence and the C 2 code sequence is Larger cases are called deeper interleaves.
- the C1 code sequence is long, the above object can be achieved without performing deep interleaving.
- the interleave of CIRC used for CD is simply made shallow so that the C2 code sequence becomes the C2 'coded sequence shown in FIG.
- the C 2 ′ code sequence is an interleave in which the interval between adjacent symbols starting from D 0 is 33 symbols. This means that one symbol has been extracted.
- the interval between each symbol of the C 2 ′ code sequence is actually longer than this, and the same purpose as in the case of deep interleaving of CD is obtained. Can be achieved.
- the symbols are adjacent on the 2 'code, such as DO and DL, and 066 and 067, and also on the disk.
- the purpose of the interleave is to disperse errors that are several symbols consecutive on the C2 code, and thus the symbol order on the disk and the symbol order on the C2 'code It is not preferable that they match, and the correction ability of the C 2 'code deteriorates.
- the symbol order on the disc does not match the symbol order on the C 2 'code.
- a format in which the interleave constraint length is increased to improve the burst error correction capability is called an L format, and the constraint length is shortened.
- the format in which the Barsteller correction capability is minimized and the processing speed is increased is called the S format.
- Figure 1 shows the C1 code as a whole in this digital signal encoding method.
- the code length is 136 symbols
- the data is 116 symbols
- the last 8 symbols are C1
- the central 12 symbols are C1.
- 2 Parity At the beginning of the code, a sync detection sync is arranged, and, for example, a 1-bit format ID is arranged following the sync.
- This file The format ID indicates either L format or S format.
- one code length of the C1 code is referred to as one frame.
- the frame ID is allocated to the first symbol of the data following the format ID.
- the frame ID is included in the C1 code, and error correction can be performed by correcting the C1 code.
- Figure 2 shows an interleave in the L format.
- the C2 code has a code length of 128 symbols and is interleaved over 128 C1 codes. Correction using all parity symbols in the C2 code can correct errors in 12 symbols in the C2 code. This is equivalent to 12 C1 codes and can correct up to a burst error of 1632 symbols.
- Figure 3 shows the interleaving using the S format.
- the C 1 code is exactly the same as the L format.
- the C2 code has a code length of 128 symbols, just like the L format, but is interleaved by the 43rd C1 code and has a constraint length of about 1 in the L format. 3 Assuming that errors in 12 symbols in the C2 code can be corrected in the same manner as in the L format, it is possible to correct up to a burst error of four C1 codes, that is, 544 symbols.
- Redundancy is 14.7 [%] in this format, compared to 25 [%] for CD.
- the number of variances is 4 symbols for both C1 and C2, but in this format they are 8 and 12 symbols, respectively, so-called LDC (Long Distance Code), so the correction capability is much higher than for CDs. it can. '
- Figure 4 shows the sector structure in this format.
- One sector consists of 18 C1 codes. Excluding parity, the data portion has 2088 symbols, of which 18 are frame IDs, 18 are sector headers, 4 are strong symbols for error detection code (EDC), and the remaining 2048 are actual data
- EDC error detection code
- 1 sectors is 2 k bytes.
- numbers 0, 1, 2,..., 17 are recorded from the first frame of the sector. This is repeated for each sector.
- FIG. 5A shows the relationship between the C1 code sequence, the C2 code sequence, and the data actually recorded on the disc in this embodiment. Data is read out horizontally and C 1 code correction is performed.
- the C1 code order is represented by i
- the symbol order in the C1 code is represented by j
- the symbol on the disk is represented by Dk.
- the odd-numbered symbols where k is even are arranged in the first half of the C 1 code, and the even-numbered symbols where k is odd are arranged in the second half of the next C 1 code.
- Such a delay can be realized by providing a delay unit 306 in FIG. 8 described later.
- the C1 code is divided into two and the symbols are arranged.
- the symbol is not limited to two and may be divided into four as shown in FIG.
- FIG. 5 (A) the odd-numbered symbols are delayed, but the even-numbered symbols may be delayed.
- the relationship between the C1 code sequence, C2 code sequence, and the data actually recorded on the disk is as shown in Fig. 5 (B).
- the odd-numbered symbols are delayed, as shown in Fig. 5 (A)
- (i, j) in the case of FIG. 5B can be expressed by the following equation.
- FIG. 7 shows the configuration of the digital signal encoding device of this embodiment.
- an L format or an S format is selected by a format switching signal.
- the input is data with the frame ID added at the beginning of the frame.
- the input signal is first input to the memory 101, sent to the error correction circuit 102 in the order of the C1 or C2 code, added with the error correction code, and written again to the memory 101. , And then sent to the EFM modulation circuit 104.
- the memory control unit 103 controls the generation of the memory write address and the read address in accordance with the format selected by the format switching signal.
- FIG. 8 shows a process in which input data is processed by the memory 101 and the error correction circuit 102 in the case of the L format shown in FIG. 5 (A).
- 116 symbols from a0 to a115 are processed as one unit.
- the even-numbered symbols are delayed by one code length in the delay unit 301.
- an interleave is performed by the interleaver 302, the cells are rearranged in the C2 code order shown in FIG.
- the coding section 303 calculates and adds the C2 correction parity.
- 0 7 is recorded in the order of b 0, b 1, b 2.
- the L format of 15 (B) is obtained by using bl, b3, and b instead of providing the delay unit 306 on the b0, b2, b4b132, and b134 sides in FIG. 5 It can be realized by providing it on the side of bl33 and b135.
- FIG. 9 shows the case of the S format as described above.
- the only difference from the L format is the interleaver 402 and the interleaver 404.
- the delay unit 401 is a delay unit 301
- the C2 code encoder 4003 is a C2 code encoder 303
- the C1 code encoder 450 is a C1 code encoder.
- the delay unit 406 has the same configuration as the delay unit 306, and the inverter 407 has the same configuration as the inverter 307.
- the data sent from the memory 101 to the EFM modulation circuit 104 is EFM-modulated.
- the next sync format ID addition circuit 105 selects the sync and the format ID of the selected format Is added. Next, it is sent to the cutting device 106 to produce the disc 107.
- the encoding method of the digital signal according to this embodiment is based on the premise that it is used for recording and reproducing not only computer data but also compressed data of an image. However, care has been taken to ensure that the impossible part does not spread widely. You That is, a C2 code is added after passing through an interleaver so that data is recorded on the disk 107 in the order of the original data, that is, in the order of a0 to a115. After that, the process of returning to the original order is performed by the data reader. Further, a delay unit 301 is provided so that the delay amount of the even symbol and the odd symbol is the same.
- the delay unit 301 is provided to absorb this delay amount.
- the original data order matches the data order recorded on the disc, and the uncorrectable portion of the original data order is shrunk compared to the case of shuffling the original data order like a CD. Expansion can be prevented.
- the delay unit 301 may not be provided.
- the data order recorded on the disc matches the data order of the C1 code sequence, and does not completely match the original data order. Compared to the case of shuffling the data order, the original data order is maintained to some extent, so that the expansion of the uncorrectable portion can be prevented.
- the delay section 507 is not provided on the decoder side.
- the digital signal decoding device is configured as shown in FIG. 10, and the signal read from the disk 107 passes through the: RF amplifier 201, and the sync / format ID detection / separation circuit 2 0 2 sync and format ID are detected and separated. Then, it discriminates between the L format and the S format based on the format ID, and sends a format discrimination signal to the memory control unit 206 at the subsequent stage.
- the data from which the sync and format ID have been removed by the sync / format ID detection / separation circuit 202 are demodulated by the EFM demodulation circuit 203 and taken into the memory 204.
- the memory control unit 206 recognizes the L format or the S format based on the format discrimination signal output from the sync format ID detection / separation circuit 202, and responds accordingly to the memory. It controls the write / read address of the device.
- the data taken into the memory 204 is rearranged in the order of the C1 code, sent to the error correction circuit 205, and the corrected code is written into the memory 204 again.
- the code for which the C 1 code correction has been completed is read out in the order of the C 2 code, similarly corrected by the error correction circuit 205, and written into the memory 204 again.
- the data after error correction is output from memory 204. These controls are performed by the memory control unit 206.
- FIG. 11 shows how the C1 code corrected code is written into memory 204.
- frame 1 the frame with the frame ID of 1 is referred to as frame 1.
- Frames 4, 5, 6, and 7 are written sequentially, and the next four frames are lost with a burst error. Suppose that one code cannot be corrected and correction can be performed again from frame 12.
- the C2 code becomes 4 symbols narrower and cannot be corrected. Take the following measures to prevent this. That is, when the difference between Frame 7 immediately before the burst error and Frames 12 immediately after the burst error is calculated, it is found that the number of lost frames is four.
- the frame ID enclosed in parentheses in the figure indicates the frame missing due to the burst error.
- the memory control unit 20 always monitors the frame ID and writes the C1 code so that the C2 code correction does not fail even if several frames are lost due to the burst error. We switch appropriately.
- FIG. 12 shows a process in which the data is processed by the memory 204 and the error correction circuit 205 in the case of the L format shown in FIG. 5 (A).
- the inverters 501 invert the C 1 and C 2 variances, and the delay section 502 delays the even-numbered symbols by one code length.
- the C1 code is corrected by the C1 code decoder 503, the interleave is performed by the interleaver 504, and the C2 code is corrected by the C2 code decoder 505.
- the data is interleaved by a deinterleaver 506, and the odd-numbered symbols are delayed by one code length in a delay unit 507 to obtain outputs a0 to a11.
- the interleaver 504 is the same as the interleaver 302
- the interleaver 506 is the same as the interleaver 304.
- the L format in Fig. 5 (B) is
- FIG. 1 shows the case of S format as described above.
- the only difference from the L format is the interleaver 604 and the interleaver 606.
- Inverter 6 0 1 is an inverter 5 0
- delay section 6 2 is a delay section 5 0
- C 1 code decoding section 6 0 3 is a C 1 code decoding section 5 0 3
- the C2 code decoding unit 505 and the delay unit 607 are the same as the delay unit 507.
- the delay g (X) of the interleaver 604 is the interleaver 402 and the delay f (X) of the interleaver 606 is the interleave. They are the same as in 404.
- the processing in the delay units and the interleaver shown in FIG. 8 and FIG. 9 is actually performed by the memory control unit 103, and the write address and read address of the memory 101 are actually used. It can be realized by controlling the write timing and the read timing.
- the processing in each of the delay units and the deinterleaver shown in FIGS. 12 and 13 is actually performed by the memory control unit 206, and the write address and the read address of the memory 204 are used. It can be realized by controlling the dress, write timing, and read timing.
- switching between the L format and the S format can be realized by switching the control method of the memory control unit 103 and the memory control unit 206.
- the code length and the number of error correction parities are increased compared to the CD standard, and the error correction capability for random errors and burst errors is significantly improved by increasing the interleave constraint length. Can be improved, and the amount of data that can be actually recorded can be increased by reducing the redundancy compared to the CD standard.
- the digital signal is encoded and decoded with an error correction code. In this case, the error correction capability can be improved with a simple configuration and the redundancy can be reduced.
- formats having the same code length and the same number of error correction parities but differing only in the interleave constraint length are prepared, and the format is determined by the format ID.
- the format ID By identifying the data, it is possible to cope with a plurality of formats without complicating the encoding device and the decoding device.
- recording and reproduction can be performed by mixing multiple formats on a single disc by identifying the format ID.
- the delay amount of the odd-numbered or even-numbered symbols is devised so that the C2 code order and the data order on the disc do not match, thereby preventing deterioration of the burst error correction capability. be able to. Further, by adding the frame ID, even if several frames are continuously lost due to a burst error, the number of the frames can be accurately determined, so that the C2 code correction can be performed without any trouble and the error can be corrected.
- the C1 code I code length that is, 1 frame length is 136 symbols
- C1 parity and C2 parity are 8 symbols and 12 symbols, respectively
- the interleaving is performed.
- the constraint length is 128 symbols, but the length of one frame, parity length, and interleave constraint length are not limited to these, and various types can be selected as necessary. Even if the length is set to half of the constraint length of the L format, the same effect as in the above-described embodiment can be realized.
- the C 1 parity is placed at the end of the code
- the C 2 parity is placed at the center of the code.
- the C1 code length that is, 1 frame length is set to 170 symbols
- C1 parity and C2 parity are set to 8 symbols and 14 symbols, respectively
- the interleave constraint is set.
- the length may be 138 frames
- C 1 parity and C 2 parity may be placed at the end of the code.
- the L format and the S format are selectable, and a format ID for identifying the selected format is provided.
- the L format and the S format are not used. Formats that employ only one of them from the beginning are also included in the scope of the present invention. In this case, no format ID is required.
- the format ID is added to one bit following the sink has been described.
- the arrangement of the format ID is not limited to this, and for example, the format ID is provided inside the sector header. Is also good.
- the frame ID is periodically repeated in units of one sector, the frame ID may be repeated in units of several sectors instead. Alternatively, for example, a period from 0 to 255 may be used independently of the sector. You may make it repeat repeatedly.
- a read-only optical disc such as a compact disc is assumed as a recording medium for digital signals.
- the present invention is not limited to this. It is widely applied to a digital signal encoding method and apparatus, a digital signal recording medium, and a digital signal decoding method and apparatus using a writable medium such as a disk, a magnetic disk, and a magnetic tape. It is suitable.
- the code length and the number of error correction parities are increased, and the interleave constraint length is increased, so that random error and burst error can be prevented.
- Digital signal coding that can improve error correction capability, reduce redundancy compared to the compact disc standard, and increase the amount of data that can be actually recorded.
- a method and apparatus, a digital signal recording medium, and a digital signal decoding method and apparatus can be realized.
- a format is prepared in which the code length and the number of corrections are the same and only the interleave constraint length is different, and the format is identified by the format ID.
- a device that can handle multiple formats without complicating the device, and can record and play back multiple formats in a single medium by identifying them using a format ID.
- a digital signal encoding method and apparatus, a digital signal recording medium, and a digital signal decoding method and apparatus can be realized.
- the delay amount of the odd-numbered symbols is devised so that the C2 code order does not match the data order on the disk. Deterioration can be prevented, and by adding a frame ID, even if several frames are continuously lost due to a burst error, the number of frames can be detected and the C2 code corrected without any trouble.
- a digital signal encoding method and apparatus, a digital signal recording medium, and a digital signal decoding method and apparatus capable of performing error correction can be realized.
- the digital signal encoding method and apparatus of the present invention can be used for a DVD (digital video disk) recording apparatus.
- the digital signal decoding method and device of the present invention can be used for a DVD playback device.
- the digital recording medium of the present invention can be used as DVD.
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AU18245/95A AU681259B2 (en) | 1994-03-01 | 1995-02-28 | Digital signal encoding method and apparatus, digital signal recording medium, and digital signal decoding method and apparatus |
CA002160913A CA2160913C (en) | 1994-03-01 | 1995-02-28 | Digital signal encoding method and apparatus, digital signal recording medium, and digital signal decoding method and apparatus |
BR9505853A BR9505853A (pt) | 1994-03-01 | 1995-02-28 | Processo e aparelho de codificação e de decodificação de sinal digital e meio de registro de sinal digital |
MX9504156A MX9504156A (es) | 1994-03-01 | 1995-02-28 | Metodo y aparato de codificacion de señales digitales, medio de registro de señales digitales y metodo y aparato de descodificacion de señales digitales. |
PL95334663A PL179264B1 (pl) | 1994-03-01 | 1995-02-28 | Sposób i urzadzenie do dekodowania sygnalu cyfrowego PL PL |
EP95909998A EP0696799A4 (en) | 1994-03-01 | 1995-02-28 | METHOD AND DEVICE FOR CODING DIGITAL SIGNALS, DIGITAL RECORDING CARRIER AND METHOD AND DEVICE FOR DECODING DIGITAL SIGNALS |
PL95311310A PL178386B1 (pl) | 1994-03-01 | 1995-02-28 | Sposób i urządzenie do kodowania sygnału cyfrowego |
US08/530,303 US5745505A (en) | 1994-03-01 | 1995-02-28 | Digital signal encoding method and apparatus, digital signal recording medium, and digital signal decoding method and apparatus |
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JP2638248B2 (ja) * | 1990-03-15 | 1997-08-06 | 松下電器産業株式会社 | 光学的情報媒体および再生装置および記録装置および再生方法および記録方法 |
JPH04154222A (ja) * | 1990-10-17 | 1992-05-27 | Canon Inc | 符号化及び復号化装置 |
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-
1995
- 1995-02-28 WO PCT/JP1995/000305 patent/WO1995024037A1/ja not_active Application Discontinuation
- 1995-02-28 AU AU18245/95A patent/AU681259B2/en not_active Expired
- 1995-02-28 CA CA002160913A patent/CA2160913C/en not_active Expired - Lifetime
- 1995-02-28 CN CN95190147A patent/CN1082227C/zh not_active Expired - Lifetime
- 1995-02-28 EP EP95909998A patent/EP0696799A4/en not_active Withdrawn
- 1995-02-28 US US08/530,303 patent/US5745505A/en not_active Expired - Lifetime
- 1995-02-28 KR KR1019950704789A patent/KR100384087B1/ko active IP Right Grant
- 1995-02-28 BR BR9505853A patent/BR9505853A/pt not_active Application Discontinuation
- 1995-02-28 CN CNB011207515A patent/CN1143267C/zh not_active Expired - Lifetime
- 1995-02-28 PL PL95334663A patent/PL179264B1/pl unknown
- 1995-02-28 PL PL95311310A patent/PL178386B1/pl unknown
- 1995-02-28 MX MX9504156A patent/MX9504156A/es unknown
- 1995-05-19 TW TW084104993A patent/TW265493B/zh not_active IP Right Cessation
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JPS60143486A (ja) * | 1983-12-29 | 1985-07-29 | Ricoh Co Ltd | 誤り訂正方式 |
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Title |
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See also references of EP0696799A4 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0766246A1 (en) * | 1995-09-28 | 1997-04-02 | Sony Corporation | Method for recording (sending)/reproducing (receiving) data, apparatus thereof, and data recording medium |
US5841749A (en) * | 1995-09-28 | 1998-11-24 | Sony Corporation | Method for recording (sending) /reproducing (receiving) data, apparatus thereof and data recording medium |
US5870366A (en) * | 1995-09-28 | 1999-02-09 | Sony Corporation | Method for recording (sending) /reproducing (receiving) data, apparatus thereof, and data recording medium |
Also Published As
Publication number | Publication date |
---|---|
AU1824595A (en) | 1995-09-18 |
MX9504156A (es) | 1997-04-30 |
KR960702154A (ko) | 1996-03-28 |
CN1124062A (zh) | 1996-06-05 |
BR9505853A (pt) | 1996-02-21 |
CN1082227C (zh) | 2002-04-03 |
US5745505A (en) | 1998-04-28 |
CA2160913C (en) | 2002-11-19 |
EP0696799A4 (en) | 2000-06-28 |
PL311310A1 (en) | 1996-02-05 |
CA2160913A1 (en) | 1995-09-08 |
CN1143267C (zh) | 2004-03-24 |
TW265493B (ja) | 1995-12-11 |
PL179264B1 (pl) | 2000-08-31 |
CN1332442A (zh) | 2002-01-23 |
EP0696799A1 (en) | 1996-02-14 |
AU681259B2 (en) | 1997-08-21 |
PL178386B1 (pl) | 2000-04-28 |
KR100384087B1 (ko) | 2003-08-25 |
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