WO1995001609A1 - Procede et dispositif de traitment d'images - Google Patents

Procede et dispositif de traitment d'images Download PDF

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Publication number
WO1995001609A1
WO1995001609A1 PCT/JP1994/001067 JP9401067W WO9501609A1 WO 1995001609 A1 WO1995001609 A1 WO 1995001609A1 JP 9401067 W JP9401067 W JP 9401067W WO 9501609 A1 WO9501609 A1 WO 9501609A1
Authority
WO
WIPO (PCT)
Prior art keywords
image
image data
window
foreground
frame buffer
Prior art date
Application number
PCT/JP1994/001067
Other languages
English (en)
Japanese (ja)
Inventor
Seiichi Kajiwara
Shuji Hori
Original Assignee
Sega Enterprises, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sega Enterprises, Ltd. filed Critical Sega Enterprises, Ltd.
Priority to JP7501588A priority Critical patent/JP2891542B2/ja
Priority to EP94919833A priority patent/EP0660266A4/fr
Priority to BR9405493-2A priority patent/BR9405493A/pt
Publication of WO1995001609A1 publication Critical patent/WO1995001609A1/fr
Priority to KR1019950700746A priority patent/KR950703183A/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/10—Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Definitions

  • Patent application title Image processing method and apparatus
  • the present invention relates to an image processing method and an apparatus used in a game machine or the like and capable of rewriting image data in a frame buffer.
  • an image processing device used in a game machine has a plurality of background images (still images) for displaying a background and a foreground image (moving images) for displaying characters appearing in a game. It is displayed on the screen of the scan monitor.
  • Each of the background image and the foreground image has a display priority (hereinafter referred to as a priority), and only a high-priority foreground image or a background image is displayed at a position where they overlap.
  • the priority is determined by the priority number. As an example, an image with a higher priority number is displayed in the foreground.
  • the background image is usually specified in plane units, and the foreground image is specified in character units.
  • a background image BG0 shown in Fig. 13 (a) a background image BG1 shown in (b) and a foreground image FG shown in (c), and the priority number of the background image BG0 is "4". It is assumed that the priority number of the background image BG 1 is “2” and the priority number of the character CHR of the foreground image FG is “6”. Then, when these are superimposed, as shown in FIG. 13 (d), the character CHR—the background image BG0—the background image BG1 appears to be in the foreground.
  • an image area called a window is set for each of the background image and the foreground image, and a transparent processing or an inner or outer window is set for this window.
  • This window processing is processing that forcibly applies transparency processing or color calculation processing to the screen in the specified area of each screen regardless of the priority, and does not display the image of that plane.
  • the background image BG1 may be seen through the background image BG0. This is achieved by setting a window in the transparent area and performing color arithmetic processing inside it.
  • This color calculation process is a process that, when multiple screens overlap, adds the color data of the pixels on the same coordinates of each screen to give the effect that the back image can be seen through the front image. It is.
  • a platform that displays the status of the player (physical strength, play time, etc.) that is not normally displayed when the background is displayed as shown in Fig. 15 (a), such as during a game.
  • the screen displayed when the game stage is cleared may gradually disappear.
  • a window WL is set for each of the foreground image FG and the background images BGO and BG1, and the outside is subjected to the transparent processing. Since neither the foreground image nor the background image is displayed in the area AR2 outside the window WL, a preset monochrome back screen is displayed. Then, by gradually changing the window WL of each screen as shown in (c) to (d), the back screen becomes large and the display screen appears to gradually disappear.
  • Such an image processing device that displays various images using the priority and the window includes a display control unit that outputs the image data of the foreground image and the background image according to the priority number described above, and a control unit that controls the window. And a window control unit.
  • the position of the window is set by the window control unit, and the above-described color calculation processing and transparency processing are performed inside or outside the window.
  • These display control unit and window control unit have internal registers, and commands from the CPU are set in this register.
  • the rectangular window WR is a window as shown in Fig. 15 (c).
  • the coordinates of the start point A and the end point B in the vertical and horizontal directions are defined by the above-mentioned window control. It is obtained by setting in the register of the control unit.
  • the line window WL is a window as shown in FIGS. 16B to 16D and FIG. 17A. That is, in the case of the line window WL, as shown in FIG. 17 (a), the starting point C (CI, C27) And the ending point D (D1, D2,. ) Are stored in a storage means such as a VRAM in advance as a table, and the address of this table is set in the register of the control unit together with the coordinates of the vertical start point E and the vertical end point F.
  • a storage means such as a VRAM in advance as a table
  • a RAM for storing a command for drawing a foreground image FG and image data such as characters of the foreground image FG, and an image data read from the RAM are stored in a monitor.
  • a frame buffer to be displayed corresponding to the screen is provided.
  • a first object of the present invention is to change only predetermined bits of image data written in a frame buffer.
  • An object of the present invention is to provide a frame buffer access method.
  • a second object of the present invention is to provide a frame buffer access method capable of changing a bit of image data corresponding to a shape of an image desired by image data storage means.
  • a third object of the present invention is to provide an image processing method capable of setting a window having a complicated shape without providing special hardware.
  • a sixth object of the present invention is to provide an image processing method capable of displaying an image having a low priority on either the inside or the outside of the window.
  • An eighth object of the present invention is to provide an image processing method capable of performing effective image processing on a screen with respect to any one of the inside and outside of the window.
  • a ninth object of the present invention is to provide an image processing method capable of setting a window corresponding to image data in image data storage means.
  • a tenth object of the present invention is to provide a frame buffer access device capable of realizing the first object.
  • a first object of the present invention is to provide a frame buffer access device capable of realizing the second object.
  • a twelfth object of the present invention is to provide an image processing apparatus S that can realize the third object.
  • a thirteenth object of the present invention is to provide an image processing device capable of realizing the fourth object.
  • a fourteenth object of the present invention is to provide an image processing apparatus capable of changing only a predetermined bit of image data damaged in a frame buffer.
  • a fifteenth object of the present invention is to provide an image processing apparatus capable of setting a window corresponding to the shape of an image stored in image data storage means.
  • a sixteenth object of the present invention is to provide an image processing apparatus which can efficiently realize the above-described image processing method without enlarging a conventional frame buffer area.
  • a seventeenth object of the present invention is to provide an image processing device capable of determining whether or not each view is inside a window.
  • An eighteenth object of the present invention is to provide an image processing apparatus capable of setting a window for each screen of a foreground image and a background image.
  • a nineteenth object of the present invention is to provide a game machine capable of setting a window having a complicated shape without providing special hardware.
  • a second object of the present invention is to provide a game machine which can use both a conventional window whose shape is set in advance and a window having a complicated shape.
  • a second object of the present invention is to provide a game machine capable of changing only a predetermined bit of image data written in a frame buffer.
  • a twenty-second object of the present invention is to provide a game machine capable of setting a window corresponding to the shape of an image stored in image data storage means.
  • a 23rd object of the present invention is to provide a game machine which can efficiently realize the above image processing method without enlarging a conventional frame buffer area.
  • a twenty-fourth object of the present invention is to determine whether each pixel is inside a window or not. It is to provide a game machine which can be used.
  • a twenty-fifth object of the present invention is to provide a game machine capable of setting a window for each screen of a foreground image and a background image.
  • a frame buffer access method is a frame buffer access method for reading image data from image data storage means and writing the image data into a frame buffer. Reading image data already written in an address corresponding to an image of an arbitrary shape from the mbabapa, changing a value of a predetermined bit of the image data read from the frame buffer, The feature is that the address is written again.
  • the first aspect of the present invention having the above configuration, it is possible to change a predetermined bit of image data already damaged in the frame buffer.
  • the frame buffer access method according to the second aspect of the present invention is the frame buffer access method according to the first aspect, wherein the arbitrary shape is defined by a shape of an image read from the image data recording unit. I have. For this reason, a predetermined bit of the image data in the frame buffer can be changed according to the shape of the image stored in the image data storage means.
  • the image processing method is to read out the image data set for each pixel of the foreground image from the first storage unit, develop the image data in a frame buffer, and read the image data from the frame buffer at a predetermined timing. Read out the image data set at least for each pixel of the background image of one screen from the second storage means, and display the image data of the foreground image and the image data of the background image.
  • An image processing method for determining a priority order and generating display display data obtained by combining the foreground image and the background image based on the priority order comprising the steps of: Read out the image data already written in the address corresponding to the image data, change the value of a predetermined bit of the image data read out from the frame buffer, Serial again written to the address on the frame buffer, the frame bar one et one
  • image data having the following formula is used as image data constituting the inside of a window, and image processing is performed on one of the inside and outside of the window.
  • the image processing method according to the invention according to claim 4, wherein the image data set for each foreground image search is read out from the first storage means and developed in a frame buffer, and the image data is read from the frame buffer at a predetermined timing.
  • the image data set for each pixel of the background image of at least one screen is read out from the second storage means, and the image data of the foreground image and the image data of the background image are displayed.
  • the image processing method according to the invention described in claim 5 is the image processing method according to the invention described in claim 3 or 4. And changing the value of the most significant bit of the image data read from the frame buffer. For this reason, the most significant bit, which has no branch in other processing, is used as the predetermined bit, so that there is no need to set a new area, which is efficient.
  • An image processing method is the image processing method according to claim 3, 4, or 5, wherein, as the image processing, at least one of the inside and outside of the window includes a foreground image and a background image. It is characterized in that at least one screen pixel is forcibly made transparent by making it transparent. Therefore, by applying transparency processing to either the inside or outside of the window, an image with a low display priority can be displayed there.
  • the image processing method according to claim 7 is the image processing method according to claim 3, 4, or 5, wherein the image processing includes a pixel other than a transparent pixel in one of the inside and outside of the window. It is characterized in that a color operation including an addition operation is performed on the image data. For this reason, by performing color arithmetic processing on either the inside or outside of the window, an effect can be obtained in which a distant image can be seen through the image in front.
  • the image processing method according to claim 8 is the image processing method according to claim 3, 4 or 5, wherein the image processing is performed on one of an inner side and an outer side of the window.
  • the image processing method according to the ninth aspect of the present invention is the image processing method according to the third, fourth, or fifth aspect, wherein the arbitrary shape is defined by a shape of an image read from the image data storage unit. And Therefore, the window can be set according to the shape of the image stored in the image data storage means.
  • a frame buffer access device S according to claim 10 is a frame buffer access device having a first terminal to which image data storage means is connected and a second terminal to which a frame buffer is connected.
  • Address designating means for designating an address on the frame buffer corresponding to an image of an arbitrary shape; and a frame buffer for reading image data already written from the frame buffer at an address designated by the address designating means.
  • a read unit; a bit changing unit that changes a value of a predetermined bit of the image data read by the frame buffer reading unit; and an access unit that accesses the frame buffer, and the value of the predetermined bit is changed.
  • the frame buffer access device wherein the address designating unit designates an address corresponding to an image read from the image data storage unit. And for this reason, the address corresponding to the shape of the image stored in the image data recording means is specified by the address specifying means, and the predetermined bit of the image data corresponding to the shape of the image is changed. be able to.
  • An image processing apparatus wherein a CPU for issuing a command, the command for displaying a foreground image on a display, and image data set for each pixel of the foreground image are stored.
  • a frame buffer for storing image data corresponding to the foreground image to be displayed on the display, and reading the image data of the foreground image from the first storage device and storing the read image data in the frame buffer.
  • Foreground image control means for reading and outputting image data from the frame buffer at a predetermined timing at writing, and second storage means for storing image data set for each pixel of the background image. Reading the image data from the second storage unit based on a command issued from the CPU, and outputting the foreground image data output from the foreground image control unit.
  • Background image control means for generating display display data obtained by synthesizing the foreground image and the background image based on the priority order, wherein the foreground image control means is developed in the frame buffer. Any of the image data set in the command is read out of the read image data, the value of the predetermined bit is changed, and then the data is written again to the same position on the frame buffer.
  • the foreground image data output from the foreground image control means is image data in which the value of the predetermined bit has been changed by the foreground image control means, the image data constitutes the inner side of the window. It is characterized in that image processing is performed on either the inside or outside of this window as image data.
  • the foreground image control means reads out the image data constituting the inside of the window from the image data expanded in the frame buffer, changes the value of a predetermined bit of the image data, and again reads the same data on the frame buffer. Hurt in place.
  • This image data is used as the image data constituting the inside of the window in the background image control means.
  • image processing is performed by the background image control means on either one of the inside and outside of the window.
  • An image processing apparatus stores a CPU for issuing a command, the command for displaying a foreground image on a display, and image data set for each pixel of the foreground image.
  • a first storage unit a frame buffer for storing image data corresponding to the foreground image to be displayed on a display, and a frame buffer for reading out the image data of the foreground image from the first storage unit.
  • Foreground image control means for reading out and outputting image data from the frame buffer at a predetermined timing; and a second storage storing image data set for each pixel of the background image. Means for reading the image data from the second storage means based on a command issued by the CPU, and foreground image output from the foreground image control means.
  • Background image control for determining display priority of data and the image data of the background image, and generating display display data obtained by combining the foreground image and the background image based on the priority order Means, the CPU comprising: a coordinate of a starting point and an ending point in a vertical direction and a horizontal direction of a first window whose shape is set in advance with respect to at least one of the foreground image and the background image; Are respectively designated for the background image control means, and the foreground image control means develops the image data in the frame buffer.
  • the arbitrary image data set in the command is read out of the obtained image data, the value of the predetermined bit is changed, and then the image data is written again in the same position on the frame buffer.
  • the foreground image data output from the foreground image control means is image data in which the value of the predetermined bit has been changed by the foreground image control means
  • the image data is displayed in a second window.
  • the image data constituting the inside of the first window is subjected to image processing on either the inside or the outside of the second window and the first window.
  • the CPU specifies the coordinates of the starting point and the ending point in the vertical and horizontal directions of the window whose shape has been set in advance for at least one of the foreground image and the background image.
  • the above window can be used together with a window having a complicated shape set for each pixel.
  • the image processing apparatus is the image processing apparatus according to claim 12 or 13, wherein the foreground image control means specifies an address on the frame buffer corresponding to an image having an arbitrary shape.
  • Address specifying means for accessing the frame buffer and reading image data already written in the address specified by the address specifying means, and image read by the frame buffer reading means
  • Bit changing means for changing the value of a predetermined bit of data
  • frame buffer writing means for accessing the frame buffer and writing the image data having the predetermined bit value changed. It is characterized by Therefore, the already written image data is read from the address on the frame buffer corresponding to the image of an arbitrary shape by the frame buffer reading means.
  • An image processing apparatus is the image processing apparatus according to the fifteenth aspect, wherein the address designating means designates an address corresponding to an image read from the image data storage means. . For this reason, by designating the address corresponding to the shape of the image stored in the image data storage means by the address designating means, the window corresponding to the shape of the image stored in the image data storage means is specified. Window can be set.
  • An image processing apparatus is the image processing apparatus according to the fourteenth aspect, wherein the bit changing means changes a value of a most significant bit of the image data. For this reason, the bit changing means uses the most significant bit having no role in other processing as the predetermined bit, so that it is efficient without setting a new area.
  • the image processing apparatus is the image processing apparatus according to claim 12 or 13, wherein the background image control unit is configured to set the value of the predetermined bit of the foreground image image data to Detecting whether or not the value is changed by the foreground image control means; and detecting that the value of a predetermined bit of the image data is changed by the window detecting unit and the window detecting unit.
  • the background image control unit is configured to set the value of the predetermined bit of the foreground image image data to Detecting whether or not the value is changed by the foreground image control means; and detecting that the value of a predetermined bit of the image data is changed by the window detecting unit and the window detecting unit.
  • a window control unit that determines image processing on either the inside or the outside of the window configured by the image data, and the second storage unit.
  • a background image generation unit that accesses and reads the image data of the background image, and combines and outputs the image data of the foreground image and the image data of the background image under the control of the window control unit. And a display control unit for inputting the information.
  • the window detection unit can detect the value of a predetermined bit of the image data of the foreground image, and can determine whether or not each image is an image in the window.
  • the image processing device is the image processing device according to claim 17, wherein the window control unit is configured to execute the processing of the window based on a command from the CPU and a detection result of the window detection unit.
  • Color calculation control that outputs a power calculation signal that instructs one of the inside and outside to perform a power calculation process including an addition operation on image data of a scene other than transparent pixels.
  • a window on the foreground image based on a command from the CPU and a detection result of the window detection unit, and forcibly assigns a pixel to either the inside or outside of the window.
  • a foreground image transparency processing control unit that outputs a symbol for foreground image transparency processing that instructs to perform transparency processing to make transparent pixels, and a command from the CPU corresponding to the background image, respectively Based on the detection result of the window detection unit, a window ⁇ is set in the background image, and the transparent processing is performed on one of the inside and outside of the window.
  • At least one background image transparency processing control unit that outputs a background image transparency processing signal that instructs the foreground image transparency processing signal to be output when the foreground image transparency processing signal is supplied.
  • First switch means for forcibly converting the image data into image data representing transparent pixels, and respectively corresponding to the background image transparency processing control unit, and when the background image transparency processing signal is supplied.
  • At least one second switch for forcibly converting the image data of the background image into image data representing transparent pixels; and when the signal for color operation processing is supplied, the foreground image and the background are provided.
  • a color operation circuit for performing the color operation on image data having the same coordinates of the image. For this reason, the instruction of the color calculation processing and the instruction of the transparent processing are separately performed, and the instruction of the transparent processing is performed for each screen. Therefore, a window is set for each screen unit of the foreground image and the background image. Each of them can be subjected to color calculation and transparency processing.
  • a CPU for issuing a command, the command for displaying a foreground image on a display, and image data set for each pixel of the foreground image are stored.
  • a first storage unit a frame buffer for storing image data corresponding to the foreground image to be displayed on a display, and reading the image data of the foreground image from the first storage unit and writing the image data to the frame buffer;
  • Foreground image control means for reading and outputting image data from the frame buffer at a predetermined timing, second storage means for storing image data set for each pixel of the background image, and the CPU The image data is read from the second storage unit based on the issued command, and the image data of the foreground image output from the foreground image control unit is read.
  • Background image control means for determining display priorities of the image data of the background image and the background image, and generating display data obtained by combining the foreground image and the background image based on the priority order.
  • the foreground image control means reads out arbitrary image data set in the command among the image data expanded in the frame buffer, and changes the value of a predetermined bit of the read image data.
  • the background image control means writes the image data of the foreground image output from the foreground image control means with the image data in which the value of the predetermined bit is changed by the foreground image control means.
  • the image data is used as image data constituting the inside of the window, and the image data is written to either the inside or outside of the window. It is characterized by performing image processing.
  • the foreground image control means reads out the image data that composes the inside of the window from the image data expanded in the frame buffer, changes the value of a predetermined bit of the image data, and again returns to the same location on the frame buffer. Write to.
  • This image data is the image data that forms the inside of the window in the background image control means. Then, the image processing is performed on one of the inside and the outside of the window by the background image control means.
  • a game machine wherein the CPU for issuing the command, the first command for displaying the foreground image on the display, and the first image storing the image data set for each pixel of the foreground image are stored.
  • a frame buffer for storing image data corresponding to the foreground image to be displayed on a display, and reading out the image data of the foreground image from the first storage unit and developing the image data in the frame buffer ′.
  • Foreground image control means for reading and outputting image data from the frame buffer at a predetermined timing, second storage means for storing image data set for each of the background images, and the CPU The image data is read out from the second storage means based on a command issued by the Data and the background image data are determined, and the priority (the background image control means for generating display data obtained by synthesizing the foreground image and the background image based on the priority).
  • the CPU comprises: a coordinate system for a starting point and an ending point in a vertical direction and a horizontal direction of a first window ⁇ having a predetermined shape, for at least one of the foreground image and the background image;
  • the foreground image control unit reads out any image data set in the command among the image data expanded in the frame buffer, and changes the value of a predetermined bit of the image data. Then, the image data of the foreground image output from the foreground image control unit is written to the same position on the frame buffer again.
  • the image data is used as image data forming the inside of a second window, and the second window and the first window are The image processing is performed on either the inner side or the outer side.
  • the CPU has at least one of the foreground image and the background image whose shape is set in advance by the CPU.
  • the window can be used together with a window having a complicated shape set for each view by the foreground image control means.
  • the address designating means for designating an address on the frame buffer corresponding to an image having an arbitrary shape;
  • a frame buffer reading unit that accesses a buffer and reads image data already written to an address specified by the address specifying unit; and a value of a predetermined bit of the image data read by the frame buffer reading unit.
  • a frame buffer damaging unit that accesses the frame buffer and damages the image data whose value of the predetermined bit has been changed. Therefore, the already written image data is read from the address on the frame buffer corresponding to the image of an arbitrary shape by the frame buffer reading means. Then, a predetermined bit of the image data read from the frame buffer is changed, and is damaged again by the address of the frame buffer.
  • a game machine is the game machine according to claim 21, wherein the address designation means designates an address corresponding to an image read from the image data storage means. . For this reason, by specifying the address corresponding to the shape of the image stored in the image data storage means by the address specifying means, the window corresponding to the shape of the image stored in the image data storage means is specified. Can be set.
  • a game machine is the game machine according to the twenty-first aspect, wherein the bit changing means changes a value of a most significant bit of the image data. For this reason, the bit changing means uses the most significant bit that does not hinder other processing as the predetermined bit, so that there is no need to newly set an area, and it is efficient.
  • the background image control means is configured so that the value of the predetermined bit of the foreground image data is A window for detecting whether or not the value is changed by the foreground image control means
  • the window detection unit detects that the value of a predetermined bit of the image data has been changed by the window detection unit
  • the window detection unit is configured by the image data based on a command from the CPU.
  • a window control unit that determines image processing for either the inside or outside of the window to be accessed, a background image generation unit that accesses the second storage unit, and reads out image data of the background image, and the window control unit.
  • a display control unit that combines the image data of the foreground image and the image data of the background image and outputs the combined image data. For this reason, the value of a predetermined bit of the image data of the foreground image is detected by the window detection unit, and it is possible to determine whether each pixel is a pixel in the window or not for each image.
  • the window control unit is configured to control the window based on a command from the CPU and a detection result of the window detection unit.
  • a force signal that outputs a force signal processing signal instructing one of the inside and outside to perform a force operation process including an addition operation on image data of a pixel other than a transparent pixel.
  • a window is set in the foreground image based on an arithmetic control unit and a command from the CPU and a detection result of the window detection unit, and a search is forced on either the inside or outside of the window.
  • a foreground image transparency processing control unit that outputs a signal for foreground image transparency processing that instructs to perform transparency processing to make transparent pixels, and a command from the CPU and the window corresponding to the background image, respectively. Based on the detection result of the detection unit, a window is set in the background image, and at least one signal for outputting a background image transparent processing signal instructing one of the inside and outside of the window to perform the transparent processing is output.
  • the display control unit forcibly converts the image data of the foreground image into image data representing transparent pixels.
  • the first switch means and the background image transparency processing control unit respectively, and when the background image transparency processing signal is supplied, the background image data is forcibly represented as transparent pixels.
  • the color calculation is performed on the image data of the same coordinates of the foreground picture and the background picture.
  • Mosquito is characterized by having a chromatography operation circuit. For this reason, the instruction of the color operation processing and the instruction of the transparent processing are separately performed, and the transparent processing instruction is performed. Since the processing instruction is performed for each screen, a window can be set for each screen unit of the foreground image and the background image, and color calculation and transparency processing can be performed on each of them.
  • FIG. 1 is a block diagram showing an overall configuration of an image processing apparatus according to one embodiment of the present invention
  • FIG. 2 is a block diagram showing a configuration of a scroll engine 21 of the image processing apparatus according to one embodiment of the present invention
  • FIG. FIG. 4 is a diagram showing image data FGDT of a foreground image in the embodiment
  • FIG. 4 is a block diagram showing a configuration of a split engine 20 in the embodiment
  • FIG. 5 is (a) a foreground image developed in a frame buffer in the embodiment.
  • An example of FG (b) a diagram illustrating a case where a character Wl is used as a split window, and (c) a diagram illustrating a case where a character W2 is used as a split window.
  • FIG. 1 is a block diagram showing an overall configuration of an image processing apparatus according to one embodiment of the present invention
  • FIG. 2 is a block diagram showing a configuration of a scroll engine 21 of the image processing apparatus according to one embodiment of the present invention
  • FIG. 6 shows a window control unit 44 in the embodiment.
  • Figure 7 shows a rectangular window WR
  • Figure 8 shows a line window WL
  • Figure 9 shows a split window WS
  • Figure 10 shows a rectangular window WR
  • Fig. 11 illustrates the case where the rectangular window WR and the split window WS are used simultaneously.
  • Fig. 12 illustrates the case where the rectangular window WR and the split window WS are used simultaneously.
  • Fig. 12 illustrates the case where the rectangular window and the split window WS are used simultaneously.
  • Fig. 13 shows the superimposition of (a) background image BGO, (b) background image BG1, (c) foreground image FG, and (d) background image BG0, BG1 and foreground image FG.
  • FIG. 14 illustrates the color operation processing
  • Fig. 15 illustrates the case where the transparent processing is performed inside the window
  • Fig. 16 illustrates the case where the transparent processing is performed outside the window.
  • FIG. 17 is a diagram for explaining (a) the line window WL, and (b) a diagram for explaining the problems of the conventional image processing apparatus.
  • the background image is assumed to have two sides (BGO, BG1).
  • FIG. 1 is a block diagram showing an embodiment of the image processing apparatus according to the present invention.
  • reference numeral 10 denotes a game machine main body.
  • An input device such as a control pad 34 for a user to operate a game is provided with a game machine main body 10 by SMPC (Systera Manager & Peripheral Control, system manager). Connected via 33.
  • SMPC Synstera Manager & Peripheral Control, system manager
  • a cartridge 35 in which a game program is stored is detachably attached to the game machine body 10.
  • This game program is usually harmed by a semiconductor memory (mask ROM), and the semiconductor memory is incorporated in the cartridge 35.
  • the game machine body 10 is provided with a CD-ROM drive (not shown), the game program can be supplied from a CD-ROM.
  • the bus 14 is connected to the CPU 15, the RAM 16 for work of the CPU 15, the ROM 17 for storing programs, and the SMP C 33.
  • the CPU 15 controls the entire system, and is composed of, for example, a 32-bit RISC type high-speed CPU (two CPU chips called SH-2). SM
  • the PC 33 is an I / 0 controller, which controls reset of the entire system and controls an interface with an external device such as the control pad 34.
  • the bus 14 is connected to a split engine 20 for performing image processing of a foreground image and a scroll engine 21 for performing image processing of a background image.
  • the split engine 20 is connected to a command RAM 22 for storing command data from the CPU and image data as the original picture of the foreground picture, and a frame buffer 23 for developing the foreground picture image data.
  • the scroll engine 21 is connected to a video RAM (VRAM) 24 that stores image data for each pixel of the background image, and a color RAM 25.
  • a bus controller 18 connected to the bus 14 includes a DMA controller, an interrupt controller, and the like, and controls an interface between the CPU 15, the split engine 20, and the scroll engine 21.
  • the split engine 20 selects and reads both foreground image data such as characters from the command RAM 22 and performs processing such as rotation, enlargement, reduction, and color calculation. After that, the data is written to a predetermined address of the frame buffer 23.
  • the split engine 20 sequentially reads out one frame of image data written in the frame buffer 23 and supplies the image data directly to the scroll engine 21 without passing through the bus 14.
  • the CPU 15 supplies command data to the splic engine 20 by executing a program in the ROM 17.
  • This command data is data (drawing command) indicating a drawing command of the foreground image, and is written into the command RAM 22 by the split engine 20 as a command table. Then, the command data is read out by the split engine 20, and is executed by being set in an internal system register.
  • the VRAM 24 stores pattern data including image data of cells of 8 ⁇ 8 pixels in length and width. Further, when the above cells are laid out vertically and horizontally by 28 ⁇ 40 cells to constitute one frame of the background images BG 0 and BG 1, pattern name data is stored corresponding to the arrangement.
  • the pattern name data specifies control information such as the head address of the pattern data stored in the VRAM 24 and the priority of the pattern data for each pattern data, and is stored for two frames.
  • the color RAM 25 stores RGB data as color data.
  • one pixel of RGB data is output from the terminal 56 of the scroll engine 21 in synchronization with the horizontal synchronization signal, and supplied to the DA converter 31.
  • the D / A converter converts the RGB data into an analog signal and outputs it from terminal 32 as a video signal. This video symbol is supplied to a monitor (not shown) and displayed on a TV screen.
  • FIG. 3 shows image data FGDT for one pixel of the foreground image processed by the split engine 20.
  • one pixel is represented by 16 bits.
  • the lower 11 bits D0 to D10 are bits for a color code CLC for specifying a color, and these 11 bits are used as an address of the color RAM 25.
  • Foreground characters can be commanded at 4 or 8 bits per dot.
  • the color RAM address offset value specified for each character is added to the upper side of the character buffer.
  • the next four bits Dl1 to D14 are priority codes PRC, and are used to control the priority of each overlapping pixel when displaying multiple images in an overlapping manner. In this case, a pixel with a higher priority is displayed in preference to a pixel with a lower priority.
  • the most significant bit D15 is the window flag FLG. If the value is ⁇ 1 J, it indicates that the pixel is within the window.If the value is “0”, it is not a pixel within the window. ing. The setting of the window flag FLG will be described later.
  • the split engine 20 has an MSB on function.
  • MSB on function In this embodiment,
  • the MSB on function is to read the target data in the frame buffer and write the data, instead of simply overwriting when writing a character to the specified location in the frame buffer 23.
  • This function changes MSB (Most Significant Bit) from rcu to “1” and writes the data to the same address again.
  • This MSB on function is used for setting the window flag FLG of the image data FGDT of the foreground image FG described above.
  • the frame buffer 23 in the present embodiment is divided into two frame buffers 23a and 23b, and can be switched between drawing and display as appropriate.
  • the frame buffer 23a is used for drawing and the frame buffer 23b is used for display.
  • the frame buffers 23a and 23b are switched from drawing to display, all written data is erased.
  • reference numeral 101 denotes an arbitration circuit which controls an interface between the CPU 15, the split engine 20, and the command RAM 22, and transfers command data from the CPU 15 to the command RAM 22; And command RAM 22 Arbitration between the reading of command data and image data from.
  • Reference numeral 102 denotes a command read control circuit, which reads command data from the command RAM 22.
  • Reference numeral 103 denotes an image data readout circuit which reads out image data of a character designated to be drawn in the command data from the command RAM 22, and outputs one dot of image data.
  • a command register 104 stores command data for one foreground picture character read by the command read control circuit 102.
  • Reference numeral 105 denotes an MSB ON instruction register, which is a 1-bit register in the command register and stores an ON / OFF designation bit for specifying whether the MSB ON function is to be turned ON or OFF. . This bit is set to “1” when the use of the MSB on function is set, and becomes “OJ” when it is not set. This MSB on function is specified for each character.
  • Reference numeral 106 denotes a transparent / non-transparent determining circuit which determines whether or not the image data output from the image data reading circuit 103 is transparent and outputs it as transparent Z non-transparent information. In this case, if the color code CLC force of the image data is “0000HJ”, it is considered to be transparent;
  • Reference numeral 107 denotes a frame buffer write read control circuit, which controls the timing of reading and rewriting of the frame buffer 23a when the MSB ON function is set.
  • Reference numeral 108 denotes a read word signal generator, which generates a read signal for designating reading from the drawing frame buffer 23a.
  • Reference numeral 109 denotes a write signal generator which generates a write signal for designating writing to the frame buffer 23a. The light signal generator 109 prevents the generation of the light signal when the data indicating that the dot is transparent is supplied as the transparent / non-transparent information from the transparent / non-transparent determining circuit 106. Has become.
  • 1 10 is a data selector, which outputs image data from the image data reading circuit 103 when the MSB on function is not set, and outputs the frame buffer 23a when the MSB on function is set. It outputs the image data read from. 1 1 is an OR circuit, which is the MSB of the image data output from the data selector 110 and the ON / OFF designation bit set in the MSB ON instruction register 105 Perform an OR operation with
  • Reference numeral 12 denotes a frame buffer address generator, which outputs an address signal designating an address on the frame buffer 23a accessed by the split engine 20.
  • Reference numeral 13 denotes a frame buffer switching circuit, which switches between the drawing and display frame buffers 23a and 23b every 60 seconds.
  • Reference numeral 114 denotes a data output buffer which temporarily holds the image data output from the data selector 110 and outputs the image data at the timing of the light signal generated by the light signal generator 109.
  • this data output buffer 114 does not output anything.
  • Reference numeral 15 denotes a frame buffer readout circuit which reads out image data from the display frame buffer 23 b and outputs it to the scroll engine 21.
  • FIG. 5 (a) it is assumed that the characters C1.C2.W1 are developed in the foreground image FG, and that the characters C1 ⁇ C2—W1 are written in this order. I do.
  • the data values for each dot are assumed to be ⁇ 0001 HJ, ⁇ 0002HJ, and 00030003HJ, respectively.
  • the read image data of the character W1 is represented by a drawing dot WDT as shown in FIG. 5 (b). It is assumed that a window having the shape of the character W1 is formed on a TV screen, for example, on the TV screen.
  • the split engine 20 harms the shape of the character C1 with “0001 H” at the designated position of the frame buffer 23.
  • the image data of the character C1 is read by the image data reading circuit 103 based on the command data read by the command reading control circuit 102
  • one dot of the image data is read from the data selector 110. Is output to
  • MS B on function since the MS B on function is not set, MS B image data data selector 1 10 that is output from the c data selector 1 10 for outputting the image data, Kyo ⁇ the OR circuit 1 1 1 Is done.
  • the MSB of the above image data is “0”
  • the value set in the MSB instruction register 105 at this time is also “0”, so the output of the OR circuit 1 1 1 1 Also, the power becomes “0J.”
  • the MSB and the bits other than the MSB are supplied to the frame buffer switching circuit 113 and output to the data output buffer 114. Then, the light signal generator 109 It is written to the frame buffer 23a at the timing of the generated write signal.
  • the split engine 20 writes “0002HJ” in the shape of the character C2 and writes “ ⁇ 0003 ⁇ ” in the shape of the character W1 at the designated position of the frame buffer 23a.
  • the command read from the command RAM 22 specifies the use of the MSB on function. Therefore, “1” is set in the MSB ON instruction register 105 of the command register 104. Then, the image data of the character W1 is supplied from the image data reading circuit 103 to the data selector 110 and the transparent / non-transparent determining circuit 106.
  • the image data of the character W1 is read from the frame buffer 23a and supplied to the data selector 110.
  • the data selector 110 outputs the image data read from the frame buffer 23a.
  • the MSB of this image data is supplied to the OR circuit 111, and since the set value of the MSB ON instruction register 105 is “1”, the output of the OR circuit 111 becomes “1”.
  • the output of the OR circuit 111 and the bits other than the MSB output from the data selector 110 that is, the image data ( ⁇ 8003 ⁇ ) in which the MSB of the image data of the character W1 is converted to "1"
  • the data is supplied to the data output buffer 114 via the buffer switching circuit 113, and is written to the frame buffer 23a at the timing of the write signal generated from the write signal generator 109.
  • this image data is written again to the address on the frame buffer 23a where the image data of the character W1 was originally written.
  • the platform is determined to be transparent, and the transparent / non-transparent information is Output to light signal generator 109. Therefore, no write signal is generated from the write signal generator 109. Therefore, the image data from the data selector 110 is not input to the frame buffer 23a.
  • the image data converted to the MSB force, “1” is handled as image data of pixels in the window by the scroll engine 21.
  • a window in which a window is specified on the frame buffer is called a "split window”.
  • FIG. 2 shows the configuration of the scroll engine 21.
  • a background image generation unit 41 reads pattern name data for two frames from the VRAM 24 and reads pattern data corresponding to the pattern name data. Then, the background image generation section 41 outputs image data BGODT, BG1DT for one pixel of the pattern data in synchronization with the horizontal synchronization signal.
  • the image data BG 0 DT and BG 1 DT are 15-bit data consisting of the priority code PRC and the color code CLC excluding the window flag FLG of the image data F GDT of the foreground image FG shown in FIG. It has a configuration.
  • terminal 40 receives image data FGDT of the foreground image FG from the split engine 20.
  • the window flag FLG of the most significant bit D15 of the image data FGDT is supplied to the split window detecting unit 42,
  • the remaining lower 15 bits D0 to D14 of the color code CLC and the priority code PRC are supplied to the display controller 43.
  • the split window detection unit turns on the split window signal SPR output to the window control unit.
  • FIG. 6 shows the configuration of the window control unit 44. In this figure, the following registers are set in the control register 60.
  • Window position R P 0 S Coordinates of the horizontal and vertical start and end points of a normal rectangular window.
  • Line window table address TB L Line window in VRAM24 ⁇ Start address of table (table of horizontal start and end point coordinates for each line) 0
  • Window Position L P 0 S The coordinates of the vertical start and end points of the normal line window.
  • Reference numeral 61 denotes a normal window control unit 1, which determines whether the normal window is a rectangular window or a line window according to the contents of the control register 60, and determines whether the normal window is a normal line window.
  • the line window table of VRAM 24 is searched according to the line window table address TBL. When the pixel is inside the normal rectangular window or inside the normal line window, the rectangular window signal REC or the line window signal LIN is turned on, respectively.
  • 62 is a control unit for color calculation processing
  • 63 is a control unit for foreground image transparency processing
  • Reference numeral 5 denotes a control unit for background image transparent processing. These are composed of control registers 66a to 66d, enable circuits 67a to 67d, internal / external control circuits 68a to 68d, and sum-of-products control circuits 69a to 69d, each having the same configuration. I have.
  • the background image transparency processing control units 64 and 65 correspond to the number of background images. Ie tree implementation In the example, two background images B GO. BG 1 are provided, but if there are five background images, for example, five background image transparent processing control units are provided.
  • the following registers are set in the control registers 66a to 66d.
  • Window logic LOG How to overlap multiple windows, ie, ANDZOR logic setting.
  • Normal window enable NWEN 1 Whether to use a rectangular window for each screen.
  • Normal window enable NWEN2 Whether to use the line window for each screen.
  • the enable circuits 67a to 67d are supplied with a split window signal SPR together with the rectangular window signal REC and the line window signal LIN. Then, the enable circuits 67 a to 67 d provide the rectangular window signal REC, the line window signal LIN, or The valid one of the sprite window signals SPR is turned on.
  • the color operation enable CLENB of the control registers 66 a to 66 d is set to perform the color operation, only the output of the enable circuit 67 a is turned on, and the enable circuit 67 b to All signals output from 67d are turned off.
  • the internal / external control circuits 68 a to 68 d use the rectangular window signal RE C when displaying the effective area of the window according to the window areas NWAR 1 and NWAR 2 and SWAR set in the control registers 66 a to 66 d. Turn on either the line window signal IN or the split window signal SPR.
  • the sum-of-products control circuits 69a to 69d perform color calculation processing or transparent processing based on the window logic L0G set in the control registers 66a to 66d when using multiple windows. Set the effective area.
  • the switching signal BGO SW for background image transparency processing or the switching signal BG1 SW for background image transparency processing is turned on.
  • the switching signal CLSW for color operation processing is turned on.
  • the switch 50 To the switch 50, a portion of the foreground image FG except for the window flag FLG of the image data FGDT, that is, the priority code PRC and the color code CLC are input.
  • the switch 50 outputs the input signal as it is when the foreground picture transparent processing switching signal FGSW from the window control unit 44 is off, and forcibly changes the color code CLC of the input signal to “00 HJ” when it is on. And output.
  • the switch 51 receives the image data BGODT of the background image BG0 from the background image generation unit 41, and the switch 52 receives the image data BG1DT of the background image BG1. ing. And switch 51 and switch 52 are respectively
  • 54 is a control register, and the following registers are set.
  • Special priority mode MOD E Sets the function to change the priority for each character or dot on each background image. When this mode is set, the character or dot's priority code is also set.
  • Color calculation ratio RAT I 0 Addition ratio when performing color calculation.
  • Reference numeral 55 denotes a priority circuit, to which image data FGDT, BGODT.BG1DT which is an output signal of the switches 50 and 51.52 are supplied.
  • the priority circuit 55 determines whether or not the color code CLC of the image data FGDT, BGODT, BG1DT is “ ⁇ 0HJ”. And, color code CLC power ⁇
  • Reference numeral 56 denotes a color RAM control circuit.
  • the color RAM 25 is accessed based on the color code CLC output from the brightness circuit 55, and the RGB is controlled. Get data. If the image data FGDT, BG ODT, and BG1DT are in RGB format, the color code CLC is used as RGB data.
  • Reference numeral 57 denotes a color operation circuit which performs a color operation on the image data supplied from the color RAM control circuit 56.
  • the color from the window control unit 44 When the arithmetic processing switching signal CLSW is turned on, a color operation is performed based on the color operation ratio RAT I0 set in the control register 54 and the priority determined by the priority circuit 55.
  • the color operation switching signal CL SW When the color operation switching signal CL SW is off, the RGB data of the image data having the highest priority among the image data supplied from the color RAM control circuit 56 is output from the terminal 58.
  • the CPU 15 sets the following in each control register.
  • the image data F GDT, BG ODT and BG 1 DT input to the switches 50. 51. 52 are all supplied to the priority circuit 55 as they are,
  • a color operation circuit 57 It is supplied to a color operation circuit 57 via a RAM control circuit 56. At this time, since the switching signal CLSW for the color calculation processing is ON, the color calculation circuit 57 performs the color calculation based on the color calculation ratio RATI0 set in the control register 54.
  • the color arithmetic circuit 57 outputs the RGB data of the image data having the highest priority among the image data FGDT and BGODT.BG 1 DT, and supplies it to a monitor (not shown).
  • the switching signal CLSW for color calculation processing is turned on, so that color calculation is performed, and when the outer area AR2 is displayed, the color is switched.
  • the switching signal CL SW for operation processing is turned off, and no color operation is performed.
  • the image is displayed only in the area AR1 inside the line window WL, and both the foreground image FG and the background images BGO and BG1 are displayed in the outer area AR2.
  • the back screen is displayed without performing the operation.
  • the CPU 15 sets a register as shown below.
  • the line window signal LIN from the inner control circuits 68b to 68d is turned on. Therefore, the foreground picture transparent processing switching signal FGSW and the background picture transparent processing switch BG 0 SW, BG 1 SW are turned off, and the image data F GDT, BGODT, BG 1 DT are supplied to the priority circuit 55 as they are. . Then, the color code is supplied to the color arithmetic circuit 57 via the color RAM control circuit 56, and the color arithmetic circuit 57 outputs the color code CLC of the image data having the highest priority among the image data FGDT. BGODT. BG 1 DT. .
  • the line window signal LIN output from the normal window control unit 61 is turned off, and the line window signals LIN from the enable circuits 67b to 67d are turned off. Since the normal window enable NWEN2 is set for the foreground image FG and the background images BGO and BG1 and the outside of the line window WL is valid, the internal / external control circuit 68b ⁇ The line window signal LIN from 68d turns on. As a result, the switching signal FGSW for foreground image transparency processing, the switching signal B G0 SW for background image transparency processing, and the switching signal BG 1 SW for background image transparency processing are all turned on.
  • the color codes C LC of the image data FGDT, BG ODT, and BG 1 DT that are manually input to the switches 50, 51, and 52 are all converted to “O OH” and output from the terminal 58 as they are.
  • the area AR2 becomes a single-color back screen because the transparent processing is applied to all of the foreground image FG and the background image BG0.BG1.
  • the line window signals from the enable circuits 67b to 67d are turned on, but since the outside of the line window WL is valid, the line window signals LIN from the internal / external control circuits 68b to 68d are turned off. .
  • the switching signal FG SW for the foreground image transparency processing and the switching signal BG 0 SW, BG 1 SW for the background image transparency processing are all turned on.
  • the color data CLC force ⁇ ”(transparency) for each gamut is obtained.
  • the above signals are all off, so no transparency processing is performed.
  • transparent processing can be performed in the same manner as in the above-described line window WL.
  • color arithmetic processing can be performed in the same manner as in the rectangular window WR described above.
  • the split engine 20 converts the MSB of the image data at the position where the split window is set to “1” by the MSB on function. Also, at this time, the CPU 15 sets the registration time as described below.
  • the window flag FLG of this image data is "0", so that the split window signal SPR is turned off. It becomes.
  • the split window signals SPR of the enable circuits 67b to 67d are respectively turned off, but since the outside of the split window WS is valid, the split window output from the internal / external control circuits 68b to 68d is provided.
  • Signal SP 11 ⁇ turns on. Therefore, the foreground picture transparent processing switching signal FG SW and the background picture transparent processing switching signals BGO SW and BG 1 SW are all turned on.
  • the area AR2 becomes a single-color back screen because the transparent processing is applied to all of the foreground image FG and the background images BGO and BG1.
  • the window flag FLG of this image data is "1", so that the split window signal SPR is turned on.
  • the split window signal output from the internal / external control circuits 68b to 68d is not effective because the split window signal SPR of the enable circuits 67b to 67d is turned on and the inside of the split window WS is not effective. SPR is turned off. Therefore, the switching signal FGSW for foreground image transparency processing and the switching signals BGOSW, BG1SW for background image transparency processing are all turned off.
  • the image data FGDT, BGODT, and BG1DT are supplied as they are to the priority circuit 55 and supplied to the color arithmetic circuit 57 via the color RAM control circuit 56. Then, the color operation circuit 57 outputs the color data of the image data having the highest priority among the image data F GDT. BGODT and BG 1 DT. Since LG is ⁇ 1 ”, the split window signal SPR is turned on. Here, since the color calculation enable CLENB of the control registers 66a to 66d is set, the split window signal SPR output from the enable circuit 67a is turned on. Then, the switching signal CLSW for color calculation processing is turned on, and the switching signal FG SW for foreground picture transparency processing and the switching signals B GO SW, BG 1 SW for background picture transparency processing are all turned off.
  • the image data FGD T, BG ODT, and BG 1 DT input to the switches 50, 51, and 52 are directly supplied to the priority circuit 55, and are sent to the color arithmetic circuit 57 through the color RAM control circuit 56. Supplied. At this time, the switching signal CL SW for color operation processing is supplied to the color operation circuit 57, so that the color operation based on the color operation ratio RAT I0 set in the control register 54 is performed in the color operation circuit 57. Will be
  • the window flag FLG of these image data is "0", so that the split window signal SPR is turned off. Therefore, the color arithmetic processing switching signal C L SW is turned off, and the color arithmetic circuit 57 outputs the RGB code of the image data having the highest priority among the image data FG.BG0 and BG1.
  • the split engine 20 uses the MSB on function to set the MSB of the image data at the position corresponding to the inside of the split window WS shown in FIG.
  • the CPU 15 also sets the register as shown below. Mode C LC is output.
  • the MSB of the image data at the corresponding position on the frame buffer may be set to “1”.
  • the rectangular window signal REC is turned on, but in the sum-of-products control circuits 69a to 69d, the area outside the effective area of the window (area AR3). It is determined that there is. Therefore, the switching signal CL SW for color operation processing (for color operation processing) or the switching signal FG SW for foreground image transparency processing and the switching signal BGO SW, BG 1 SW for background image transparency processing (for transparent processing) ) Is turned off.
  • the force at which the sprite window signal SPR is turned on, and similarly, the product sum control circuits 69a to 69d are turned off.
  • the product-sum control circuits 69a to 69d determine that the area is an effective area of the window, and the switching signal CL SW for color operation processing (for color operation processing) or the foreground image transparent processing. At least one of the switching signal FG SW and the switching signal BG 0 SW and BG 1 SW for background image transparent processing (in the case of transparent processing) is turned on.
  • the splicing is performed by the product-sum control circuits 69a to 69d. Only the area AR5 excluding the area AR3 of the window WS is judged to be the effective area of the window. Further, as shown in FIG. 12, when the inside of the rectangular window WR and the inside of the split window ⁇ WS are valid, and the overlapping method is OR processing, the sum-of-products control circuits 69a to 69d determine the area AR3. , AR4, AR5 are all judged to be valid areas.
  • the color calculation enable C LE NB is set for the rectangular window
  • the split window enable SWEN is set for the target screen.
  • a window is set for each pixel using the MSB of the image data expanded in the frame buffer.
  • a window with a complicated shape can be set.
  • a window can be set for each foreground image and background image, and a plurality of windows can be used at the same time, and color calculation and transparency processing can be performed on them, a variety of windows can be obtained. Display can be performed. .
  • the present invention is not limited to the above embodiment, and can be widely used in other than video game machines, that is, in image display devices of personal computers and other computers.
  • the power using MSB to set the window flag FLG ⁇ is not limited to this, and an unused bit of the image data FGDT may be used.
  • a frame buffer access method comprising changing a value of a predetermined bit of image data read from the frame buffer, and rewriting the address in the address on the frame buffer.

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Abstract

Les données d'image déjà enregistrées dans les adresses et correspondant à une image présentant une forme arbitraire sont lues à partir d'une mémoire d'images (23), et les valeurs des bits prédéterminés des données d'images de lecture sont modifiées, puis lesdites données d'images sont à nouveau enregistrées dans les adresses. Lorsque les données d'images du premier plan sont lues à partir de ladite mémoire d'images (23) à intervalles prédéterminés, la valeur de chaque bit prédéterminé est vérifiée de manière à déterminer si elle correspond à la valeur modifiée ou non. En cas de valeur binaire modifiée, les données d'images présentant la valeur binaire modifiée est considérée comme étant les données d'images constituant la région intérieure d'une fenêtre, et le traitement des transparences ou du calcul des couleurs de l'intérieur ou l'extérieur de la fenêtre est réalisé. Ainsi, les bits prédéterminés des données d'images enregistrées dans la mémoire d'images peuvent être modifiés, et une fenêtre de toute forme complexe peut être élaborée en conséquence.
PCT/JP1994/001067 1993-06-30 1994-06-30 Procede et dispositif de traitment d'images WO1995001609A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP7501588A JP2891542B2 (ja) 1993-06-30 1994-06-30 画像処理方法及び装置
EP94919833A EP0660266A4 (fr) 1993-06-30 1994-06-30 Procede et dispositif de traitment d'images.
BR9405493-2A BR9405493A (pt) 1993-06-30 1994-06-30 Sistema e processo para processamento de imagem
KR1019950700746A KR950703183A (ko) 1993-06-30 1995-02-27 화상 처리 방법 및 장치(Image Processing Method and Device Therefor)

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JP5/162976 1993-06-30
JP16297693 1993-06-30

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WO1995001609A1 true WO1995001609A1 (fr) 1995-01-12

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KR (1) KR950703183A (fr)
CN (1) CN1111461A (fr)
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WO (1) WO1995001609A1 (fr)

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WO1999034334A1 (fr) * 1997-12-25 1999-07-08 Hudson Co., Ltd. Dispositif de sortie d'image

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BR9405493A (pt) 1999-09-08
KR950703183A (ko) 1995-08-23

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