WO1993003501A1 - Agencement compact de memoires a semi-conducteurs et son procede de fabrication - Google Patents

Agencement compact de memoires a semi-conducteurs et son procede de fabrication Download PDF

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Publication number
WO1993003501A1
WO1993003501A1 PCT/EP1992/001653 EP9201653W WO9303501A1 WO 1993003501 A1 WO1993003501 A1 WO 1993003501A1 EP 9201653 W EP9201653 W EP 9201653W WO 9303501 A1 WO9303501 A1 WO 9303501A1
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WO
WIPO (PCT)
Prior art keywords
trench
electrode
insulating layer
bit line
layer
Prior art date
Application number
PCT/EP1992/001653
Other languages
German (de)
English (en)
Inventor
Hanno Melzner
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to DE59204621T priority Critical patent/DE59204621D1/de
Priority to KR1019940700278A priority patent/KR100273779B1/ko
Priority to US08/182,187 priority patent/US5378907A/en
Priority to JP50321593A priority patent/JP3431143B2/ja
Priority to EP92916425A priority patent/EP0596975B1/fr
Publication of WO1993003501A1 publication Critical patent/WO1993003501A1/fr
Priority to HK99097A priority patent/HK99097A/xx

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Definitions

  • the invention relates to a semiconductor memory arrangement in a semiconductor substrate with memory cells, each consisting of a capacitor and a MOS selection transistor.
  • Semiconductor memories consist of a number of memory cells in a e.g. semiconductor substrate consisting of silicon, each composed of a capacitor for storing the information and a transistor for selecting the specific capacitor.
  • a semiconductor substrate consisting of silicon
  • Arrangement must be increased, ie the space requirement of a cell must be minimized.
  • a linear downsizing of all structures of the cell is not possible, however, since, for example, for reasons of electrical reliability, the capacitor must not fall below a certain capacitance and structures of any desired size cannot be produced using the techniques available. Instead, a cell that is as small as possible must be achieved with a given structural fineness, ie the goal is a cell that is as compact as possible.
  • the object of the present invention is to provide a semiconductor memory arrangement which solves the problems explained.
  • Figure 1 is a plan view of
  • FIG. 2 to 7 show a cross section through a semiconductor substrate in the area of memory cells in a schematic illustration, on which the steps of an embodiment of the method are illustrated, the section running along the line II-II in FIG. 1.
  • Figure 8 shows a top view of the memory matrix
  • FIG. 9 shows a top view of the memory arrangement with an advantageous arrangement of word lines.
  • Isolation areas 2 are produced in a semiconductor substrate 1, which run essentially in a strip shape and the lateral isolation between them Isolation areas 2 serve to produce memory cells.
  • the isolation regions 2 are preferably produced as buried oxide regions, for example according to the method described in the article by C. Zeller, F. Stelz, conference proceedings ESSDERC 89, pages 135-138, so that they are essentially at a depth of approximately 600 nm have vertical flanks and their surfaces lie in one plane with the surface of the Ralbleitersuhstrats 1.
  • FIG. 2 A gate oxide (not shown) is generated on the entire surface 3 of the semiconductor substrate 1, then a layer is deposited over the entire surface to form a gate 4 of the selection transistor and a primary word line (4 '), for example doped polysilicon of about 250 nm thickness .
  • An insulation layer 5 is deposited thereon preferably by pyrolytic decomposition of tetraethyl orthosilicate (TEOS) (hereinafter referred to as TEOS layer 5) and structured into a web with the aid of a photo technique.
  • TEOS tetraethyl orthosilicate
  • the polysilicon layer is structured with the structured TEOS layer 5 as a mask, so that a primary word line (4 ') running approximately perpendicular to the strip-shaped insulation regions 2 is produced; a part running over the semiconductor substrate 1 simultaneously represents the gate 4.
  • An etching process with a sufficiently high selectivity for the gate oxide and for the buried oxide 2 is used.
  • the primary word line and the gate 4 are laterally encapsulated for isolation with spacers 6, which are usually produced by a wide TEOS deposition of approximately 100 nm and an anisotropic etching back process; the surface of word line and gate 4 are already covered with TEOS 5.
  • conductive areas (source and drain) of the transistors are now implanted, especially the transistors in the periphery of the circuit.
  • the conductive regions of the selection transistor can also be produced in a later method step. Processes which are common in semiconductor technology can be used for the method steps described above. For example, in order to achieve a short gate length, it is known to reduce the width of the TEOS web 5 below the limit set by the photo technology by wet etching before the structuring of the polysilicon layer. An oxidation step for rounding the lower gate edges is also customary.
  • the invention now provides for a capacitor trench 7 to be self-aligned with the structures already created, i.e. to the insulation regions 2 and to the primary word lines or gates 4 encapsulated with the TEOS layer 5 and the spacers 6 (4 "denotes an adjacent gate) in the semiconductor substrate 1.
  • An anisotropic etching process is used which Material of the structures mentioned, namely silicon dioxide and TEOS, etches to a sufficient extent more slowly than the exposed semiconductor substrate 1.
  • the TEOS layer 5 and the spacers 6 must still provide sufficient insulation after the etching process
  • the capacitor has an essentially rectangular cross section.
  • FIG. 3 For isolation from the semiconductor substrate 1, a first insulating layer 8, 9 is applied to the surface of the trench 7, which consists of a bottom 7 ′ and a wall 7 ′′ that is essentially perpendicular to the semiconductor substrate surface 3.
  • the first insulating layer consists of a double layer with an approximately 20 nm thick silicon oxide layer 8 and a silicon nitride layer 9, which is deposited over the entire surface and is approximately 30 nm thick, as components.
  • a structured photoresist layer 10 exposes one side of the trench wall 7 "in the vicinity of the upper trench edge to a certain depth which can be set during the structuring via the exposure time. At least the opposite side of the trench wall 7" and the bottom are covered with lacquer 10.
  • the first insulating layer 8, 9 is removed at the exposed location, so that a first opening is formed in the first insulating layer 8, 9; the TEOS 5,6 of the gate encapsulation may only be attacked slightly.
  • the now exposed location of the semiconductor substrate 1 in the upper region of the trench wall 7 ′′ enables later contact between a capacitor electrode and a conductive region of the selection transistor and represents the so-called trench contact 11. It defines the selection transistor associated with the trench 7, which is shown in FIG on the left side of the
  • FIG. 4 The structured photoresist layer 10 is removed.
  • a first electrode layer 12 ′ is produced to form a first electrode 12 of the capacitor.
  • an approximately 30 nm thick doped polysilicon layer can be deposited, which is then removed by anisotropic etching back at least above the TEOS path 5.
  • the first electrode layer 12 ′ is produced, from which the first electrode 12 is later formed.
  • the trench 7 can be partially filled with a lacquer plug 13, which covers the step produced by the underlying first insulating layer 8, 9 in the first electrode layer 12 'at the trench contact 11.
  • the first electrode layer 12 ' is not attacked at this stage and also covers the trench bottom 7'.
  • the paint stopper 13 can, for example, be brought into the trench with a back-coating of the lacquer (ie full-area exposure and development); after the etching back, it is removed.
  • the first electrode layer 12 'thus produced is still connected to the first electrode layer in a trench adjacent in the direction of the primary word line (41), specifically via the part of the first electrode layer 12' above the substrate surface 3, laterally on the TEOS spacer 6.
  • the first electrode layer 12 ' is structured such that a first electrode 12 lies in each trench.
  • the photo technology (not shown) defines a second opening on the side of the trench wall 711 opposite the first opening (the trench contact 11) in the vicinity of the upper trench edge.
  • the first electrode layer 12 ' is selectively removed from the underlying first insulating layer 8, 9 and thus has the second opening.
  • the side of the trench wall 7 ′′ on which the first opening is arranged is covered with photoresist during this process step.
  • the second opening in the word line direction must have at least the dimensions (32) shown in FIG.
  • a second insulating layer 14 is produced as a capacitor dielectric, at least on the first electrode 12, for example a so-called DNG layer.
  • the TEOS layer 18 is structured in such a way that it is suitable as a mask for the production of a bit line contact:
  • the trench wall with the trench contact 11 is covered by the TEOS layer 18, selecting on the side of the trench which the second opening in of the most electrode layer 12 ', the second electrode layer 16' is at least partially exposed.
  • a second electrode 16 is now produced from the second electrode layer 16 ′ by anisotropically etching a bit line contact hole 19 to a depth that is below the substrate surface 3 and preferably above the. Top edge of the first electrode 12 on this
  • the second electrode layer 16 'thus has, like the first electrode layer, a second opening which lies essentially at the same location on the trench wall 7' 'and extends to a shallower depth in the trench. At this point in the trench wall 7 ′′, silicon nitride 9 is now exposed.
  • a third insulating layer 17 is produced on the exposed surface of the second electrode 16, preferably by an oxidation process.
  • the thickness of the silicon oxide layer 17 formed in this way is approximately 80 nm.
  • the exposed nitride 9 protects this point on the trench wall, the later bit line contact, from oxidation.
  • FIG. 7 In addition to the memory cell 24 in question, the figure also shows the selection transistor 25 of the memory cell adjacent to the right.
  • the silicon nitride 9 exposed on the trench wall 711 in the region of the second opening and the underlying silicon oxide 8 are removed, for example, by wet etching processes, so that a second opening is produced in the first insulating layer 8, 9, which is located at the same location as the second opening in FIG the second electrode layer 16 '. At this point, the original trench wall 7 '' is now exposed.
  • the first insulating layer 8, 9 thus has the first and the second opening, while the second insulating layer 14 and both electrode layers each have only the second opening.
  • the second opening in the first electrode layer 12 ' generally extends to a greater depth in the trench (ie the upper edge of the first electrode 12 is lower) than the other second openings, so that the capacitor dielectric 14 cannot be attacked in the last-mentioned wet etching process.
  • an approximately 500 nm thick polysilicon layer 20 is first deposited over the entire surface and etched back to approximately 100 nm, as a result of which the bit line hole 19 is already largely filled.
  • Molybdenum silicon 21, for example is applied as a suitable bit line material and structured together with the polysilicon layer 20 to form the bit line.
  • the bit line 20, 21 then runs over the trench or in the area of the bit line contact hole 19, partly in the trench 7.
  • a second conductive region becomes by diffusion out of the bit line 20, 21 via the bit line contact 22, for example during a subsequent annealing to siliconize the molybdenum 23 formed.
  • bit line contact 22 between the bit line 20, 21 and the second conductive region 23 (for example drain) of the selection transistor of the memory cell (right in the figure).
  • the bit line contact of a memory cell is therefore always arranged in the trench or on the trench wall of a memory cell adjacent in the bit line direction (here on the left).
  • the third and fourth insulating layers 17, 18 represent the isolation of the second electrode 16 with respect to the bit line 20, 21. Instead, it is also possible to directly cut the bit line hole 19 and the second opening in the second electrode layer 16 'using a photo technique, without using a fourth insulating layer 18, and after removal of the photoresist, to oxidize the entire surface or in any other way to produce a continuous third insulating layer 17.
  • the additional use of the fourth insulating layer 18 consisting of TEOS has the advantage of a better insulation effect, furthermore the requirements for the photo technology can be lower, since the bit line contact hole 19 can be further reduced by possibly forming TEOS spacers. Finally, a greater removal of the layer 18 can be accepted in the structuring of the bit line.
  • the top view of the memory matrix shows schematically the position of the memory cells in rows between the strip-shaped insulation regions 2.
  • the primary word lines 41 encapsulated with TEOS 5,6 run perpendicular to the bit lines 20, 21.
  • Cover 5.6 formed grid represents the mask for the self-aligned generation of the trenches 7.
  • the trench 7 of a memory cell has on one side the trench contact 11 to the source region of its selection transistor, on the opposite side the bit line contact 22 is arranged between the selection transistor of the adjacent memory cell and the bit line 20, 21. 7a, 11a and 22a denote the trench, trench contact and bit line contact belonging to the memory cell located in the middle.
  • the first insulating layer 8, 9 is etched with a photoresist layer that does not cover at least the areas denoted by 31 (see FIG. 3, photoresist layer 10), so that the first opening for producing the trench contact 11 is created.
  • the first electrode layer 12 ' is etched (production of the second opening in the first electrode layer 12'), so that in each trench 7 there is a first electrode which is separate from the others (see FIGS. 4 and 5).
  • the regions 32 In the direction of the word lines 41, the regions 32 must each extend at least to the insulation strips 2.
  • bit line contact hole 19 is produced by etching the fourth insulating layer 18 (cf. FIG. 6), as a result of which in subsequent steps the second opening in the second electrode layer 16 ' and is produced in the first insulating layer 8, 9 and the bit line contact 22 is produced at the second location of the trench wall.
  • the openings 32 and 33 can be congruent as indicated in FIG. 8, their overlap must at least enable the production of a sufficient bit line contact.
  • the areas 31, 32, 33 can be selected in a different form, in particular larger than indicated in the figure. They can also partially overlap.
  • the openings in the photoresist layers must be chosen larger in order to avoid adjustment errors, resolving power and the like. a. to consider. It is advantageous if the regions 31 and / or 32 and / or 33 in the second direction cover the insulation regions 2 on both sides in half.
  • the extent in the first direction is usually determined by the resolving power; particular area
  • the memory cells are arranged in rows which run parallel to the bit lines 20, 21 (first direction) and are separated from one another by the strip-shaped insulation regions 2.
  • the selection transistor is arranged on the same side of the associated capacitor, for example in the row labeled A-A all selection transistors are to the left of the associated capacitor.
  • Such a row is also shown in cross section in FIGS. 2 to 7. Accordingly, the trench contact 11 is located on the left upper trench edge, and the bit line contact 22 of the adjacent memory cell is located on the right trench upper edge. This orientation is reversed in an adjacent row of memory cells:
  • All selection transistors are to the right of the associated capacitor, trench contact 11 and bit line contact 22 are swapped accordingly. In the direction of the word lines 4 '(second direction), all the selection transistors are in a row, as are all the trenches 7.
  • This memory matrix is particularly advantageous for achieving the most compact possible cell. It places only minor demands on the photo technology used
  • the first electrodes can easily be separated from one another in different trenches.
  • a memory cell is created at each intersection of word line and bit line. Typical values for the size of such a memory cell are:
  • Word line pitch 2.1 ⁇ m
  • word line width 0.7 ⁇ m
  • bit line pitch 1.4 ⁇ m
  • bit line width 0.7 ⁇ m
  • capacitor trench 1.4 ⁇ m x 0.7 ⁇ m
  • trench depth 3 ⁇ m
  • bit line contact can be produced according to the "FOBIC" concept if, after the implantation of the peripheral transistors in the periphery, a thin nitride layer and a flowing intermediate oxide are produced (see reiteraters et al., Proc. Of the 1987 Symposium on VLSI Technology, Nagano, Japan, pp. 93 - 94).
  • bit line contact in the periphery can be opened by removing the thin nitride layer.
  • secondary word lines 40 and tertiary word lines 41 are provided, which are arranged in overlying metallization levels.
  • the secondary word line 40 is shown narrower than the tertiary word line 41.
  • the secondary word line 40 and the tertiary word line 41 run alternately in a first and an overlying second metallization level, where they are twisted:
  • the secondary word line 40 runs over a length X in the first metallization level (shown in dashed lines in the figure), is then brought up to the second metallization level via a so-called via 42, runs over a generally equally long distance in the second metallization level (solid line) and is then led back to the first metallization level via another via.
  • the tertiary word line 41 is complementary to the secondary word line, i. H. essentially parallel to it and up to the surroundings of the vias in the other metallization level; Via Via 43, it is led from the second to the first metallization level.
  • the primary word line 41 (not shown) is not applied continuously in the polysilicon layer, but rather in sections which each run, for example, over 16 cells.
  • the primary word line (or its sections) preferably runs in a straight line between two such contacts 44, 45.
  • the length X is thus related to the length of the primary word line sections, in the simplest case these two sizes are approximately the same. For reasons of clarity, the vias and contacts are shown in different sizes according to the word lines.
  • the secondary word line 40 or the tertiary word line 41 is now addressed, only that section of the primary word line is addressed over which this word line runs in the first metallization level; the 16 cells in this section are now read out. The adjacent 16 cells are not addressed. To evaluate the signal, a bit line of the addressed section is compared with one of the adjacent section. The reference bit line when reading out a cell is therefore not the next or next but one bit line as usual, but rather the sixteenth in this exemplary embodiment. These bit lines must be brought together at the sense amplifiers, for example via metal bridges.
  • the contact 44, 45 between the primary word line and the secondary word line and the via 42, 43 when changing a secondary or tertiary word line to the other metallization level should take up as little space as possible.
  • Such connections are referred to as non-nested / non-capped if neither of the two lines is widened.
  • Such connections can be implemented, for example, through contact holes filled with tungsten between the primary and secondary word lines and through vias filled with tungsten between secondary and tertiary word lines.
  • a contact 44 between the primary and secondary word lines is preferably arranged over an insulation region 2 (cf. FIG.
  • the strip of the insulation region 2 lying under a contact 44 may have a greater width, for example 1.6 ⁇ m in the case of the above-mentioned grids or structure sizes, than the strips of the insulation region 2, over which no contact 44 is arranged . It may also be necessary to widen the underlying strip of the insulation region 2 at the separation point of two sections of the primary word line, for example to 1.2 ⁇ m.
  • the space required for a via 42, 43, ie for the change of the secondary or tertiary word line to the other metallization level determines how short the sections of the primary word line may be, and thus how far apart the bit lines to be compared are.
  • an additional selection line 46 (so-called column-select line), which is connected to a central predecoder and to a sense amplifier, in the semiconductor memory arrangement.
  • the selection line 46 can be arranged in the second metallization level if the special arrangement of the secondary and tertiary word lines 40, 41, the contacts 44, 45 and the vias 42, 43 shown in FIG. 9 with a length of the primary word line sections of 16 cells is chosen.
  • this distance is determined by the dimensions of the trench 7 indicated.
  • the lines running in the direction of the bit line can also be used for another purpose, not just as selection lines in the above sense.

Landscapes

  • Semiconductor Memories (AREA)
  • Ceramic Capacitors (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

Un agencement comprend des cellules de mémoire composées de transistors MOS et de condensateurs comportant une rainure (7) automatiquement ajustée par rapport aux lignes primaires de mots (4) et aux zones d'isolation (2). Les deux électrodes des condensateurs sont situées à l'intérieur de la rainure, la première électrode étant raccordée au transistor de sélection par un contact ménagé dans la paroi de la rainure. Une ligne de bits (20, 21) isolée de la deuxième électrode (16) par des troisième et quatrième couches (17, 18) s'étend en partie au-dessus de la rainure et en partie à l'intérieur de la rainure et comprend à cet endroit un contact avec la zone conductrice du transistor adjacent de sélection. La matrice de la mémoire se compose de rangées de cellules de mémoire agencées dans la direction de la ligne de bits. Les cellules de mémoire faisant partie d'une même rangée ont leur transistor de sélection sur un côté déterminé du condensateur et les cellules de mémoire faisant partie de la rangée adjacente ont leur transistor de l'autre côté. On obtient une sécurité d'évaluation particulièrement élevée par une métallisation à deux couches et par un agencement spécial de lignes primaires, secondaires et tertiaires de mots (4', 40, 41).
PCT/EP1992/001653 1991-07-30 1992-07-20 Agencement compact de memoires a semi-conducteurs et son procede de fabrication WO1993003501A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE59204621T DE59204621D1 (de) 1991-07-30 1992-07-20 Kompakte halbleiterspeicheranordnung und verfahren zu deren herstellung.
KR1019940700278A KR100273779B1 (ko) 1991-07-30 1992-07-20 소형 반도체 스토리지 장치 및 그 제조방법
US08/182,187 US5378907A (en) 1991-07-30 1992-07-20 Compact semiconductor storage arrangement and method for its production
JP50321593A JP3431143B2 (ja) 1991-07-30 1992-07-20 コンパクト形半導体メモリデバイスおよびその製造方法
EP92916425A EP0596975B1 (fr) 1991-07-30 1992-07-20 Agencement compact de memoires a semi-conducteurs et son procede de fabrication
HK99097A HK99097A (en) 1991-07-30 1997-06-26 Compact semiconductor store arrangement and process for its production

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4125199A DE4125199C2 (de) 1991-07-30 1991-07-30 Kompakte Halbleiterspeicheranordnung, Verfahren zu deren Herstellung und Speichermatrix
DEP4125199.7 1991-07-30

Publications (1)

Publication Number Publication Date
WO1993003501A1 true WO1993003501A1 (fr) 1993-02-18

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PCT/EP1992/001653 WO1993003501A1 (fr) 1991-07-30 1992-07-20 Agencement compact de memoires a semi-conducteurs et son procede de fabrication

Country Status (9)

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US (1) US5378907A (fr)
EP (1) EP0596975B1 (fr)
JP (1) JP3431143B2 (fr)
KR (1) KR100273779B1 (fr)
AT (1) ATE131314T1 (fr)
DE (2) DE4125199C2 (fr)
HK (1) HK99097A (fr)
IE (1) IE80400B1 (fr)
WO (1) WO1993003501A1 (fr)

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US6552382B1 (en) * 2002-09-30 2003-04-22 Intelligent Sources Development Corp. Scalable vertical DRAM cell structure and its manufacturing methods

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DE19701935C1 (de) * 1997-01-21 1997-12-11 Siemens Ag Verfahren zur Herstellung eines Siliziumkondensators
US5909044A (en) * 1997-07-18 1999-06-01 International Business Machines Corporation Process for forming a high density semiconductor device
US6153902A (en) 1999-08-16 2000-11-28 International Business Machines Corporation Vertical DRAM cell with wordline self-aligned to storage trench
US6093600A (en) * 1999-10-29 2000-07-25 United Silicon, Inc. Method of fabricating a dynamic random-access memory device
DE10233760B4 (de) 2002-07-25 2007-05-03 Infineon Technologies Ag SRAM-Speicherzelle mit Älzgräben und deren Array-Anordnung
JP4801986B2 (ja) * 2005-02-03 2011-10-26 株式会社東芝 半導体記憶装置
US20100155801A1 (en) * 2008-12-22 2010-06-24 Doyle Brian S Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application

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Publication number Priority date Publication date Assignee Title
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Also Published As

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US5378907A (en) 1995-01-03
ATE131314T1 (de) 1995-12-15
JP3431143B2 (ja) 2003-07-28
EP0596975B1 (fr) 1995-12-06
HK99097A (en) 1997-08-08
IE80400B1 (en) 1998-06-17
DE4125199C2 (de) 1994-04-28
EP0596975A1 (fr) 1994-05-18
DE4125199A1 (de) 1993-02-04
JPH06509443A (ja) 1994-10-20
KR100273779B1 (ko) 2000-12-15
IE922466A1 (en) 1993-02-10
DE59204621D1 (de) 1996-01-18

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