Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/02—Containers; Seals
  • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
  • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/02—Containers; Seals
  • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
  • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
  • H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
  • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
  • H01L2224/45001—Core members of the connector
  • H01L2224/45099—Material
  • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
  • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
  • H01L2224/45124—Aluminium (Al) as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
  • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
  • H01L2224/45001—Core members of the connector
  • H01L2224/45099—Material
  • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
  • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
  • H01L2224/45147—Copper (Cu) as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/4805—Shape
  • H01L2224/4809—Loop shape
  • H01L2224/48091—Arched
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01019—Potassium [K]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01078—Platinum [Pt]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/013—Alloys
  • H01L2924/0132—Binary Alloys
  • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
  • H01L2924/097—Glass-ceramics, e.g. devitrified glass
  • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12042—LASER
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/161—Cap
  • H01L2924/1615—Shape
  • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Definitions

• This invention relates generally to a package for housing an electronic circuit. More particularly, the invention relates to a surface mount package having a composite metal base supported by a ceramic frame.
• SMT surface mount package
• the SMT substrate is formed from a plurality of ceramic layers. Each ceramic layer has certain designated functions. For example, a portion of a first ceramic layer may be metallized to permit soldering of an electronic device. A second layer may have metallized circuit traces for wire bonding. Another ceramic layer may be glass sealed to a lid encasing the chip in a hermetic package. Of course, any or all layers may be for a multiplicity of functions.
• Metallization extending from the circuit traces are soldered to contacts on a circuit board electrically interconnecting the package to the board.
• a surface mount package is favored where a low profile package is required or the space available to mount the package is limited.
• the desirability of a surface mount package increases.
• the heat generated by operation increases. If the heat is not removed, the temperature of the device rises shortening the operational life. It is therefore highly desirable to develop surface mount packages having high thermal conductivity.
• Most ceramic surface mount packages have an alumina (A1 ⁇ note_ * 0_) base.
• Alumina is selected because its coefficient of thermal expansion is close to that of silicon integrated circuits and alumina hybrid circuits.
• Prefired alumina green tape
• After firing, a dense chemically resistant substrate is formed.
• a - l -2 0 3 is a poor conductor of heat, having a thermal conductivity (T ) of 20 W/m-K.
• copper has a T of 393.7 W/m-K.
• U.S. Patent No. 4,827,082 by Horiuchi et al discloses the use of a ceramic base having better thermal conductivity than alumina. Rather than forming the base of the package from Al.O-, A1N or SiC having a thermal conductivity in excess of 140 W/m-K are chosen for the base. The device is mounted directly to the A1N or SiC base resulting in an eight fold improvement in thermal conductivity.
• Aluminum nitride and silicon carbide are more expensive than alumina and more difficult to shape. Care must be take during firing to prevent oxidation of aluminum nitride back to Al 2 0 3 .
• a metallic heat sink is soldered to an alumina substrate opposite the integrated circuit device.
• the heat sink is selected to be a composite material having high thermal conductivity and a relatively low coefficient of thermal expansion.
• Disclosed substrates include molybdenum clad copper and copper clad molybdenum. Proper selection of cladding thickness adjusts the coefficient of thermal expansion to a desired quantity.
• a disadvantage with this approach is that an insulative alumina layer is disposed between the integrated circuit device and the heat sink. The removal of heat from the chip is limited by the conduction of heat through the alumina layer.
• An infiltrated base has limitations. All pores in the skeleton must be filled with the molten copper. Any air gaps reduce thermal conductivity. When the concentration of the tungsten is high, above about 65% by volume (80% by weight), the infiltrated composite becomes difficult to shape by forging or other deformation processes. Machining is required, necessitating piece by piece manufacture and the generation of scrap increasing the cost of the composite. Accordingly, it is an object of the invention to provide a ceramic surface mount package which does not have the disadvantages of the prior art. It is a feature of the invention that in one embodiment the package has a ceramic frame and a pressed powder copper-tungsten base. The base is preferably brazed to the frame. Another feature of the invention is that both the integrated circuit device and the bond wires are attached directly to the composite material. Yet another feature of the invention is that the package may be sealed by seam welding a metallic lid.
• Advantages of the surface mount package of the invention include improved thermal conductivity and better electrical properties in the form of lower resistance than provided by the prior art.
• Another advantage of the SMT of the invention is that electrically conductive vias may be recessed below the body of the ceramic frame to minimize electrical short circuits.
• Yet another advantage is that the package may be sealed by seam welding minimizing exposure of the device to elevated temperatures.
• a package for use in encapsulating an electronic device includes a ceramic frame having first and second sides and a plurality of apertures. A plurality of metallic components are bonded to the frame. A separate metallic component extends across each of the apertures.
• Figure 1 shows in cross-sectional representation a ceramic surface mount package as known from the prior art.
• Figure 2 shows in cross-sectional representation a ceramic surface mount package containing a plurality of apertures sealed with a composite material in accordance with the invention.
• Figure 3 shows in cross-sectional representation the surface mount package of the invention having a seam welded metallic lid.
• Figures 4A and 4B show in bottom planar view and top planar view, respectively, a ceramic frame and metallization used in the assembly of the surface mount package of the invention.
• Figures 5A and 5B show in bottom planar view and top planar view, respectively, the surface mount package of the invention subsequent to brazing a chip attach pad, electrically conductive vias and seal ring.
• Figure 1 shows in cross-sectional representation a ceramic surface mount package 10 as known from the prior art.
• the package 10 has a ceramic body 12 defining a cavity 14 for housing an integrated circuit device.
• a first metallic plate 16 and second metallic plate 18 are bonded to an interior surface 20 of the ceramic body 12. Both the first 16 and second 18 metallic plates are formed from copper-tungsten.
• the cavity 14 has a limited depth, so the thickness of the first metallic plate 16 is limited to about .25mm (10 mils), while the second metallic plate 18 is about .76mm (30 mils) thick.
• a third metallic plate 22 and fourth metallic plate 24 are bonded to an exterior surface 26 of the ceramic body 12 opposite the first 16 and second 18 metallic plates to provide electrical connection to external circuitry.
• the third 22 and fourth 24 metallic plates are formed from copper-tungsten and have a thickness of about .25mm (10 mils).
• Metallized vias 28 conduct heat and electrical impulses from the first 16 and second 18 metallic plates to the third 22 and fourth 24 metallic plates.
• the vias are formed from a fired tungsten paste.
• the thermal and electrical limitations of the prior art SMT package 10 originate with the metallized vias 28.
• the vias 28 occupy a limited area between metallic plates. The remainder of the area is thermally and electrically insulating A1 2 0 3 . Both the thermal conductivity and electrical conductivity are limited by the cross-sectional dimension of the metallized vias 28.
• FIG. 2 shows in cross-sectional representation a surface mount package 30 which does not suffer the limitations of the prior art package.
• the surface mount package 30 has a ceramic frame 32.
• the ceramic frame has a first, exterior facing, side 33 and a second, interior facing, side 35.
• Extending through the ceramic frame 32 are a plurality of apertures 34.
• the plurality of apertures 34 are sealed by separate metallic components 36, 38 which each extend across an aperture 34 sealing one end.
• the ceramic frame 32 is manufactured from a suitable ceramic which is thermally stable at elevated temperatures, chemically resistant and resistant to gas diffusion.
• a preferred ceramic is alumina (A1_0-.).
• Other suitable ceramics such as aluminum nitride and silicon carbide may be used.
• the ceramic may include various fillers to influence its properties. For example, a pigment may be added to impart the ceramic with a desired coloration. One preferred color is black for cosmetic reasons or to improve infrared absorption to assist soldering.
• the first 36 and second 38 metallic components are formed from a material having good thermal conductivity and a coefficient of thermal expansion close to that of the ceramic frame 32. While low expansion metals such as molybdenum and iron nickel alloys such as alloy 42 (42% nickel, remainder iron) meet these requirements, more preferred are composite materials having high thermal and electrical conductivity.
• the preferred materials include composites having a molybdenum or tungsten matrix and a high thermal conductivity, high electrical conductivity second phase.
• the second phase may be copper, silver, a copper alloy or a silver alloy. Most preferred is a composite of copper and tungsten.
• the concentration of copper is preferably between about 5% and about 25% by weight. More preferably, the copper concentration is between about 10% and about 20% and most preferably from about 12% to about 16%.
• the composite may be formed by any suitable process such as infiltration of a tungsten skeleton by molten copper or by powder metallurgy. To facilitate shaping of the metallic components, powder metallurgy is preferred.
• the first metallic component 36 and second metallic component 38 may be a plate extending across the apertures 34.
• both the first 36 and second 38 metallic components are shaped to include a flange 40 and a pedestal 42.
• the flange 40 is bonded to one side of the ceramic frame 32 by soldering, brazing or other means of adhesion.
• the pedestal 42 extends into the aperture 34 to receive an integrated circuit device.
• the second metallic component 38 contains a flange 44 and pedestal 46.
• the flange 44 is for bonding to the ceramic frame 32 and the pedestal 46 is for receiving wire bonds.
• the surface mount package 30 is sealed by soldering or glass sealing a lid to the ceramic frame 32 opposite the metallic components.
• a seal ring 8 manufactured from a low expansion metal such as Kovar (nominal composition by weight 53% Fe, 17% Co and 29% Ni) is brazed to the ceramic frame 32.
• seam welding is preferred over soldering or glass sealing because the sealing energy is concentrated at the interface of the lid and the seal ring 48. It is not necessary to elevate the entire package to the sealing temperature, typically in excess of 300°C. The microelectronic device is not subjected to elevated temperatures and sealing does not require a controlled atmosphere.
• Figure 3 shows in cross-sectional representation a completed SMT package 50.
• An integrated circuit device 52 is bonded to the pedestal 42 of the first metallic component 36.
• the coefficient of thermal expansion of the first metallic component 36 is approximately equal to that of the alumina or silicon based integrated circuit 52, so any conventional die attach material may be used.
• Preferred die attach materials are eutectic gold solders such as gold tin and gold silicon.
• the preferred composite metal having a copper concentration of about 15% and the remainder tungsten has a thermal conductivity of about 167 W/m-K and an electrical conductivity of about 35% IACS. There is no interposing alumina to isolate the chip from the metallic heat sink. The entire chip is in contact with the heat sink improving thermal transfer.
• the second metallic component 38 preferably includes pedestal 46 which does not extend above the surface of the ceramic frame 32.
• the central portion 54 of the ceramic frame is higher than either pedestal 42 or pedestal 46.
• a bond wire 56 electrically interconnects the integrated circuit device 52 with the second metallic component 38.
• the bond wire 56 is typically manufactured from copper or aluminum and has a thickness of about 38mm (.015 inches).
• the thin bond wire 56 is subject to distortion and wire bond sag as a result of the package being exposed to heat or acceleration.
• Forming the central portion 54 of the ceramic frame 32 to be the highest portion within the SMT package 50 insures that if the bond wire 56 sags or moves, the wire will contact the central portion 54 rather than a metallic component. Wire sag or wire movement will not result in an electrical short circuit.
• the SMT package 50 is sealed with a metallic cover 58.
• the metallic cover 58 is preferably Kovar or another metal having a coefficient of thermal expansion approximately equal to that of the ceramic frame 32.
• the metallic cover 58 is bonded to seal ring 48 by a process such as seam welding. In seam welding, arc or resistance welding produces a series of overlapping spot welds which form a continuous, hermetic seal.
• the assembled package is then soldered to a printed circuit board or other external circuitry such that exterior surfaces of the first 36 and second 38 metallic components are bonded to and electrically interconnected to the external circuitry.
• Figures 4A and 4B show the assembly of the SMT package of the invention.
• Figure 4A shows an intermediate assembly step in bottom planar view while Figure 4B shows the same intermediate assembly step in top planar view.
• An alumina substrate is provided with apertures 34, 34' by laser drilling.
• a CO understand laser cuts the apertures to form ceramic frame 32.
• the ceramic frame 32 is selectively metallized with tungsten paste 60.
• the tungsten paste 60 is applied on the backside of the ceramic frame as illustrated in Figure 4A to define the bonding locations of the first metallic component which extends across aperture 34 and at least one second metallic component extending across aperture 34'. Either simultaneously or as a sequential operation, tungsten metallization is applied to the front side of the ceramic frame 32 as illustrated in Figure 4B for bonding the seal ring.
• the tungsten metallization is generally applied by a screen printing operation which provides an accurate deposition of a controlled thickness of tungsten.
• the tungsten paste is preferably screened to a thickness which will produce a post firing thickness of from about 25 microns (1000 microinches) to about 75 microns (3000 microinches) .
• Metallizations other than tungsten, such as moly manganese may also be utilized.
• the ceramic frame 32 is then fired at an elevated temperature of about 1400°C to fire the tungsten paste. Firing converts the tungsten paste into tungsten metal and binds the tungsten to the ceramic substrate.
• the fired tungsten paste is nickel plated in an electrolytic bath to a thickness of from about 1.25 microns (50 microinches) to 3.75 microns (150 microinches) .
• the plated substrate may be sintered by heating to a temperature of about 600°C in a reducing atmosphere.
• the metallic components are a mixture of copper and tungsten. It is preferred to deposit a layer of nickel on the metallic components. However, adhesion of nickel to the tungsten is not satisfactory due to residual refractory oxides. Using a preplate activation process sufficiently aggressive to remove refractory oxides attacks the copper constituent of the component producing an uneven surface. Applicants have discovered that the deposition of a flash about .25 microns (10 microinches) to .63 microns (25 microinches) of gold deposited from an electrolytic bath can be deposited on the composite.
• nickel of a desired thickness about 1.25 microns (50 microinches) to about 3.75 microns (150 microinches) may be deposited on the gold by standard electrolytic deposition.
• the metallic components are then ready for brazing to the ceramic frame.
• the Kovar seal ring is preferably coated with from about 1.25 microns (50 microinches) to 3.75 microns (150 microinches) of nickel prior to brazing.
• the metallization on the ceramic frame 32, the metallic components and the seal ring are nickel plated, the assembly is bonded. Any suitable adhesion technique may be used. Brazing with the copper/silver eutectic referred to as BT (nominal composition 72% copper/28% silver) is preferred.
• the braze either as a paste or preform is disposed between the metallized surfaces 60 of the ceramic frame 32 and the flanges of the first and second metallic components and the seal ring.
• the metallic components are positioned so the pedestals extend into the apertures 34, 34'. Alignment is maintained using a fixture such as a graphite boat.
• the assembly is brazed by heating to a temperature of about 780°C in hydrogen.
• the SMT package is then essentially as shown by reference numeral 30 in Figure 2.
• the brazed assembly is illustrated in bottom planar view in Figure 5A and top planar view in Figure 5B.
• brazed to the ceramic frame 32 are the first metallic component 36 and one or more second metallic components 38.
• the seal ring 48 is brazed to the perimeter of the ceramic frame 32.
• the first pedestal 42 extends into the aperture 34 for receiving an integrated circuit device.
• One or more second pedestals 46 extend into the apertures 34' to receive the bond wires.
• the assembly 30 may be gold plated with from about .75 microns (30 microinches) to about 1.5 microns (60 microinches) of gold.
• the BT braze or metallic components and seal ring To prevent diffusion of the gold into the BT braze or metallic components and seal ring, it is preferably to deposit from about 1.25 microns (50 microinches) to about 3.75 microns (150 microinches) of nickel by an electroless process onto all metallized surfaces of the assembly prior to gold plating. After gold plating, the chip is attached and wire bonded. The lid is then s -aled to the seal ring completing the SMT package.
• Ceramic powder may be pressed into a mold having the desired shape including the apertures.
• the powder can be injection molded to precise dimensions.
• the powder is pressed into a loose compact which has sufficient integrity for tungsten metallization.
• the compact and metallization are fired by heating to a temperature of about 1550 C.
• the metallized ceramic frame is then further processed as above.
• While the metallic components have been illustrated as bonded to the exterior facing surface of the ceramic frame, it is within the scope of the invention to bond some or all the metallic components to the interior facing surface of the ceramic frame.
• the pedestals then extend through the apertures and outwardly from the package.
• This configuration is particularly suited for pin grid array and pad array packages. While the package and assembly process have been described in terms of a surface mount package, other ceramic packages such as leadless chip carriers, cerdips or cerquads are also applicable. Ceramic pin grid array packages are particularly suited for a ceramic substrate having a plurality of metallic contact pads on an exterior surface extending into apertures on an inside surface.

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• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
• Ceramic Products (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (2)

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• 1991
  • 1991-03-29 US US07/677,078 patent/US5111277A/en not_active Expired - Lifetime
• 1992
  • 1992-02-12 EP EP92909877A patent/EP0577731A1/en not_active Ceased
  • 1992-02-12 AU AU16847/92A patent/AU1684792A/en not_active Abandoned
  • 1992-02-12 WO PCT/US1992/001166 patent/WO1992017902A2/en not_active Ceased
  • 1992-02-12 JP JP4509057A patent/JPH06506321A/ja active Pending

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