US9701902B2 - Etching method, method of manufacturing article, and etching solution - Google Patents

Etching method, method of manufacturing article, and etching solution Download PDF

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US9701902B2
US9701902B2 US14/845,818 US201514845818A US9701902B2 US 9701902 B2 US9701902 B2 US 9701902B2 US 201514845818 A US201514845818 A US 201514845818A US 9701902 B2 US9701902 B2 US 9701902B2
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etching
mol
etching solution
organic additive
catalyst layer
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US20160079078A1 (en
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Yusaku ASANO
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
    • C09K13/08—Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Definitions

  • Embodiments described herein relate generally to an etching technique.
  • microstructure manufacturing processes such as processes of manufacturing microelectromechanical system (MEMS) and through-silicon via (TSV)
  • MEMS microelectromechanical system
  • TSV through-silicon via
  • etching As semiconductor etching, generally used are isotropic wet etching using an etching solution containing hydrofluoric acid, nitric acid, and acetic acid, anisotropic etching using an alkali solution such as tetramethylammonium hydroxide (TMAH) or KOH, and dry etching using a plasma of an etching gas such as SF 6 or CF 4 .
  • TMAH tetramethylammonium hydroxide
  • KOH tetramethylammonium hydroxide
  • high-aspect-ratio deep etching can be performed by using an etching rate difference corresponding to the crystal orientation of a semiconductor.
  • the shape of a pattern to be formed by etching and the crystal orientation of a semiconductor must be so determined that the etching rate in the depth direction is much higher than that in the widthwise direction. That is, the shape of a structure to be formed by etching is limited, so design limitations are large.
  • the deep etching techniques using dry etching include a technique called a Bosch process.
  • a Bosch process plasma etching using SF 6 gas or the like and sidewall protective film formation using C 4 F 8 gas or the like are alternately repeated.
  • This technique has a problem that a fluorocarbon-based deposit remains on sidewalls and exerts influence on the performance of the device.
  • This technique also has a problem that sidewalls are formed into a scalloped shape.
  • MacEtch metal-assisted chemical etching
  • FIG. 1 is a sectional view schematically showing an insulating layer formation step in an etching method according to an embodiment
  • FIG. 2 is a sectional view schematically showing a catalyst layer formation step in the etching method according to the embodiment
  • FIG. 3 is an electron micrograph of the upper surface of the catalyst layer
  • FIG. 4 is a sectional view schematically showing a dipping step in the etching method according to the embodiment
  • FIG. 5 is a sectional view schematically showing an example of a structure obtained by an etching method using no organic additive
  • FIG. 6 is an electron micrograph of a section of the structure obtained by the etching method using no organic additive
  • FIGS. 7A, 7B, 7C, 7D, and 7E are electron micrographs showing sections of structures obtained by etching methods using no organic additives
  • FIG. 8 is a sectional view schematically showing an example of a structure obtained by the etching method according to the embodiment.
  • FIG. 9 is a schematic sectional view for explaining the reason why needle-like residual portions hardly form.
  • FIG. 10 is a schematic sectional view for explaining the reason why the needle-like residual portions hardly form
  • FIG. 11 is an electron micrograph of a section of a structure obtained by the etching method according to the embodiment.
  • FIG. 12 is an electron micrograph of a section of a structure obtained by an etching method using no organic additive
  • FIG. 22 is an electron micrograph of a section of a structure obtained by an etching method using no organic additive
  • FIG. 29 is an electron micrograph of a section of a structure obtained when using succinic acid as an organic additive
  • FIG. 30 is an electron micrograph of a section of a structure obtained when using malic acid as an organic additive
  • FIG. 31 is an electron micrograph of a section of a structure obtained when using dipropyl amine as an organic additive
  • FIG. 32 is an electron micrograph of a section of a structure obtained when using alanine as an organic additive
  • FIG. 33 is a plan view schematically showing an insulating layer formation step in a semiconductor device manufacturing method according to an embodiment
  • FIG. 34 is a sectional view taken along a line XXXIV-XXXIV of the structure shown in FIG. 33 ;
  • FIG. 35 is a plan view schematically showing a catalyst layer formation step in the semiconductor device manufacturing method according to the embodiment.
  • FIG. 36 is a sectional view taken along a line XXXVI-XXXVI of the structure shown in FIG. 35 ;
  • FIG. 37 is a plan view schematically showing an example of the structure obtained by the method shown in FIGS. 33, 34, 35, and 36 ;
  • FIG. 38 is a sectional view taken along a line XXXVIII-XXXVIII of the structure shown in FIG. 37 .
  • a structure 10 shown in FIG. 1 is first prepared.
  • the structure 10 is made of a semiconductor.
  • This semiconductor is selected from semiconductors made of Si, Ge, compounds of group-III and group-V elements such as GaAs and GaN, and SiC. Note that a term “group” herein used is “a group” in the short-form periodic table.
  • the structure 10 is, e.g., a semiconductor wafer.
  • An impurity can be doped in this semiconductor wafer, or a semiconductor element such as a transistor or diode can be formed on the semiconductor wafer.
  • the principal surface of the semiconductor wafer can be parallel to any crystal plane of the semiconductor.
  • an insulating layer 20 is formed on the structure 10 .
  • the insulating layer 20 has an opening.
  • a region 11 of the structure 10 which corresponds to the opening of the insulating layer, is removed by etching.
  • any material can be used as the material of the insulating layer 20 , provided that the material can suppress deposition of a noble metal (to be described later) on a region of the surface of the structure 10 , which is covered with the insulating layer 20 .
  • the material are organic materials such as polyimide, a fluorine resin, a phenolic resin, an acrylic resin, and a novolak resin, and inorganic materials such as silicon oxide and silicon nitride.
  • the insulating layer 20 can be formed by, e.g., existing semiconductor processes.
  • the insulating layer 20 made of an organic material can be formed by, e.g., photolithography.
  • the insulating layer 20 made of an inorganic material can be formed by, e.g., deposition of an insulating layer by vapor phase deposition, formation of a mask by photolithography, and patterning of the insulating layer by etching.
  • the insulating layer 20 made of an inorganic material can be formed by oxidation or nitriding of the surface region of the structure 10 , formation of a mask by photolithography, and patterning of an insulating layer by etching.
  • a catalyst layer 30 is formed on the region 11 as shown in FIG. 2 .
  • the catalyst layer 30 is an aggregate of a plurality of particles 31 each made of a noble metal.
  • the catalyst layer 30 is used to activate the oxidation reaction of the semiconductor that constitutes the region 11 in contact with the catalyst layer 30 .
  • the noble metal can be selected from, e.g., Au, Ag, Pt, Pd, and combinations thereof.
  • the shape of the noble metal particle 31 is preferably spherical.
  • the noble metal particle 31 may also have another shape such as a rod-like shape or plate-like shape.
  • the particle size of the noble metal particle 31 is not particularly limited as long as the particle size is much smaller than the width of the region 11 .
  • the particle size of the noble metal particle 31 is several tens of nm to several hundreds of nm, and typically, 50 to 200 nm.
  • SEM scanning electron microscope
  • a proportion of the total area of the noble metal particles 31 in the area of the viewing field is, e.g., 50% to 90%, and typically, 75% to 85%.
  • the particle size is a value obtained by the following method. First, the principal surface of the catalyst layer 30 is photographed using an SEM. The magnification is ⁇ 10,000 to ⁇ 100,000. Then, wholly seen particles 31 are selected from the image, and the area of each of the selected particles 31 is obtained. Subsequently, assuming that each particle 31 is a sphere, the diameter of the particle 31 is obtained from the area. This diameter is the particle size of the particle 31 .
  • the catalyst layer 30 can be formed by, e.g., electroplating, reduction plating, or displacement plating.
  • the catalyst layer 30 can also be formed by application of a dispersion containing noble metal particles, or vapor phase deposition such as evaporation or sputtering. Of these methods, displacement plating is particularly favorable because it is possible to directly and evenly deposit a noble metal on the region 11 .
  • the deposition of a noble metal by displacement plating can be performed by using, e.g., a silver nitrate solution.
  • a silver nitrate solution An example of the process will be explained below.
  • a displacement plating solution is, e.g., a solution mixture of a silver nitrate solution, hydrofluoric acid, and water.
  • Hydrofluoric acid has a function of removing a native oxide film from the surface of the structure 10 .
  • the structure 10 When the structure 10 is dipped in the displacement plating solution, a native oxide film on the surface of the structure 10 is removed, and a noble metal, silver in this case, is deposited on a portion of the surface of the structure 10 , which is not covered with the insulating layer 20 . As a consequence, the catalyst layer 30 is obtained.
  • the silver nitrate concentration in the displacement plating solution is preferably 0.001 to 0.01 mol/L.
  • the hydrofluoric acid concentration in the displacement plating solution is preferably 0.1 to 6.5 mol/L.
  • the electron micrograph of FIG. 3 is an SEM image showing the upper surface of the catalyst layer 30 .
  • the catalyst layer 30 was formed by using an aqueous solution containing 0.005 mol/L of silver nitrate and 1.0 mol/L of hydrogen fluoride as the displacement plating solution, and dipping a 10 mm ⁇ 10 mm silicon chip in this displacement plating solution at 25° C. for 3 min.
  • white portions are silver particles. The particle sizes of these particles are about 100 nm.
  • the etching solution 40 contains hydrofluoric acid, an oxidizer, and an organic additive.
  • the semiconductor is oxidized in only portions of the region 11 that are close to the noble metal particles 31 , and a generated oxide is dissolved away by hydrofluoric acid. Therefore, only the portions close to the noble metal particles 31 are selectively etched.
  • the noble metal particles 31 do not chemically change and move downward as the etching progresses, and the same etching as described above is performed there. Consequently, as shown in FIG.
  • etching progresses in a direction perpendicular to the upper surface of the structure 10 .
  • etching does not progress, and the semiconductor remains in the shape of needles. That is, needle-like residual portions 12 are generated.
  • the micrograph of FIG. 6 is an SEM image showing a section of a structure obtained when using an etching solution containing only hydrofluoric acid and an oxidizer.
  • a catalyst layer 30 was formed on a silicon ship, which was the structure 10 , under the same conditions as those for the catalyst layer 30 shown in FIG. 3 , an aqueous solution containing 10 mol/L of hydrogen fluoride and 2 mol/L of hydrogen peroxide was used as an etching solution, and the structure 10 was dipped in the etching solution for 30 min.
  • reference symbol R denotes a region (catalyst layer formation region) where the catalyst layer 30 was formed.
  • FIGS. 7A, 7B, 7C, 7D, and 7E are SEM images each showing a section of a structure obtained when using etching solutions containing only hydrofluoric acid and an oxidizer.
  • a catalyst layer 30 was formed on a silicon chip, which was the structure 10 , under the same conditions as those for the structure 30 shown in FIG. 3 .
  • an aqueous solution containing 20 mol/L of hydrogen fluoride and 1 mol/L of hydrogen peroxide was used as the etching solution.
  • FIG. 7A an aqueous solution containing 20 mol/L of hydrogen fluoride and 1 mol/L of hydrogen peroxide was used as the etching solution.
  • an aqueous solution containing 10 mol/L of hydrogen fluoride and 2 mol/L of hydrogen peroxide was used as the etching solution.
  • an aqueous solution containing 5 mol/L of hydrogen fluoride and 4 mol/L of hydrogen peroxide was used as the etching solution.
  • an aqueous solution containing 4 mol/L of hydrogen fluoride and 5 mol/L of hydrogen peroxide was used as the etching solution.
  • an aqueous solution containing 2.5 mol/L of hydrogen fluoride and 8 mol/L of hydrogen peroxide was used as the etching solution.
  • the structure 10 was dipped in each etching solution for 30 min.
  • the present inventor made extensive studies on the composition of an etching solution for use in the MacEtch method. As a consequence, the present inventor has found a composition which can achieve a high aspect ratio and hardly generates the needle-like residual portions 12 .
  • the etching solution 40 herein used contains hydrofluoric acid, an oxidizer, and an organic additive.
  • etching progresses in those portions of the region 11 , which are close to the noble metal particles 31 , and also progresses in other portions of the region 11 . Consequently, as shown in FIG. 8 , the generation of the needle-like residual portions 12 is suppressed, and a recess 14 having a high aspect ratio is obtained.
  • the concentration of hydrogen fluoride in the etching solution 40 is preferably 1 to 20 mol/L, more preferably, 5 to 10 mol/L, and most preferably, 3 to 7 mol/L. If the hydrogen fluoride concentration is low, a high etching rate is difficult to achieve. If the hydrogen fluoride concentration is high, excess side etching may occur.
  • the oxidizer can be selected from, e.g., AgNO 3 , KAuCl 4 , HAuCl 4 , K 2 PtCl 6 , H 2 PtCl 6 , Fe(NO 3 ) 3 , Ni(NO 3 ) 2 , Mg(NO 3 ) 2 , Na 2 S 2 O 8 , K 2 S 2 O 8 , KMnO 4 , and K 2 Cr 2 O 7 .
  • Hydrogen peroxide is favorable as the oxidizer because hydrogen peroxide does not form any harmful byproduct and does not contaminate a semiconductor element.
  • the concentration of the oxidizer in the etching solution 40 is preferably 0.2 to 8 mol/L, more preferably, 2 to 4 mol/L, and most preferably, 3 to 4 mol/L.
  • the molecules of the organic additive are, e.g., polar molecules.
  • An organic additive like this is generally water-soluble.
  • the molecular weight of the organic additive is preferably 60 to 20,000, and more preferably, 60 to 1,000. Note that when the organic additive is a polymer compound, its molecular weight is a weight-average molecular weight.
  • organic additive it is possible to use one or more compounds selected from the group consisting of, e.g., alcohol, carboxylic acid, hydroxy acid, amine, amino acid, thiols, an organic fluorine compound, and a chelating agent.
  • alcohol it is possible to use ethylene glycol, diethylene glycol, polyethylene glycol, 1,4-butanediol, 1,6-hexanediol, or a combination thereof.
  • carboxylic acid it is possible to use monocarboxylic acid, polycarboxylic acid, or a combination thereof.
  • polycarboxylic acid it is possible to use dicarboxylic acid such as malonic acid or succinic acid.
  • carboxylic acid it is possible to use one type of compound or a plurality of types of compounds.
  • hydroxy acid it is possible to use, e.g., malic acid, citric acid, or a combination thereof.
  • amine it is possible to use, e.g., propylamine, dipropylamine, or a combination thereof.
  • amino acid it is possible to use, e.g., glycine, alanine, or a combination thereof.
  • organic fluorine compound heptafluorobutyric acid or the like can be used.
  • the chelating agent it is possible to use, e.g., diethylenetriamine pentaacetic acid, ethylenediamine tetraacetic acid, or a combination thereof.
  • one or more compounds selected from the group consisting of polyethylene glycol, succinic acid, malic acid, dipropylamine, and alanine are used as the organic additive.
  • the concentration of the organic additive in the etching solution 40 is preferably 0.001 to 5 mass %, more preferably, 0.01 to 1 mass %, and most preferably, 0.05 to 0.2 mass %.
  • the use of the organic additive suppresses the generation of the needle-like residual portions 12 , so a recess having a high aspect ratio is obtained.
  • the present inventor considers the reason for this as follows, although the present inventor does not want to be bound by a theory. Assume that the structure 10 is a silicon wafer.
  • the deposition amount of an organic additive 41 to a unit amount of the semiconductor is larger in the distal end portions P 3 of the needle-like residual portions 12 than in other portions of the structure 10 .
  • the organic additive attracts holes by the polarity.
  • the oxidizer and hydrofluoric acid are supplied to the distal end portions P 3 of the needle-like residual portions 12 from not only the region above them but also the gaps between them. Consequently, as shown in FIG. 10 , silicon oxidation by the oxidizer and removal of the generated oxide by dissolution by hydrofluoric acid are promoted in the distal end portions of the needle-like residual portions 12 . Accordingly, the generation of the needle-like residual portions 12 is suppressed, and a recess having a high aspect ratio is obtained.
  • the organic additive when the organic additive behaves as a complexing agent which forms a complex together with an element, silicon in this case, which forms the structure, the organic additive may accelerate dissolution of silicon in a portion of the structure 10 where holes exist. At least some excess holes generated by silicon oxidation move to the needle-like residual portions 12 .
  • the specific surface area of the needle-like residual portion 12 is larger than those of other portions of the structure 10 . In the needle-like residual portion 12 , therefore, etching of silicon by complexation occurs more easily than in other portions of the structure 10 . Accordingly, the generation of the needle-like residual portions 12 is suppressed, and a recess having a high aspect ratio is obtained.
  • the organic additive behaves as a surfactant, and promotes circulation of the etching solution from the gaps between the needle-like residual portions 12 to other regions and vice versa.
  • the specific surface area of the distal end portion of the needle-like residual portion 12 is larger than those of other portions of the structure 10 .
  • the micrograph of FIG. 11 is an SEM image showing a section of a structure obtained when using an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive.
  • a catalyst layer 30 was formed on a silicon chip as the structure 10 under the same conditions as those for the catalyst layer 30 shown in FIG. 3 .
  • the structure 10 was dipped in this etching solution for 30 min.
  • the micrograph of FIG. 12 is an SEM image showing a section of a structure obtained when using an etching solution containing only hydrofluoric acid and an oxidizer.
  • the micrographs of FIGS. 13, 14, 15, 16, 17, 18, 19, 20 , and 21 are SEM images each showing a section of a structure obtained when using an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive.
  • a catalyst layer 30 was formed on a silicon chip as the structure 10 under the same conditions as those for the catalyst layer 30 shown in FIG. 3 . Then, the structure 10 was dipped in the etching solution for 30 min.
  • an aqueous solution containing 5 mol/L of hydrogen fluoride and 4 mol/L of hydrogen peroxide was used as the etching solution.
  • the micrograph of FIG. 22 is an SEM image showing a section of a structure obtained when using an etching solution containing only hydrofluoric acid and an oxidizer.
  • the micrographs of FIGS. 23, 24, 25, 26, 27, 28, 29, 30, 31, and 32 are SEM images each showing a section of a structure obtained when using an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive.
  • a catalyst layer 30 was formed on a silicon chip as the structure 10 under the same conditions as those for the catalyst layer 30 shown in FIG. 3 . Then, the structure 10 was dipped in the etching solution for 30 min.
  • an aqueous solution containing 5 mol/L of hydrogen fluoride and 4 mol/L of hydrogen peroxide was used as the etching solution.
  • an aqueous solution containing 5 mol/L of hydrogen fluoride, 4 mol/L of hydrogen peroxide, and 0.1 mass % of succinic acid was used as the etching solution.
  • an aqueous solution containing 5 mol/L of hydrogen fluoride, 4 mol/L of hydrogen peroxide, and 0.1 mass % of malic acid was used as the etching solution.
  • an aqueous solution containing 5 mol/L of hydrogen fluoride, 4 mol/L of hydrogen peroxide, and 0.1 mass % of dipropylamine was used as the etching solution.
  • an aqueous solution containing 5 mol/L of hydrogen fluoride, 4 mol/L of hydrogen peroxide, and 0.1 mass % of alanine was used as the etching solution.
  • the method according to the embodiment can perform high-aspect-ratio deep etching by a simple wet process. That is, the embodiment provides an etching technique capable of anisotropic etching.
  • the aggregate of the plurality of particles 31 each made of a noble metal was used as the catalyst layer 30 , but the catalyst layer 30 may also have another form.
  • the catalyst layer 30 may also be obtained by forming a plurality of through holes in a continuous layer.
  • the above-described etching method can be used to manufacture various articles.
  • the above-described etching method can be used to manufacture a semiconductor device, a circuit board such as an interposer, or a stamper for use in nanoimprinting.
  • a substrate such as a protective substrate, which has a recess in one principal surface and forms a hollow structure when bonded to another substrate.
  • This etching method is also usable to form a recess such as a trench or a through hole such as a via hole.
  • the etching method can also be used to divide a structure such as a substrate.
  • FIGS. 33, 34, 35, 36, 37, and 38 illustrate a method of dividing a semiconductor wafer into a plurality of semiconductor chips.
  • This structure includes a semiconductor wafer 10 , insulating layer 20 , and dicing sheet 50 .
  • Semiconductor elements 13 are formed in the surface region of the semiconductor wafer 10 .
  • the insulating layer 20 covers a region of the semiconductor wafer 10 , in which the semiconductor elements 13 are formed, and protects the semiconductor elements 13 against damage.
  • the dicing sheet 50 is adhered on a surface of the semiconductor wafer 10 , which is opposite to the surface on which the protective layer 20 is formed.
  • the catalyst layer 30 is an aggregate of a plurality of particles 31 each made of a noble metal.
  • etching is performed by using an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive. More specifically, the structure shown in FIGS. 35 and 36 is dipped in the etching solution so as to remove a portion of the semiconductor wafer 10 that is positioned below the catalyst layer 30 . Thus, a semiconductor chip 10 ′ each including the semiconductor element 13 is obtained as shown in FIGS. 37 and 38 .
  • the insulating layer 20 can be used as, e.g., a protective layer for protecting the semiconductor chip 10 ′.
  • the insulating layer 20 covers the entire surface of the semiconductor chip 10 ′. Therefore, this method can achieve a high strength as compared with the case where general dicing using a blade is performed.
  • the shape of the upper surface of the semiconductor chip 10 ′ is not limited to a square or rectangle.
  • the upper surface shape of the semiconductor chip 10 ′ may also be a circle or triangle.
  • this method can simultaneously form semiconductor chips 10 ′ having different upper surface shapes.

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