US8987876B2 - Power overlay structure and method of making same - Google Patents

Power overlay structure and method of making same Download PDF

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Publication number
US8987876B2
US8987876B2 US13/897,638 US201313897638A US8987876B2 US 8987876 B2 US8987876 B2 US 8987876B2 US 201313897638 A US201313897638 A US 201313897638A US 8987876 B2 US8987876 B2 US 8987876B2
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semiconductor device
thermal interface
layer
coupled
pol
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US20140264799A1 (en
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Arun Virupaksha Gowda
Paul Alan McConnelee
Shakti Singh Chauhan
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General Electric Co
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General Electric Co
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Assigned to GENERAL ELECTRIC COMPANY reassignment GENERAL ELECTRIC COMPANY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GOWDA, ARUN VIRUPAKSHA, CHAUHAN, SHAKTI SINGH, MCCONNELEE, PAUL ALAN
Priority to US13/897,638 priority Critical patent/US8987876B2/en
Priority to TW103107092A priority patent/TWI628750B/zh
Priority to TW107117243A priority patent/TWI703681B/zh
Priority to JP2014048289A priority patent/JP6595158B2/ja
Priority to KR1020140029835A priority patent/KR102151047B1/ko
Priority to CN202010052240.1A priority patent/CN111508912B/zh
Priority to CN201410094386.7A priority patent/CN104051377B/zh
Priority to EP14159735.1A priority patent/EP2779230B1/en
Publication of US20140264799A1 publication Critical patent/US20140264799A1/en
Priority to US14/665,735 priority patent/US9704788B2/en
Publication of US8987876B2 publication Critical patent/US8987876B2/en
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Priority to US15/601,735 priority patent/US20170263539A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H01L23/49568—
    • H01L23/3677—
    • H01L23/4334—
    • H01L23/5389—
    • H01L24/19—
    • H01L24/24—
    • H01L24/83—
    • H01L24/92—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/461—Leadframes specially adapted for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H01L2224/04105—
    • H01L2224/12105—
    • H01L2224/24137—
    • H01L2224/32245—
    • H01L2224/73267—
    • H01L2224/92144—
    • H01L2224/9222—
    • H01L2924/15311—
    • H01L2924/15312—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to a power overlay (POL) packaging structure that includes an improved thermal interface.
  • POL power overlay
  • Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. Many power semiconductor devices are used in high voltage power applications and are designed to carry a large amount of current and support a large voltage. In use, high voltage power semiconductor devices are connected to an external circuit by way of a power overlay (POL) packaging and interconnect system.
  • POL power overlay
  • FIG. 1 The general structure of a prior art power overlay (POL) structure 10 is shown in FIG. 1 .
  • the standard manufacturing process for the POL structure 10 typically begins with placement of one or more power semiconductor devices 12 onto a dielectric layer 14 by way of an adhesive 16 .
  • Metal interconnects 18 e.g., copper interconnects
  • the metal interconnects 18 may be in the form of a low profile (e.g., less than 200 micrometers thick), planar interconnect structure that provides for formation of an input/output (I/O) system 20 to and from the power semiconductor devices 12 .
  • I/O input/output
  • current POL packages use solder ball grid arrays (BGAs) or land grid arrays (LGAs).
  • the use of a DBC substrate in a POL structure 10 has a number of limitations.
  • the material properties of the copper and ceramic materials of the DBC substrate place inherent limitations on the design of the DBC substrate.
  • copper sheets 28 , 30 must be kept relatively thin to avoid undue stresses placed on the ceramics caused by large swings in temperature in the copper material.
  • the surface of the lower copper layer of the DBC substrate 24 that faces semiconductor device(s) 12 is planar, the DBC substrate 24 does not facilitate fabrication of a POL package having semiconductor devices of differing height.
  • DBC substrates are relatively expensive to manufacture and are a prefabricated component.
  • the thickness of copper sheets 28 , 30 is predetermined based on the thickness of the copper foil layer applied to the ceramic substrate 26 .
  • the dielectric filler or epoxy substrate that surrounds the semiconductor devices 12 is applied using an underfill technique after the DBC substrate 24 is coupled to semiconductor devices 12 . This underfill technique is time consuming and can result in undesirable voids within the POL structure.
  • a method of forming a power overlay (POL) structure includes providing a semiconductor device, affixing a first surface of the semiconductor device to a dielectric layer, forming vias through the dielectric layer and forming a metal interconnect structure extending through the vias in the dielectric layer to electrically connect to the semiconductor device.
  • the method also includes affixing a first surface of a conductive shim to a second surface of the semiconductor device and forming a thermal interface atop a second surface of the conductive shim.
  • the method includes thermally coupling a heat sink to the conductive shim absent a direct bond copper (DBC) substrate positioned between the heat sink and the conductive shim.
  • DBC direct bond copper
  • a power overlay (POL) packaging structure includes a POL sub-module.
  • the POL sub-module includes a dielectric layer, a first semiconductor device attached to the dielectric layer, and an interconnect structure electrically coupled to a first side of the first semiconductor device.
  • the interconnect structure extends through the dielectric layer to electrically connect to at least one contact pad on the first semiconductor device.
  • a first conducting shim has a bottom surface coupled to a second side of the first semiconductor device and a thermal interface coupled to a top surface of the first conducting shim absent a direct bond copper (DBC) substrate positioned therebetween.
  • a heat sink is directly coupled to the thermal interface.
  • a semiconductor device package includes a dielectric layer having a plurality of vias formed therethrough and a semiconductor device having a first surface coupled to a top surface of the dielectric layer.
  • the semiconductor device package also includes a metal interconnect structure coupled to a bottom surface of the dielectric layer. The metal interconnect structure extends through the plurality of vias of the dielectric layer to connect to the first surface of the semiconductor device.
  • the semiconductor device package also includes a conducting shim having a bottom surface coupled to a second surface of the semiconductor device and an organic thermal interface coupled to a top surface of the conducting shim absent a direct bond copper (DBC) substrate positioned between the organic thermal interface and the conducting shim.
  • DBC direct bond copper
  • FIG. 4 is a schematic cross-sectional side view of a POL structure according to yet another embodiment of the invention.
  • FIG. 17 is a schematic cross-sectional side view of a portion of a leaded POL sub-module according to another embodiment of the invention.
  • Dielectric layer 48 may be in the form of a lamination or a film, according to various embodiments, and may be formed of one a plurality of dielectric materials, such as Kapton®, UItem®, polytetrafluoroethylene (PTFE), Upilex®, polysulfone materials (e.g., Udel®, Radel®), or another polymer film, such as a liquid crystal polymer (LCP) or a polyimide material.
  • PTFE polytetrafluoroethylene
  • Upilex® polysulfone materials
  • LCP liquid crystal polymer
  • polyimide material e.g., a polyimide material
  • a power overlay (POL) packaging structure includes a POL sub-module.
  • the POL sub-module includes a dielectric layer, a first semiconductor device attached to the dielectric layer, and an interconnect structure electrically coupled to a first side of the first semiconductor device.
  • the interconnect structure extends through the dielectric layer to electrically connect to at least one contact pad on the first semiconductor device.
  • a first conducting shim has a bottom surface coupled to a second side of the first semiconductor device and a thermal interface coupled to a top surface of the first conducting shim absent a direct bond copper (DBC) substrate positioned therebetween.
  • a heat sink is directly coupled to the thermal interface.

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
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US13/897,638 2013-03-14 2013-05-20 Power overlay structure and method of making same Active US8987876B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US13/897,638 US8987876B2 (en) 2013-03-14 2013-05-20 Power overlay structure and method of making same
TW103107092A TWI628750B (zh) 2013-03-14 2014-03-03 功率覆蓋結構及其製造方法
TW107117243A TWI703681B (zh) 2013-03-14 2014-03-03 功率覆蓋結構及其製造方法
JP2014048289A JP6595158B2 (ja) 2013-03-14 2014-03-12 パワーオーバーレイ構造およびその製造方法
KR1020140029835A KR102151047B1 (ko) 2013-03-14 2014-03-13 전력 오버레이 구조 및 그 제조 방법
CN201410094386.7A CN104051377B (zh) 2013-03-14 2014-03-14 功率覆盖结构及其制作方法
CN202010052240.1A CN111508912B (zh) 2013-03-14 2014-03-14 功率覆盖结构及其制作方法
EP14159735.1A EP2779230B1 (en) 2013-03-14 2014-03-14 Power overlay structure and method of making same
US14/665,735 US9704788B2 (en) 2013-03-14 2015-03-23 Power overlay structure and method of making same
US15/601,735 US20170263539A1 (en) 2013-03-14 2017-05-22 Power overlay structure and method of making same

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US201361784834P 2013-03-14 2013-03-14
US13/897,638 US8987876B2 (en) 2013-03-14 2013-05-20 Power overlay structure and method of making same

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US8987876B2 true US8987876B2 (en) 2015-03-24

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US14/665,735 Active US9704788B2 (en) 2013-03-14 2015-03-23 Power overlay structure and method of making same
US15/601,735 Abandoned US20170263539A1 (en) 2013-03-14 2017-05-22 Power overlay structure and method of making same

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US15/601,735 Abandoned US20170263539A1 (en) 2013-03-14 2017-05-22 Power overlay structure and method of making same

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US (3) US8987876B2 (https=)
EP (1) EP2779230B1 (https=)
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KR (1) KR102151047B1 (https=)
CN (2) CN111508912B (https=)
TW (2) TWI703681B (https=)

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US20150194375A1 (en) * 2013-03-14 2015-07-09 General Electric Company Power overlay structure and method of making same
US9953917B1 (en) 2016-12-12 2018-04-24 General Electric Company Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof
US9953913B1 (en) 2016-12-12 2018-04-24 General Electric Company Electronics package with embedded through-connect structure and method of manufacturing thereof
US9966371B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US9966361B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10224268B1 (en) * 2016-11-28 2019-03-05 CoolStar Technology, Inc. Enhanced thermal transfer in a semiconductor structure
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same
US10312194B2 (en) 2016-11-04 2019-06-04 General Electric Company Stacked electronics package and method of manufacturing thereof
US10497648B2 (en) 2018-04-03 2019-12-03 General Electric Company Embedded electronics package with multi-thickness interconnect structure and method of making same
US10589998B2 (en) 2013-11-05 2020-03-17 Neograf Solutions, Llc Graphite article
US10700035B2 (en) 2016-11-04 2020-06-30 General Electric Company Stacked electronics package and method of manufacturing thereof
US10957832B2 (en) 2018-10-22 2021-03-23 General Electric Company Electronics package for light emitting semiconductor devices and method of manufacturing thereof
US20220070996A1 (en) * 2020-08-28 2022-03-03 Ge Aviation Systems Llc Power overlay module and method of assembling
US12237243B2 (en) 2022-01-25 2025-02-25 Ge Aviation Systems Llc Power overlay module with thermal storage

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US9425114B2 (en) * 2014-03-28 2016-08-23 Oracle International Corporation Flip chip packages
US9613843B2 (en) 2014-10-13 2017-04-04 General Electric Company Power overlay structure having wirebonds and method of manufacturing same
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JP2016225413A (ja) * 2015-05-28 2016-12-28 株式会社ジェイテクト 半導体モジュール
JP6406190B2 (ja) * 2015-09-15 2018-10-17 トヨタ自動車株式会社 半導体装置
JP6418126B2 (ja) * 2015-10-09 2018-11-07 三菱電機株式会社 半導体装置
CN208159004U (zh) 2015-11-05 2018-11-27 株式会社村田制作所 部件安装基板
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JP2018049938A (ja) * 2016-09-21 2018-03-29 株式会社東芝 半導体装置
JP6724707B2 (ja) * 2016-10-11 2020-07-15 トヨタ自動車株式会社 半導体冷却装置
US20180130731A1 (en) * 2016-11-04 2018-05-10 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
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