US8937382B2 - Secondary device integration into coreless microelectronic device packages - Google Patents

Secondary device integration into coreless microelectronic device packages Download PDF

Info

Publication number
US8937382B2
US8937382B2 US13/169,162 US201113169162A US8937382B2 US 8937382 B2 US8937382 B2 US 8937382B2 US 201113169162 A US201113169162 A US 201113169162A US 8937382 B2 US8937382 B2 US 8937382B2
Authority
US
United States
Prior art keywords
microelectronic device
package
microelectronic
layer
secondary device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US13/169,162
Other languages
English (en)
Other versions
US20120326271A1 (en
Inventor
Weng Hong Teh
John S. Guzek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US13/169,162 priority Critical patent/US8937382B2/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GUZEK, JOHN S., TEH, Weng Hong
Priority to TW101119764A priority patent/TWI489917B/zh
Priority to PCT/US2012/043945 priority patent/WO2013003257A2/en
Priority to CN201280032156.7A priority patent/CN103620767B/zh
Priority to GB1321492.9A priority patent/GB2505802B/en
Priority to DE112012002654.3T priority patent/DE112012002654B4/de
Priority to JP2014517243A priority patent/JP5866441B2/ja
Priority to SG2013084900A priority patent/SG194999A1/en
Priority to DE112012007316.9T priority patent/DE112012007316B3/de
Publication of US20120326271A1 publication Critical patent/US20120326271A1/en
Priority to US14/566,198 priority patent/US9686870B2/en
Publication of US8937382B2 publication Critical patent/US8937382B2/en
Application granted granted Critical
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Definitions

  • Embodiments of the present description relate generally to the field of microelectronic device package designs and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs.
  • BBUL bumpless build-up layer
  • FIGS. 1-13 illustrate side cross-sectional views of a process of forming a bumpless build-up layer coreless (BBUL-C) microelectronic package with surface mounted device-side secondary devices, according to one embodiment of the present description.
  • BBUL-C bumpless build-up layer coreless
  • FIGS. 14-25 illustrate side cross-sectional views of a process of forming a bumpless build-up layer coreless (BBUL-C) microelectronic package with embedded device-side secondary devices, according to another embodiment of the present description.
  • BBUL-C bumpless build-up layer coreless
  • FIGS. 26-37 illustrate side cross-sectional views of a process of forming a bumpless build-up layer coreless (BBUL-C) microelectronic package with embedded device-side secondary devices, according to still another embodiment of the present description.
  • BBUL-C bumpless build-up layer coreless
  • Embodiments of the present description relate to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device, such as a capacitor, a micro electro-mechanical device (such as an accelerometer, radio frequency switches, and the like), a GPS device, a passive device, and the like, is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.
  • BBUL bumpless build-up layer
  • openings or cavity structures may be created using relatively thick dielectric materials, such as photo definable photoresist materials, wherein microelectronic devices and components may be mounted therein.
  • relatively thick dielectric material cavities may enable packaging architectures that can allow surface mounting or embedding a variety of device side secondary devices without sacrificing z-height (i.e. thickness) constraints.
  • embodiments of the present description may allow for microelectronic device back surfaces being above the device side secondary devices, such that heat sinks may directly contact the microelectronic device back surfaces, or such that additional devices (e.g. memory, logic, etc) may be attached with through silicon vias to the microelectronic device back surfaces.
  • FIGS. 1-13 illustrate cross-sectional views of an embodiment of a process of forming a bumpless build-up layer coreless (BBUL-C) microelectronic package with surface mounted device-side secondary devices.
  • a carrier 100 may be provided.
  • the carrier 100 illustrated may be a copper laminated substrate comprising an adhesion material 106 disposed between two opposing copper release layers (i.e. a first copper release layer 104 and a second copper release layer 104 ′) with a two opposing copper layers (i.e. a first copper layer 102 and a second copper layer 102 ′) abutting their respective copper release layers (i.e.
  • the adhesion material 106 may be any appropriate material, including but not limited to an epoxy material. It is understood that although the layers laminated with the adhesion material 106 are specifically identified as copper layers (i.e. the copper layers and the copper release layers), the present description is not so limited, as the layers may be made of any appropriate material.
  • a first sacrificial material layer 110 such as a photoresist material
  • a second sacrificial material layer 110 ′ such as a photoresist material
  • a first protective layer 120 such as a metal foil (for example, copper foil)
  • a second protective layer 120 ′ such as a metal foil (for example, copper foil)
  • a metal foil for example, copper foil
  • the first sacrificial material layer 110 and the second sacrificial material layer 110 ′ may be formed by any technique known in the art, including but not limited to spin coating, dry photofilm lamination, and chemical vapor deposition.
  • the first protective layer 120 and the second protective layer 120 ′ may be formed by any technique known in the art, including but not limited to deposition and foil lamination.
  • the first and second sacrificial material layer 110 and the second sacrificial material layer 110 ′ may be deposited to thickness of between about 300 ⁇ m and 600 ⁇ m.
  • secondary device pads may be formed on the protective layers.
  • a first secondary device pad 124 a and a second secondary device pad 124 b may be formed on the first protective layer 120
  • a third secondary device pad 124 a ′ and a fourth secondary device pad 124 b ′ may be formed on the second protective layer 120 ′.
  • Metallization layers i.e. elements 122 a , 122 b , 122 a ′, and 122 b ′ may be disposed between their respective protective layers (i.e. elements 120 and 120 ′) and their respective secondary device pads (e.g. elements 124 a , 124 b , 124 a ′, and 124 b ′).
  • PoP package-on-package
  • first package-on-package pad 128 a and a second package-on-package pad 128 b may also be formed on the first protective layer 120
  • a third package-on-package pad 128 a ′ and a fourth package-on-package pad 128 b ′ may be formed on the second protective layer 120 ′.
  • Metallization layers i.e. elements 126 a , 126 b , 126 a ′, and 126 b ′ may also be disposed between their respective protective layers (e.g. elements 120 and 120 ′) and their respective package-on-package pad (e.g. elements 128 a , 128 b , 128 a ′, and 128 b ′).
  • the package-on-package pads may be used to form connections between microelectronic device packages in the z-direction for stacking (e.g. referred to as 3D stacking), without the need for through silicon vias.
  • the secondary device pads and the package-on-package pads may be formed by any technique known in the art, including deposition, photolithography, and etching.
  • an opening 132 may be formed through the first protective layer 120 to expose a portion of the first sacrificial material layer 110 , and an opening 132 ′ may be formed simultaneously in second protective layer 120 ′ to expose a portion of the second sacrificial material layer 110 ′.
  • the first protective layer opening 132 and the second protective layer opening 132 ′ may be formed by any technique known in the art, including but not limited to photolithographic patterning and etching. It is understood that the first sacrificial material layer 110 and the second sacrificial material layer 110 ′ may act as an etch stop during the formation of the first protective layer opening 132 and the second protective layer opening 132 ′.
  • an opening 134 may be formed, using the first protective layer 120 as a mask, through the first sacrificial material layer 110 to expose a portion of the carrier first surface 108 .
  • An opening 134 ′ may be formed simultaneously, using the second protective layer as a mask, through the second sacrificial material layer 110 ′ to expose a portion of the carrier second surface 108 ′.
  • the first sacrificial material layer opening 134 and the second sacrificial material layer opening 134 ′ may be formed by any technique known in the art, including but not limited to photolithographic processes and wet or dry etching, wherein the first copper layer 102 and the second copper layer 102 ′ may act as etch stops.
  • a first microelectronic device 142 may be attached by a back surface 150 thereof with an adhesive material 144 to the carrier first surface 108 within the first sacrificial material layer opening 134 .
  • the first microelectronic device 142 may have at least one contact land (shown as elements 146 a and 146 b ) on an active surface 148 thereof.
  • a second microelectronic device 142 ′ may be attached by a back surface 150 ′ with an adhesive material 144 ′ to the carrier second surface 108 ′ within the second sacrificial material layer opening 134 ′.
  • the second microelectronic device 142 ′ may have at least one contact land (shown as elements 146 a ′ and 146 b ′) on an active surface 148 ′ thereof.
  • the first microelectronic device 142 and the second microelectronic device 142 ′ may be any desired device, including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, an application specific integrated circuit, or the like.
  • the adhesive material 144 and 144 ′ may be any appropriate material, including but not limited to a die backside film.
  • a first dielectric layer 152 may be formed on the first microelectronic device 142 , the first protective layer 120 , the first package-on-package pads 128 a , the second package-on-package 128 b , the first secondary device pad 124 a , and the second secondary device pad 124 b .
  • a second dielectric layer 152 ′ may be simultaneously formed on the second microelectronic device 142 ′, the second protective layer 120 ′, the third package-on-package pad 128 a ′, the fourth package-on-package pad 128 b ′, the third secondary device pad 124 a ′, and the fourth secondary device pad 124 b ′.
  • FIG. 8 a first dielectric layer 152 may be formed on the first microelectronic device 142 , the first protective layer 120 , the first package-on-package pads 128 a , the second package-on-package 128 b , the first secondary device pad 124 a , and
  • a plurality of openings 154 may be formed in the first dielectric layer 152 to expose at least a portion of each opening's 154 respective the first microelectronic device contact lands 146 a and 146 b , the first package-on-package pads 128 a , the second package-on-package pads 128 b , the first secondary device pads 124 a , and the second secondary device pads 124 b .
  • a plurality of openings 154 ′ may also be simultaneously formed in the second dielectric layer 152 ′ to expose at least a portion of each opening's 154 ′ respective the second microelectronic device contact lands 146 a ′ and 146 b ′, the third package-on-package pads 128 a ′, the fourth package-on-package pads 128 b ′, the third secondary device pads 124 a ′, and the fourth secondary device pads 124 b ′.
  • the first dielectric layer 152 and the second dielectric layer 152 ′ may comprise silica-filled epoxy, such as build-up films available from Ajinomoto Fine-Techno Co., Inc., 1-2 Suzuki-cho, Kawasaki-ku, Kawasaki-shi, 210-0801, Japan (e.g. Ajinomoto ABF-GX13, Ajinomoto GX92, and the like).
  • the openings 154 and 154 ′ may be formed by any technique known in the art including but not limited to laser or ion drilling, etching, and the like.
  • a conductive material such as copper, aluminum, silver, gold, and alloys thereof, may be disposed within the openings 154 , by any technique known in the art, to form a first microelectronic device contact land first conductive via 166 a , a first microelectronic device contact land second conductive via 166 b , a first package-on-package pad conductive via 162 a , a second package-on-package pad conductive via 162 b , a first secondary device pad conductive via 164 a , and a second secondary device pad conductive via 164 b .
  • the conductive material may also be simultaneously disposed within the openings 154 ′ to form a second microelectronic device contact land first conductive via 166 a ′, a second microelectronic device contact land second conductive via 166 b ′, a third package-on-package pad conductive via 162 a ′, a fourth package-on-package pad conductive via 162 b ′, a third secondary device pad conductive via 164 a ′, and a fourth secondary device pad conductive via 164 b ′.
  • conductive traces may be formed to electrically connect various conductive vias.
  • a first conductive trace 168 a may be formed to electrically connect the first secondary device pad conductive via 164 a and the first microelectronic device contact land first conductive via 166 a and a second conductive trace 168 b may be formed to electrically connect the second secondary device pad conductive via 164 b and the first microelectronic device contact land second conductive via 166 b .
  • a third conductive trace 168 a ′ may be formed to electrically connect the third secondary device pad conductive via 164 a ′ and the second microelectronic device contact land first conductive via 166 a ′ and a fourth conductive trace 168 b ′ may be formed to electrically connect the fourth secondary device pad conductive via 164 b ′ and the second microelectronic device contact land second conductive via 166 b ′.
  • the conductive traces (e.g. elements 168 a , 168 b , 168 a ′, and 168 b ′) may be any appropriate conductive material, including but not limited to copper, aluminum, silver, gold, and alloys thereof.
  • first exterior layer 172 may be formed on the first dielectric layer 152 and a second exterior layer 172 ′ may be formed on the second dielectric layer 152 ′.
  • the exterior layers i.e. first exterior layer 172 and second exterior layer 172 ′ may be used to engineer inherent warpages/stresses in microelectronic packages, as will be understood to those skilled in the art.
  • FIG. 10 illustrates the structure formed on the carrier first surface 108 after depaneling.
  • the first sacrificial material layer 110 may be removed, such as by plasma ashing or solvent release, as will be understood to those skilled in the art.
  • the protective layer 120 may also be removed by any appropriate technique known in the art, as also shown in FIG. 11 .
  • the adhesive layer 144 may be removed from the first microelectronic device 142 , such as by plasma ashing or a dissolution chemical, as shown in FIG. 12 , to form a microelectronic device package 180 . It is understood that if plasma ashing is used to remove the first sacrificial material layer 110 , the adhesive layer 144 may also be removed in a single plasma ashing step.
  • At least one secondary device may then be attached to a secondary device pad.
  • a first secondary device 174 a may be attached to the first secondary device pad 124 a with the metallization layer 122 a
  • a second secondary device 174 b may be attached to the second secondary device pad 124 b with the metallization layer 122 b .
  • the process of FIGS. 1-13 may result in a secondary device (e.g. elements 174 a and 174 b ) which is disposed within a thickness T of the first microelectronic device 142 (i.e. between the first microelectronic device active surface 148 and the first microelectronic device back surface 150 ).
  • FIGS. 14-25 illustrate cross-sectional views of another embodiment of a process of forming a bumpless build-up layer coreless (BBUL-C) microelectronic package with embedded device side secondary devices.
  • a carrier such as the carrier 100 of FIG. 1
  • at least one stand-off may be formed on the carrier.
  • a first stand-off 202 a and a second stand-off 202 b may be formed on the carrier first surface 108
  • a third stand-off 202 a ′, and a fourth stand-off 202 b ′ may be formed on the carrier second surface 108 ′.
  • the stand-offs e.g. elements 202 a , 202 b , 202 a ′, and 202 b ′
  • a first sacrificial material layer 210 such as a photoresist material
  • a second sacrificial material layer 210 ′ such as a photoresist material
  • a first protective layer 220 may be formed on the first sacrificial material layer 210
  • a second protective layer 220 ′ such as a metal foil may be formed on the second sacrificial material layer 210 ′, as shown in FIG.
  • the first sacrificial material layer 210 and the second sacrificial material layer 210 ′ may be formed by any technique known in the art, including but not limited to spin coating, dry photofilm lamination, and chemical vapor deposition.
  • the first protective layer 220 and the second protective layer 220 ′ may be formed by any technique known in the art, including but not limited to deposition and foil lamination.
  • the first sacrificial material layer 210 and the second sacrificial material layer 210 ′ may be deposited to thickness of between about 300 ⁇ m and 600 ⁇ m.
  • an opening 232 may be formed through the first protective layer 220 to expose a portion of the first sacrificial material layer 210
  • an opening 232 ′ may be formed simultaneously in second protective layer 220 ′ to expose a portion of the second sacrificial material layer 210 ′.
  • the first protective layer opening 232 and the second protective layer opening 232 ′ may be formed by any technique known in the art, including but not limited to photolithographic patterning and etching. It is understood that the first sacrificial material layer 210 and the second sacrificial material layer 210 ′ may act as an etch stop during the formation of the first protective layer opening 232 and the second protective layer opening 232 ′.
  • an opening 234 may be formed, using the first protective layer 220 as a mask, through the first sacrificial material layer 210 to expose the first stand-off 202 a , the second stand-off 202 b , and a portion of the carrier first surface 108 .
  • An opening 234 ′ may be formed simultaneously, using the second protective layer as a mask, through the second sacrificial material layer 210 ′ to expose the third stand-off 202 a ′, the fourth stand-off 202 b ′, and a portion of the carrier second surface 108 ′.
  • the first sacrificial material layer opening 234 and the second sacrificial material layer opening 234 ′ may be formed by any technique known in the art, including but not limited to photolithography, wherein the first copper layer 102 and the second copper layer 102 ′ may act as etch stops.
  • package-on-package (PoP) pads may be formed on the protective layers (e.g. elements 220 and 220 ′).
  • FIG. 19 illustrates a first package-on-package pad 228 a and a second package-on-package pad 228 b formed on the first protective layer 220 , and a third package-on-package pad 228 a ′ and a fourth package-on-package pad 228 b ′ formed on the second protective layer 220 ′.
  • Metallization layers i.e. elements 226 a , 226 b , 226 a ′, and 226 b ′ may be disposed between their respective protective layers (e.g.
  • the package-on-package pads may be used to form connections between microelectronic device packages in the z-direction for stacking (e.g. referred to as 3D stacking), without the need for through silicon vias.
  • the package-on-package pads may be formed by any technique known in the art, including deposition, photolithographic patterning, and etching.
  • a first microelectronic device 242 may be attached by a back surface 250 thereof with an adhesive material 244 to the carrier first surface 108 within the first sacrificial material layer opening 234 .
  • the first microelectronic device 242 may have at least one contact land (shown as elements 246 a and 246 b ) on an active surface 248 thereof.
  • a second microelectronic device 242 ′ may be attached by a back surface 250 ′ with an adhesive material 244 ′ to the carrier second surface 108 ′ within the second sacrificial material layer opening 234 ′.
  • the second microelectronic device 242 ′ may have at least one contact land (shown as elements 246 a ′ and 246 b ′) on an active surface 248 ′ thereof.
  • the first microelectronic device 242 and the second microelectronic device 242 ′ may be any desired device, including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, an application specific integrated circuit, or the like.
  • the adhesive material 244 and 244 ′ may be any appropriate material, including but not limited to a die backside film.
  • At least one secondary device may then be attached to a respective stand-off.
  • a first secondary device 274 a may be attached to the first stand-off 202 a with an adhesive material 276 a
  • a second secondary device 274 b may be attached to the second stand-off 202 b with an adhesive material 276 b
  • a third secondary device 274 a ′ may be attached to the third stand-off 202 a ′ with an adhesive material 276 a ′
  • a fourth secondary device 274 b ′ may be attached to the fourth stand-off 202 b ′ with an adhesive material 276 b′.
  • a first dielectric layer 252 may be formed on the first microelectronic device 242 , the first protective layer 220 , the first package-on-package pads 228 a , the second package-on-package pads 228 b , the first secondary device 274 a , and the second secondary device 274 b .
  • a second dielectric layer 252 ′ may be simultaneously formed on the second microelectronic device 242 ′, the second protective layer 220 ′, the third package-on-package pad 228 a ′, the fourth package-on-package pad 228 b ′, the third secondary device 274 a ′, and the fourth secondary device 274 b ′.
  • FIG. 22 a first dielectric layer 252 may be formed on the first microelectronic device 242 , the first protective layer 220 , the first package-on-package pads 228 a , the second package-on-package pads 228 b , the first secondary device 274 a , and
  • a plurality of openings 254 may be formed in the first dielectric layer 252 to expose at least a portion of each opening's 254 respective the first microelectronic device contact lands 246 a and 246 b , the first package-on-package pad 228 a , the second package-on-package pad 228 b , the first secondary device 274 a , and the second secondary device 274 b .
  • a plurality of openings 254 ′ may be simultaneously formed in the second dielectric layer 252 ′ to expose at least a portion of each opening's 254 ′ respective the second microelectronic device contact lands 246 a ′ and 246 b ′, the third package-on-package pad 228 a ′, the fourth package-on-package pad 228 b ′, the third secondary device 274 a ′, and the fourth secondary device 274 b ′.
  • the first dielectric layer 252 and the second dielectric layer 252 ′ may comprise silica-filled epoxy.
  • the openings 254 and 254 ′ may be formed by any technique known in the art including but not limited to laser drilling, ion drilling, etching, and the like.
  • a conductive material may be disposed within the first dielectric layer openings 254 (see FIG. 22 ), by any technique known in the art, to form a first microelectronic device contact land first conductive via 266 a , a first microelectronic device contact land second conductive via 266 b , a first package-on-package pad conductive via 262 a , a second package-on-package pad conductive via 262 b , a first secondary device first conductive via 264 1 a , a first secondary device second conductive via 264 2 a , a second secondary device first conductive via 264 1 b , and a second secondary device second conductive via 264 2 b .
  • the conductive material may also be simultaneously disposed within the second dielectric layer openings 254 ′ to form a second microelectronic device contact land first conductive via 266 a ′, a second microelectronic device contact land second conductive via 266 b ′, a third package-on-package pad conductive via 262 a ′, a fourth package-on-package pad conductive via 262 b ′, a third secondary device first conductive via 264 1 a ′, a third secondary device second conductive via 264 2 a ′, a fourth secondary device first conductive via 264 1 b ′, and a fourth secondary device second conductive via 264 2 b ′.
  • a second microelectronic device contact land first conductive via 266 a ′ As further shown in FIG.
  • conductive traces may be formed to electrically connect various conductive vias.
  • a first conductive trace 268 a may be formed to electrically connect at least one of the first secondary device first conductive via 264 1 a and the first secondary device second conductive via 264 2 a , and the first microelectronic device contact land first conductive via 266 a .
  • a second conductive trace 268 b may be formed to electrically connect at least one of the second secondary device first conductive via 264 1 b and the second secondary device second conductive via 264 2 b , and the first microelectronic device contact land second conductive via 266 b .
  • a third conductive trace 268 a ′ may be formed to electrically connect at least one of the third secondary device first conductive via 264 1 a ′ and the third secondary device second conductive via 264 2 a ′, and the second microelectronic device contact land first conductive via 266 a ′.
  • a fourth conductive trace 268 b ′ may be formed to electrically connect at least one of the fourth secondary device first conductive via 264 1 b ′ and the fourth secondary device second conductive via 264 2 b ′, and the second microelectronic device contact land second conductive via 266 b ′.
  • the conductive traces (e.g. elements 268 a , 268 b , 268 a ′, and 268 b ′) may be any appropriate conductive material.
  • first exterior layer 272 may be formed on the first dielectric layer 252 and a second exterior layer 272 ′ may be formed on the second dielectric layer 252 ′.
  • the exterior layers i.e. first exterior layer 272 and second exterior layer 272 ′ may be used to engineer inherent warpages/stresses in microelectronic packages, as will be understood to those skilled in the art.
  • FIG. 24 illustrates the structure formed on the carrier first surface 108 after depaneling, wherein the stand-offs 202 a and 202 b (see FIG. 23 ) may be removed by any appropriate technique known in the art. It is understood that if the stand-offs 202 a and 202 b are copper as is the carrier layers, the stand-offs 202 a and 202 b may be removed during the depaneling process. As shown in the FIG. 25 , the first sacrificial material layer 210 (see FIG.
  • first microelectronic device adhesive layer 244 and the secondary device adhesive layers 276 a and 276 b may also be removed from the first microelectronic device 242 , such as by plasma ashing or a dissolution chemical, as also shown in FIG. 25 , to form a microelectronic device package 280 . It is understood that if plasma ashing is used to remove the first sacrificial material layer 210 , the first microelectronic device adhesive layer 244 may also be removed in a single step.
  • the process of FIGS. 14-25 may result in a secondary device (e.g. elements 274 a and 274 b ) which is disposed within a thickness T of the first microelectronic device 242 (i.e. between the first microelectronic device active surface 148 and the first microelectronic device back surface 250 ).
  • a secondary device e.g. elements 274 a and 274 b
  • the secondary devices i.e. elements 274 a , 274 b , 274 a ′, and 274 b ′ (see FIG. 21 )
  • the same opening i.e. elements 234 , 234 ′ (see FIG. 18 )
  • the microelectronic devices 244 and 244 ′ see FIG. 21 )
  • Unique openings can be created for the secondary devices and the microelectronic devices separately to allow optimization, such as minimal build-up layer thickness variability or warpage engineering, as will be understood to those skilled in the art.
  • FIGS. 26-38 illustrate cross-sectional views of another embodiment of a process of forming a bumpless build-up layer coreless (BBUL-C) microelectronic package with embedded device-side secondary devices.
  • a carrier such as the carrier 100 of FIG. 1 , may be provided, wherein a first stand-off material layer 302 may be deposited over the carrier first surface 108 and a second stand-off material layer 302 ′ may be simultaneously deposited over the carrier second surface 108 ′.
  • the first stand-off material layer 302 and the second stand-off material layer 302 ′ may be formed of any appropriate material, including but not limited to a photoresist material, and formed by any technique known in the art, including but not limited to spin coating, dry photofilm lamination, and chemical vapor deposition. In one embodiment, the first stand-off material layer 302 and the second stand-off material layer 302 ′ may be deposited to thickness of between about 30 ⁇ m and 100 ⁇ m.
  • an opening 304 may be formed through the first stand-off material layer 302 to expose a portion of the carrier first surface 108
  • an opening 304 ′ may be formed simultaneously in second stand-off material layer 302 ′ to expose a portion of the carrier second surface 108 ′.
  • the first stand-off material layer opening 304 and the second stand-off material layer opening 304 ′ may be formed by any technique known in the art, including but not limited to photolithographic patterning and developing.
  • the photoresist material when a photoresist material is used to form the first stand-off material layer 302 and the second stand-off material layer 302 ′, the photoresist material may be flood exposed (e.g. crosslinked) by exposure to radiation (e.g. light), which is shown as arrows 306 and 306 ′, respectively.
  • a first sacrificial material layer 310 such as a photoresist material, may be formed over the first stand-off material layer 302 and in the first stand-off material layer opening 304 (see FIG.
  • a second sacrificial material layer 310 ′ such as a photoresist material, may be formed over the second stand-off material layer 302 ′ and in the second stand-off material layer opening 304 ′ (see FIG. 27 ).
  • the first sacrificial material layer 310 and the second sacrificial material layer 310 ′ may be formed by any technique known in the art, including but not limited to spin coating, dry photofilm lamination, and chemical vapor deposition. In one embodiment, the first sacrificial material layer 310 and the second sacrificial material layer 310 ′ may be deposited to thickness of between about 300 ⁇ m and 600 ⁇ m.
  • an opening 332 may be formed through the first sacrificial material layer 310 to expose a portion of the first stand-off material layer 310 and a portion of the carrier first surface 108
  • an opening 332 ′ may be formed simultaneously in the second sacrificial material layer 310 ′ to expose a portion of the second sacrificial material layer 310 ′ and a portion of the carrier second surface 108 ′.
  • the first sacrificial material layer opening 332 and the second sacrificial material layer opening 332 ′ may be formed by any technique known in the art, including but not limited to photolithographic patterning and developing.
  • first stand-off material layer 302 and second stand-off material layer 302 ′ may result in the first stand-off material layer 302 and second stand-off material layer 302 ′ being substantially unaffected during the formation of the first sacrificial material layer opening 332 and the second sacrificial material layer opening 332 ′.
  • a first microelectronic device 342 may be attached by a back surface 350 thereof with an adhesive material 344 to the carrier first surface 108 within the first sacrificial material layer opening 332 .
  • the first microelectronic device 342 may have at least one contact land (shown as elements 346 a and 346 b ) on an active surface 348 thereof.
  • a second microelectronic device 342 ′ may be attached by a back surface 350 ′ with an adhesive material 344 ′ to the carrier second surface 108 ′ within the second sacrificial material layer opening 332 ′.
  • the second microelectronic device 342 ′ may have at least one contact land (shown as elements 346 a ′ and 346 b ′) on an active surface 348 ′ thereof.
  • the microelectronic devices may be any desired devices, including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, an application specific integrated circuit, or the like.
  • At least one secondary device may then be attached to a respective stand-off material.
  • a first secondary device 374 a may be attached to the first stand-off material layer 302 with an adhesive material 376 a
  • a second secondary device 374 b may be attached to the first stand-off material layer 302 with an adhesive material 376 b
  • a third secondary device 374 a ′ may be attached to the second stand-off material layer 302 ′ with an adhesive material 376 a ′
  • a fourth secondary device 374 b ′ may be attached to the second stand-off material layer 302 b ′ with an adhesive material 376 b′.
  • a first dielectric layer 352 may be formed on the first microelectronic device 342 , the first secondary device 374 a , and the second secondary device 374 b .
  • a second dielectric layer 352 ′ may be simultaneously formed on the second microelectronic device 342 ′, the third secondary device 374 a ′, and the fourth secondary device 374 b .
  • a plurality of openings 354 may be formed in the first dielectric layer 352 to expose at least a portion of each opening's 354 respective the microelectronic device contact lands 346 a and 346 b , the first secondary device 374 a , and the second secondary device 374 b .
  • a plurality of openings 354 ′ may be formed in the second dielectric layer 352 ′ to expose at least a portion of each opening's 354 ′ respective microelectronic device contact lands 346 a ′ and 346 b ′, third secondary device 374 a ′, or fourth secondary device 374 b ′.
  • the first dielectric layer 352 and the second dielectric layer 352 ′ may comprise silica-filled epoxy.
  • the openings 354 and 354 ′ may be formed by any technique known in the art including but not limited to laser drilling, ion drilling, etching, and the like.
  • a conductive material may be disposed within the first dielectric material layer openings 354 (see FIG. 32 ), by any technique known in the art, to form a first microelectronic device contact land first conductive via 366 a , a first microelectronic device contact land second conductive via 366 b , a first secondary device first conductive via 364 1 a , a first secondary device second conductive via 364 2 a , a second secondary device first conductive via 364 1 b and a second secondary device second conductive via 364 2 b .
  • the conductive material may also be simultaneously disposed within the second dielectric material layer openings 354 ′ (see FIG.
  • conductive traces may be formed to electrically connect various conductive vias.
  • a first conductive trace 368 a may be formed to electrically connect at least one of the first secondary device first conductive via 364 1 a and the first secondary device second conductive via 364 2 a , and the first microelectronic device contact land first conductive via 366 a .
  • a second conductive trace 368 b may be formed to electrically connect at least one of the second secondary device first conductive via 364 1 b and the second secondary device second conductive via 364 2 b , and the first microelectronic device contact land second conductive via 366 b .
  • a third conductive trace 368 a ′ may be formed to electrically connect at least one of the third secondary device first conductive via 364 1 a ′ and the third secondary device second conductive via 364 2 a ′, and the second microelectronic device contact land first conductive via 366 a ′.
  • a fourth conductive trace 368 b ′ may be formed to electrically connect at least one of the fourth secondary device first conductive via 364 1 b ′ and the fourth secondary device second conductive via 364 2 b ′, and the second microelectronic device contact land second conductive via 366 b ′.
  • the conductive traces (e.g. elements 368 a , 368 b , 368 a ′, and 368 b ′) may be any appropriate conductive material.
  • first exterior layer 372 may be formed on the first dielectric layer 352 and a second exterior layer 372 ′ may be formed on the second dielectric layer 352 ′.
  • the exterior layers i.e. first exterior layer 372 and second exterior layer 372 ′ may be used to engineer inherent warpages/stresses in microelectronic packages, as will be understood to those skilled in the art.
  • FIG. 34 illustrates the structure formed on the carrier first surface 108 after depaneling.
  • the first stand-off material layer 302 and the first sacrificial material layer 310 may be removed, such as by a solvent release.
  • the first microelectronic device adhesive material layer 344 , the first secondary device adhesive material 376 a , and the second secondary device adhesive material 376 b may then be removed, such as by plasma ashing, as shown in FIG. 36 , to form a microelectronic device package 380 .
  • a controlled plasma ashing could be used to simultaneously remove the first stand-off material layer 302 , the first sacrificial material layer 310 , the first microelectronic device adhesive material layer 344 , the first secondary device adhesive material 376 a , and the second secondary device adhesive material 376 b . It is further understood that a controlled plasma ashing could be used to remove the first stand-off material layer 302 , the first microelectronic device adhesive material layer 344 , the first secondary device adhesive material 376 a , and the second secondary device adhesive material 376 b , while leaving the first sacrificial material layer 310 in place, as shown in FIG. 37 , to form a microelectronic device package 390 .
  • the process of FIGS. 26-37 may result in a secondary device (e.g. elements 374 a and 374 b ) which is disposed within a thickness T of the first microelectronic device 342 (i.e. between the first microelectronic device active surface 348 and the first microelectronic device back surface 350 ).
  • a secondary device e.g. elements 374 a and 374 b
  • FIGS. 28-37 show in stand-off layer being formed for a microelectronic device package, it is understood that multiple stand-off material layers could be formed and various pockets or cavities could be formed within the materials to allow for the creation of various package architectures for microelectronic device and package stacking and also multi-device embedding, as will be understood to those skilled in the art.
  • the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGS. 1-37 .
  • the subject matter may be applied to other microelectronic device packaging applications.
  • the subject matter may also be used in any appropriate application outside of the microelectronic device fabrication field.
  • the subject matter of the present description may be a part of a larger bumpless build-up package, it may include multiple stacked microelectronic dice, it may be formed at a wafer level, or any number of appropriate variations, as will be understood to those skilled in the art.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Micromachines (AREA)
US13/169,162 2011-06-27 2011-06-27 Secondary device integration into coreless microelectronic device packages Active 2033-04-21 US8937382B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US13/169,162 US8937382B2 (en) 2011-06-27 2011-06-27 Secondary device integration into coreless microelectronic device packages
TW101119764A TWI489917B (zh) 2011-06-27 2012-06-01 將二次裝置整合入無芯微電子裝置封裝組件中之技術
JP2014517243A JP5866441B2 (ja) 2011-06-27 2012-06-25 コアレスマイクロエレクトロニクスデバイスパッケージへの第２デバイスの集積
CN201280032156.7A CN103620767B (zh) 2011-06-27 2012-06-25 微电子器件封装及其形成方法
GB1321492.9A GB2505802B (en) 2011-06-27 2012-06-25 Secondary device integration into coreless microelectronic device packages
DE112012002654.3T DE112012002654B4 (de) 2011-06-27 2012-06-25 Integration sekundärer Bauelemente in kernlose mikroelektronische Bauelement-Packages
PCT/US2012/043945 WO2013003257A2 (en) 2011-06-27 2012-06-25 Secondary device integration into coreless microelectronic device packages
SG2013084900A SG194999A1 (en) 2011-06-27 2012-06-25 Secondary device integration into coreless microelectronic device packages
DE112012007316.9T DE112012007316B3 (de) 2011-06-27 2012-06-25 Integration sekundärer bauelemente in kernlose mikroelektronische bauelement-packages
US14/566,198 US9686870B2 (en) 2011-06-27 2014-12-10 Method of forming a microelectronic device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/169,162 US8937382B2 (en) 2011-06-27 2011-06-27 Secondary device integration into coreless microelectronic device packages

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/566,198 Division US9686870B2 (en) 2011-06-27 2014-12-10 Method of forming a microelectronic device package

Publications (2)

Publication Number Publication Date
US20120326271A1 US20120326271A1 (en) 2012-12-27
US8937382B2 true US8937382B2 (en) 2015-01-20

Family

ID=47361070

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/169,162 Active 2033-04-21 US8937382B2 (en) 2011-06-27 2011-06-27 Secondary device integration into coreless microelectronic device packages
US14/566,198 Active 2032-03-07 US9686870B2 (en) 2011-06-27 2014-12-10 Method of forming a microelectronic device package

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/566,198 Active 2032-03-07 US9686870B2 (en) 2011-06-27 2014-12-10 Method of forming a microelectronic device package

Country Status (8)

Country Link
US (2) US8937382B2 (de)
JP (1) JP5866441B2 (de)
CN (1) CN103620767B (de)
DE (2) DE112012002654B4 (de)
GB (1) GB2505802B (de)
SG (1) SG194999A1 (de)
TW (1) TWI489917B (de)
WO (1) WO2013003257A2 (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140177193A1 (en) * 2012-12-21 2014-06-26 Liwen Jin Bumpless build-up layer package including a release layer
US9295158B2 (en) * 2013-11-05 2016-03-22 Sunasic Technologies, Inc. Method of manufacturing printed circuit board having electronic component embedded
US9646851B2 (en) 2010-04-02 2017-05-09 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US9686870B2 (en) 2011-06-27 2017-06-20 Intel Corporation Method of forming a microelectronic device package
US11670613B2 (en) * 2019-12-31 2023-06-06 At&S (China) Co. Ltd. Arrangement with central carrier and two opposing layer stacks, component carrier and manufacturing method

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101043484B1 (ko) * 2006-06-29 2011-06-23 인텔 코포레이션 집적 회로 패키지를 포함하는 장치, 시스템 및 집적 회로 패키지의 제조 방법
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
KR101632249B1 (ko) 2011-10-31 2016-07-01 인텔 코포레이션 멀티 다이 패키지 구조들
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
DE112012006469B4 (de) 2012-06-08 2022-05-05 Intel Corporation Mikroelektronisches Gehäuse mit nicht komplanaren gekapselten mikroelektronischen Bauelementen und einer Aufbauschicht ohne Kontaktierhügel
US8866287B2 (en) 2012-09-29 2014-10-21 Intel Corporation Embedded structures for package-on-package architecture
US9666202B2 (en) 2013-09-10 2017-05-30 Huawei Technologies Co., Ltd. Adaptive bandwidth extension and apparatus for the same
US10206288B2 (en) * 2015-08-13 2019-02-12 Palo Alto Research Center Incorporated Bare die integration with printed components on flexible substrate
US10165677B2 (en) 2015-12-10 2018-12-25 Palo Alto Research Center Incorporated Bare die integration with printed components on flexible substrate without laser cut
TWI590407B (zh) * 2015-12-11 2017-07-01 南茂科技股份有限公司 半導體封裝結構及其製作方法
US9978698B1 (en) * 2017-01-25 2018-05-22 Raytheon Company Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members
US10847384B2 (en) 2017-05-31 2020-11-24 Palo Alto Research Center Incorporated Method and fixture for chip attachment to physical objects
US10410940B2 (en) * 2017-06-30 2019-09-10 Intel Corporation Semiconductor package with cavity

Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5510649A (en) 1992-05-18 1996-04-23 Motorola, Inc. Ceramic semiconductor package having varying conductive bonds
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6239482B1 (en) 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US20010015492A1 (en) 1996-05-24 2001-08-23 Salman Akram Packaged die on pcb with heat sink encapsulant
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US20020088116A1 (en) 2000-09-19 2002-07-11 International Business Machines Corporation Method of making a CTE compensated chip interposer
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6426545B1 (en) 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US20020145204A1 (en) * 2001-04-06 2002-10-10 Hitachi, Ltd. Semiconductor device
US6472762B1 (en) 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US6507122B2 (en) 1999-08-09 2003-01-14 International Business Machines Corporation Pre-bond encapsulation of area array terminated chip and wafer scale packages
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6555908B1 (en) 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6580611B1 (en) 2001-12-21 2003-06-17 Intel Corporation Dual-sided heat removal system
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6586276B2 (en) 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US6617682B1 (en) 2000-09-28 2003-09-09 Intel Corporation Structure for reducing die corner and edge stresses in microelectronic packages
US6703400B2 (en) 2001-02-23 2004-03-09 Schering Corporation Methods for treating multidrug resistance
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7078788B2 (en) 2000-08-16 2006-07-18 Intel Corporation Microelectronic substrates with integrated devices
US20060186536A1 (en) 2005-02-02 2006-08-24 Shih-Ping Hsu Substrate assembly with direct electrical connection as a semiconductor package
US7109055B2 (en) 2005-01-20 2006-09-19 Freescale Semiconductor, Inc. Methods and apparatus having wafer level chip scale package for sensing elements
US7144756B1 (en) 2003-11-20 2006-12-05 Altera Corporation Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate
US7160755B2 (en) 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US20080128916A1 (en) 2006-12-04 2008-06-05 Nec Electronics Corporation Semiconductor device including microstrip line and coplanar line
US7425464B2 (en) 2006-03-10 2008-09-16 Freescale Semiconductor, Inc. Semiconductor device packaging
US7442581B2 (en) 2004-12-10 2008-10-28 Freescale Semiconductor, Inc. Flexible carrier and release method for high volume electronic package fabrication
US7459782B1 (en) 2005-10-05 2008-12-02 Altera Corporation Stiffener for flip chip BGA package
US20080308917A1 (en) * 2007-06-13 2008-12-18 Infineon Technologies Ag Embedded chip package
US20080315398A1 (en) 2007-06-22 2008-12-25 Hsing-Lun Lo Packaging substrate with embedded chip and buried heatsink
US20080315377A1 (en) 2007-06-25 2008-12-25 Epic Technologies, Inc. Packaged electronic modules and fabrication methods thereof implementing a cell phone or other electronic system
US7476563B2 (en) 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US20090079064A1 (en) 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
US20090121347A1 (en) 2005-06-29 2009-05-14 Rohm Co., Ltd. Semiconductor Device and Semiconductor Device Assembly
US20090152743A1 (en) 2007-12-15 2009-06-18 Houssam Jomaa Routing layer for a microelectronic device, microelectronic package containing same, and method of forming a multi-thickness conductor in same for a microelectronic device
US20090212416A1 (en) 2008-02-22 2009-08-27 Skeete Oswald L Integrated circuit package and method of manufacturing same
US7588951B2 (en) 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
US20090236031A1 (en) 2008-03-24 2009-09-24 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring substrate and method of manufacturing semiconductor device
US7595226B2 (en) 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US7632715B2 (en) 2007-01-05 2009-12-15 Freescale Semiconductor, Inc. Method of packaging semiconductor devices
US7633143B1 (en) * 2008-09-22 2009-12-15 Powertech Technology Inc. Semiconductor package having plural chips side by side arranged on a leadframe
US7648858B2 (en) 2007-06-19 2010-01-19 Freescale Semiconductor, Inc. Methods and apparatus for EMI shielding in multi-chip modules
US20100013101A1 (en) 2008-07-18 2010-01-21 Harry Hedler Method for Manufacturing a Multichip Module Assembly
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US7659143B2 (en) 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US20100073894A1 (en) 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
KR20100038232A (ko) 2007-08-24 2010-04-13 가시오게산키 가부시키가이샤 반도체 구성요소를 구비한 반도체 장치 및 그 제조 방법
US7723164B2 (en) 2006-09-01 2010-05-25 Intel Corporation Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
US20100127394A1 (en) 2008-11-25 2010-05-27 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US20100216280A1 (en) * 2009-02-20 2010-08-26 National Semiconductor Corporation Integrated circuit micro-module
KR20100105506A (ko) 2009-03-20 2010-09-29 스태츠 칩팩, 엘티디. 듀얼 사이드 연결을 구비하는 집적회로 패키지 시스템 및 그 제조 방법
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
US20110089546A1 (en) 2009-10-16 2011-04-21 National Semiconductor Corporation Multiple leadframe package
US20110101491A1 (en) 2007-09-25 2011-05-05 Oswald Skeete Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US20110108999A1 (en) 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US20110156261A1 (en) 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
US20110156235A1 (en) 2009-12-29 2011-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip package having enhanced thermal and mechanical performance
US20110156231A1 (en) 2009-12-29 2011-06-30 Intel Corporation Recessed and embedded die coreless package
US20110215464A1 (en) 2009-12-29 2011-09-08 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US20110228464A1 (en) 2010-03-17 2011-09-22 Guzek John S System-in-package using embedded-die coreless substrates, and processes of forming same
US20110241186A1 (en) 2010-04-06 2011-10-06 Nalla Ravi K Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US20110241215A1 (en) 2010-04-02 2011-10-06 Sankman Robert L Embedded semiconductive chips in reconstituted wafers, and systems containing same
US20110241195A1 (en) 2010-04-06 2011-10-06 Nalla Ravi K Forming in-situ micro-feature structures with coreless packages
US20110254124A1 (en) 2010-04-16 2011-10-20 Nalla Ravi K Forming functionalized carrier structures with coreless packages
US20110281375A1 (en) 2010-05-12 2011-11-17 Rajasekaran Swaminathan Magnetic microelectronic device attachment
US20110316140A1 (en) 2010-06-29 2011-12-29 Nalla Ravi K Microelectronic package and method of manufacturing same
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US20120009738A1 (en) 2010-07-06 2012-01-12 Crawford Grant A Misalignment correction for embedded microelectronic die applications
US8105934B2 (en) 2004-04-14 2012-01-31 Samsung Electronics Co., Ltd. Bump structure for a semiconductor device and method of manufacture
US20120074581A1 (en) 2010-09-24 2012-03-29 Guzek John S Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
JP2012074536A (ja) 2010-09-29 2012-04-12 Panasonic Corp ハイブリッドコア基板とその製造方法、半導体集積回路パッケージ、及びビルドアップ基板とその製造方法
US20120112336A1 (en) 2010-11-05 2012-05-10 Guzek John S Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
US20120139116A1 (en) 2010-12-07 2012-06-07 Manusharow Mathew J Bumpless build-up layer and laminated core hybrid structures and methods of assembling same
US20120139095A1 (en) 2010-12-03 2012-06-07 Manusharow Mathew J Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same
US8264849B2 (en) 2010-06-23 2012-09-11 Intel Corporation Mold compounds in improved embedded-die coreless substrates, and processes of forming same
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US20130003319A1 (en) 2011-06-30 2013-01-03 Pramod Malatkar Bumpless build-up layer package warpage reduction
WO2013003257A2 (en) 2011-06-27 2013-01-03 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8497587B2 (en) 2009-12-30 2013-07-30 Stmicroelectronics Pte Ltd. Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
WO2013172814A1 (en) 2012-05-14 2013-11-21 Intel Corporation Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
WO2013184145A1 (en) 2012-06-08 2013-12-12 Intel Corporation Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4921160A (en) 1988-02-29 1990-05-01 American Telephone And Telegraph Company Personal data card and method of constructing the same
JPH05166623A (ja) * 1991-12-12 1993-07-02 Matsushita Electric Ind Co Ltd 小形固定コイル
US5899705A (en) 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
FI981219A (fi) * 1998-05-29 1999-11-30 Upm Kymmene Corp Menetelmä ja pakkauskone täytetyn pakkauksen muodostamiseksi, aihiomateriaaliraina ja täytetty pakkaus
JP3768761B2 (ja) * 2000-01-31 2006-04-19 株式会社日立製作所 半導体装置およびその製造方法
JP4530322B2 (ja) * 2001-10-09 2010-08-25 ルネサスエレクトロニクス株式会社 高周波パワーアンプモジュール
JP3938759B2 (ja) * 2002-05-31 2007-06-27 富士通株式会社 半導体装置及び半導体装置の製造方法
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
JP2004200201A (ja) * 2002-12-16 2004-07-15 Taiyo Yuden Co Ltd 電子部品内蔵型多層基板
US7294533B2 (en) 2003-06-30 2007-11-13 Intel Corporation Mold compound cap in a flip chip multi-matrix array package and process of making same
WO2005024946A1 (ja) * 2003-09-04 2005-03-17 Renesas Technology Corp. 半導体装置およびその製造方法
KR100593703B1 (ko) 2004-12-10 2006-06-30 삼성전자주식회사 돌출부 와이어 본딩 구조 보강용 더미 칩을 포함하는반도체 칩 적층 패키지
TWI245388B (en) 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
CN101147249B (zh) * 2005-03-24 2010-05-19 松下电器产业株式会社 电子部件安装方法和电子电路装置
US20070279885A1 (en) 2006-05-31 2007-12-06 Basavanhally Nagesh R Backages with buried electrical feedthroughs
TWI301663B (en) 2006-08-02 2008-10-01 Phoenix Prec Technology Corp Circuit board structure with embedded semiconductor chip and fabrication method thereof
US8034661B2 (en) 2009-11-25 2011-10-11 Stats Chippac, Ltd. Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
JP5460388B2 (ja) 2010-03-10 2014-04-02 新光電気工業株式会社 半導体装置及びその製造方法
US8519519B2 (en) * 2010-11-03 2013-08-27 Freescale Semiconductor Inc. Semiconductor device having die pads isolated from interconnect portion and method of assembling same
US9159649B2 (en) 2011-12-20 2015-10-13 Intel Corporation Microelectronic package and stacked microelectronic assembly and computing system containing same
JP5166623B1 (ja) * 2012-02-07 2013-03-21 寛治 泉 泳がせ釣り用具、およびその方法。
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer

Patent Citations (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510649A (en) 1992-05-18 1996-04-23 Motorola, Inc. Ceramic semiconductor package having varying conductive bonds
US5497033A (en) 1993-02-08 1996-03-05 Martin Marietta Corporation Embedded substrate for integrated circuit modules
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6159767A (en) 1996-05-20 2000-12-12 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US20010015492A1 (en) 1996-05-24 2001-08-23 Salman Akram Packaged die on pcb with heat sink encapsulant
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6239482B1 (en) 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6507122B2 (en) 1999-08-09 2003-01-14 International Business Machines Corporation Pre-bond encapsulation of area array terminated chip and wafer scale packages
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6396153B2 (en) 1999-10-04 2002-05-28 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6426545B1 (en) 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US7112467B2 (en) 2000-02-10 2006-09-26 Epic Technologies, Inc. Structure and method for temporarily holding integrated circuit chips in accurate alignment
US6818544B2 (en) 2000-02-10 2004-11-16 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6555908B1 (en) 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US7189596B1 (en) 2000-03-01 2007-03-13 Intel Corporation Process for forming a direct build-up layer on an encapsulated die packages utilizing intermediate structures
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US7078788B2 (en) 2000-08-16 2006-07-18 Intel Corporation Microelectronic substrates with integrated devices
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6825063B2 (en) 2000-09-08 2004-11-30 Intel Corporation Integrated core microelectronic package
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US7416918B2 (en) 2000-09-13 2008-08-26 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US20020088116A1 (en) 2000-09-19 2002-07-11 International Business Machines Corporation Method of making a CTE compensated chip interposer
US6617682B1 (en) 2000-09-28 2003-09-09 Intel Corporation Structure for reducing die corner and edge stresses in microelectronic packages
US6794223B2 (en) 2000-09-28 2004-09-21 Intel Corporation Structure and process for reducing die corner and edge stresses in microelectronic packages
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6964889B2 (en) 2000-10-18 2005-11-15 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6902950B2 (en) 2000-10-18 2005-06-07 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US7067356B2 (en) 2000-12-15 2006-06-27 Intel Corporation Method of fabricating microelectronic package having a bumpless laminated interconnection layer
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6703400B2 (en) 2001-02-23 2004-03-09 Schering Corporation Methods for treating multidrug resistance
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US20020145204A1 (en) * 2001-04-06 2002-10-10 Hitachi, Ltd. Semiconductor device
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6586276B2 (en) 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US6472762B1 (en) 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6580611B1 (en) 2001-12-21 2003-06-17 Intel Corporation Dual-sided heat removal system
US7420273B2 (en) 2002-01-07 2008-09-02 Intel Corporation Thinned die integrated circuit package
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
US7144756B1 (en) 2003-11-20 2006-12-05 Altera Corporation Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate
US8105934B2 (en) 2004-04-14 2012-01-31 Samsung Electronics Co., Ltd. Bump structure for a semiconductor device and method of manufacture
US7442581B2 (en) 2004-12-10 2008-10-28 Freescale Semiconductor, Inc. Flexible carrier and release method for high volume electronic package fabrication
US7109055B2 (en) 2005-01-20 2006-09-19 Freescale Semiconductor, Inc. Methods and apparatus having wafer level chip scale package for sensing elements
US20060186536A1 (en) 2005-02-02 2006-08-24 Shih-Ping Hsu Substrate assembly with direct electrical connection as a semiconductor package
US7160755B2 (en) 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
US20090121347A1 (en) 2005-06-29 2009-05-14 Rohm Co., Ltd. Semiconductor Device and Semiconductor Device Assembly
US7459782B1 (en) 2005-10-05 2008-12-02 Altera Corporation Stiffener for flip chip BGA package
US7425464B2 (en) 2006-03-10 2008-09-16 Freescale Semiconductor, Inc. Semiconductor device packaging
US7723164B2 (en) 2006-09-01 2010-05-25 Intel Corporation Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
US7659143B2 (en) 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US7476563B2 (en) 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US7588951B2 (en) 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
US7655502B2 (en) 2006-11-17 2010-02-02 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
US20080128916A1 (en) 2006-12-04 2008-06-05 Nec Electronics Corporation Semiconductor device including microstrip line and coplanar line
US7632715B2 (en) 2007-01-05 2009-12-15 Freescale Semiconductor, Inc. Method of packaging semiconductor devices
US20080308917A1 (en) * 2007-06-13 2008-12-18 Infineon Technologies Ag Embedded chip package
US7648858B2 (en) 2007-06-19 2010-01-19 Freescale Semiconductor, Inc. Methods and apparatus for EMI shielding in multi-chip modules
US20080315398A1 (en) 2007-06-22 2008-12-25 Hsing-Lun Lo Packaging substrate with embedded chip and buried heatsink
US20100047970A1 (en) 2007-06-25 2010-02-25 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US7619901B2 (en) 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
US20080315377A1 (en) 2007-06-25 2008-12-25 Epic Technologies, Inc. Packaged electronic modules and fabrication methods thereof implementing a cell phone or other electronic system
US20100044855A1 (en) 2007-06-25 2010-02-25 Epic Technologies, Inc. Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US20080315391A1 (en) 2007-06-25 2008-12-25 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
KR20100038232A (ko) 2007-08-24 2010-04-13 가시오게산키 가부시키가이샤 반도체 구성요소를 구비한 반도체 장치 및 그 제조 방법
US7595226B2 (en) 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US20110101491A1 (en) 2007-09-25 2011-05-05 Oswald Skeete Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US20090079064A1 (en) 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
US20090152743A1 (en) 2007-12-15 2009-06-18 Houssam Jomaa Routing layer for a microelectronic device, microelectronic package containing same, and method of forming a multi-thickness conductor in same for a microelectronic device
US8035216B2 (en) 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
US20090212416A1 (en) 2008-02-22 2009-08-27 Skeete Oswald L Integrated circuit package and method of manufacturing same
US20090236031A1 (en) 2008-03-24 2009-09-24 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring substrate and method of manufacturing semiconductor device
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US20100013101A1 (en) 2008-07-18 2010-01-21 Harry Hedler Method for Manufacturing a Multichip Module Assembly
US20100073894A1 (en) 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US20120005887A1 (en) 2008-09-22 2012-01-12 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US7633143B1 (en) * 2008-09-22 2009-12-15 Powertech Technology Inc. Semiconductor package having plural chips side by side arranged on a leadframe
US20100127394A1 (en) 2008-11-25 2010-05-27 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US20100216280A1 (en) * 2009-02-20 2010-08-26 National Semiconductor Corporation Integrated circuit micro-module
KR20100105506A (ko) 2009-03-20 2010-09-29 스태츠 칩팩, 엘티디. 듀얼 사이드 연결을 구비하는 집적회로 패키지 시스템 및 그 제조 방법
US20110156261A1 (en) 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
US20110089546A1 (en) 2009-10-16 2011-04-21 National Semiconductor Corporation Multiple leadframe package
US20110108999A1 (en) 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US20110156231A1 (en) 2009-12-29 2011-06-30 Intel Corporation Recessed and embedded die coreless package
US20110215464A1 (en) 2009-12-29 2011-09-08 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US20110156235A1 (en) 2009-12-29 2011-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip package having enhanced thermal and mechanical performance
US8497587B2 (en) 2009-12-30 2013-07-30 Stmicroelectronics Pte Ltd. Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US20110228464A1 (en) 2010-03-17 2011-09-22 Guzek John S System-in-package using embedded-die coreless substrates, and processes of forming same
US20110241215A1 (en) 2010-04-02 2011-10-06 Sankman Robert L Embedded semiconductive chips in reconstituted wafers, and systems containing same
US20130328207A1 (en) 2010-04-02 2013-12-12 Robert L. Sankman Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US20110241186A1 (en) 2010-04-06 2011-10-06 Nalla Ravi K Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US20110241195A1 (en) 2010-04-06 2011-10-06 Nalla Ravi K Forming in-situ micro-feature structures with coreless packages
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US20110254124A1 (en) 2010-04-16 2011-10-20 Nalla Ravi K Forming functionalized carrier structures with coreless packages
US20110281375A1 (en) 2010-05-12 2011-11-17 Rajasekaran Swaminathan Magnetic microelectronic device attachment
US8264849B2 (en) 2010-06-23 2012-09-11 Intel Corporation Mold compounds in improved embedded-die coreless substrates, and processes of forming same
US20110316140A1 (en) 2010-06-29 2011-12-29 Nalla Ravi K Microelectronic package and method of manufacturing same
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US20120009738A1 (en) 2010-07-06 2012-01-12 Crawford Grant A Misalignment correction for embedded microelectronic die applications
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US20120074581A1 (en) 2010-09-24 2012-03-29 Guzek John S Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
JP2012074536A (ja) 2010-09-29 2012-04-12 Panasonic Corp ハイブリッドコア基板とその製造方法、半導体集積回路パッケージ、及びビルドアップ基板とその製造方法
US20120112336A1 (en) 2010-11-05 2012-05-10 Guzek John S Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
US20120139095A1 (en) 2010-12-03 2012-06-07 Manusharow Mathew J Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same
US20120139116A1 (en) 2010-12-07 2012-06-07 Manusharow Mathew J Bumpless build-up layer and laminated core hybrid structures and methods of assembling same
WO2013003257A2 (en) 2011-06-27 2013-01-03 Intel Corporation Secondary device integration into coreless microelectronic device packages
WO2013003257A3 (en) 2011-06-27 2013-03-07 Intel Corporation Secondary device integration into coreless microelectronic device packages
WO2013003695A3 (en) 2011-06-30 2013-05-02 Intel Corporation Bumpless build-up layer package warpage reduction
WO2013003695A2 (en) 2011-06-30 2013-01-03 Intel Corporation Bumpless build-up layer package warpage reduction
US20130003319A1 (en) 2011-06-30 2013-01-03 Pramod Malatkar Bumpless build-up layer package warpage reduction
WO2013172814A1 (en) 2012-05-14 2013-11-21 Intel Corporation Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
US20140021635A1 (en) 2012-05-14 2014-01-23 Eng Huat Goh Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
WO2013184145A1 (en) 2012-06-08 2013-12-12 Intel Corporation Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer
US20140048959A1 (en) 2012-06-08 2014-02-20 Chuan Hu Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
International Preliminary Report on Patentability received for PCT Patent Application No. PCT/US2012/043945, mailed on Jan. 16, 2014, 9 Pages.
International Search Report and Written Opinion received for PCT Application No. PCT/US2012/037787, mailed on Jul. 26, 2013, 11 pages.
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US2012/041714, mailed on Feb. 26, 2013, 10 pages.
International Search Report and Written Opinion Received for PCT Patent Application No. PCT/US2012/043945, Mailed on Jan. 10, 2013, 12 pages.
International Search Report and Written Opinion Received for PCT Patent Application No. PCT/US2012/044871, mailed on Jan. 10, 2013, 10 pages.
Ma, Qing, "Direct BUiLD-Up Layer on an Encapsulated Die Package", U.S. Appl. No. 09/640,961, filed Aug. 16, 2000, 70 pages.
Office Action received for Taiwan Patent Application No. 101119764, Mailed on Dec. 10, 2012, 2 pages.
Office Action received for Taiwan Patent Application No. 101119764, mailed on Mar. 24, 2014, 15 pages of Office Action Including 9 pages of English Translation.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9646851B2 (en) 2010-04-02 2017-05-09 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US10651051B2 (en) 2010-04-02 2020-05-12 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US11257688B2 (en) 2010-04-02 2022-02-22 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US9686870B2 (en) 2011-06-27 2017-06-20 Intel Corporation Method of forming a microelectronic device package
US20140177193A1 (en) * 2012-12-21 2014-06-26 Liwen Jin Bumpless build-up layer package including a release layer
US9320149B2 (en) * 2012-12-21 2016-04-19 Intel Corporation Bumpless build-up layer package including a release layer
US9295158B2 (en) * 2013-11-05 2016-03-22 Sunasic Technologies, Inc. Method of manufacturing printed circuit board having electronic component embedded
US11670613B2 (en) * 2019-12-31 2023-06-06 At&S (China) Co. Ltd. Arrangement with central carrier and two opposing layer stacks, component carrier and manufacturing method

Also Published As

Publication number Publication date
DE112012002654B4 (de) 2017-12-28
GB201321492D0 (en) 2014-01-22
TW201330726A (zh) 2013-07-16
JP2014523119A (ja) 2014-09-08
WO2013003257A3 (en) 2013-03-07
SG194999A1 (en) 2013-12-30
DE112012007316B3 (de) 2020-01-23
GB2505802B (en) 2016-01-06
DE112012002654T5 (de) 2014-04-17
CN103620767A (zh) 2014-03-05
US20150135526A1 (en) 2015-05-21
GB2505802A (en) 2014-03-12
WO2013003257A2 (en) 2013-01-03
CN103620767B (zh) 2016-11-09
JP5866441B2 (ja) 2016-02-17
US20120326271A1 (en) 2012-12-27
TWI489917B (zh) 2015-06-21
US9686870B2 (en) 2017-06-20

Similar Documents

Publication Publication Date Title
US9686870B2 (en) Method of forming a microelectronic device package
US9627227B2 (en) Bumpless build-up layer package warpage reduction
WO2019210617A1 (zh) 晶圆级系统封装方法及封装结构
US9362253B2 (en) Bumpless build-up layer package with pre-stacked microelectronic devices
TWI647799B (zh) 半導體封裝及其製造方法
US8952519B2 (en) Chip package and fabrication method thereof
TWI579966B (zh) 半導體封裝系統及方法
US8432032B2 (en) Chip package and fabrication method thereof
TWI696226B (zh) 半導體元件和製造方法
US9741762B2 (en) Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device
US11309279B2 (en) Package structure of wafer-level system-in-package
TW201906021A (zh) 半導體封裝結構及其製造方法
KR20210035037A (ko) 반도체 디바이스 및 제조 방법
KR20170026372A (ko) 배선 기판의 제조 방법 및 배선 기판
TWI697080B (zh) 晶片封裝結構及其製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TEH, WENG HONG;GUZEK, JOHN S.;REEL/FRAME:027145/0671

Effective date: 20110623

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551)

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8