US8853684B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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US8853684B2
US8853684B2 US13/109,594 US201113109594A US8853684B2 US 8853684 B2 US8853684 B2 US 8853684B2 US 201113109594 A US201113109594 A US 201113109594A US 8853684 B2 US8853684 B2 US 8853684B2
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insulating layer
layer
oxide
oxide semiconductor
electrode layer
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US20110284854A1 (en
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Yuta ENDO
Toshinari Sasaki
Kosei Noda
Mizuho Sato
Mitsuhiro Ichijo
Toshiya Endo
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

Definitions

  • the present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.
  • a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electrooptic device, a semiconductor circuit, and an electronic device are all semiconductor devices.
  • transistors which are used for many liquid crystal display devices and light-emitting display devices typified by flat panel displays have included a silicon semiconductor such as amorphous silicon or polycrystalline silicon and have been formed over glass substrates.
  • Patent Document 1 For example, techniques by which a transistor is manufactured using zinc oxide which is a single-component metal oxide or an In—Ga—Zn—O-based oxide which is a homologous compound as an oxide semiconductor, and is used as a switching element or the like of a pixel of a display device, is disclosed (see Patent Document 1 to Patent Document 3).
  • an object of an embodiment of the present invention disclosed in this specification is to provide a semiconductor device with favorable electric characteristics.
  • an insulating layer with a low hydrogen content is used as an insulating layer being in contact with an oxide semiconductor layer which forms a channel region, whereby diffusion of hydrogen into the oxide semiconductor layer can be prevented.
  • an insulating layer in which the concentration of hydrogen is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 is used as the insulating layer being in contact with the oxide semiconductor layer.
  • An embodiment of the present invention is a semiconductor device which comprises a gate electrode layer, an oxide semiconductor layer which forms a channel region, a source electrode layer and a drain electrode layer being in contact with the oxide semiconductor layer, a gate insulating layer provided between the gate electrode layer and the oxide semiconductor layer, and an insulating layer which faces the gate insulating layer with the oxide semiconductor layer interposed therebetween and is in contact with the oxide semiconductor layer, in which the concentration of hydrogen is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • a transistor having a top-gate structure, in which a gate electrode layer overlaps with an oxide semiconductor layer with a gate insulating layer interposed therebetween has a top-contact type and a bottom-contact type.
  • the top-contact transistor includes an oxide semiconductor layer between source and drain electrode layers and the insulating layer
  • the bottom-contact transistor includes source and drain electrode layers between the oxide semiconductor layer and the insulating layer.
  • Another embodiment of the present invention is a semiconductor device including a top-gate/top-contact transistor and a top-gate/bottom contact transistor in which the concentration of hydrogen in an insulating layer being in contact with an oxide semiconductor layer is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • an oxide insulating layer comprising silicon oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, aluminum oxide, or tantalum oxide can be used as the insulating layer.
  • a gate insulating layer with a low hydrogen content is used as the gate insulating layer provided for the top-gate/top-contact transistor and the top-gate/bottom contact transistor, whereby a semiconductor device having favorable electric characteristics can be obtained.
  • Another embodiment of the present invention is a semiconductor device in which the concentration of hydrogen in the gate insulating layer being in contact with the oxide semiconductor layer is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • a semiconductor device having favorable electric characteristics can be provided.
  • FIGS. 1A and 1B illustrate a top view and a cross-sectional view of a transistor, respectively.
  • FIGS. 2A to 2D are cross-sectional views illustrating a method for manufacturing a transistor.
  • FIGS. 3A and 3B illustrate a top view and a cross-sectional view of a transistor, respectively.
  • FIGS. 4A to 4D are cross-sectional views illustrating a method for manufacturing a transistor.
  • FIG. 5 is an external view illustrating an example of an electronic book reader.
  • FIGS. 6A and 6B are external views illustrating respective examples of a television device and a digital photo frame.
  • FIG. 7 is a perspective view illustrating an example of a portable computer.
  • FIG. 8 is a graph showing the concentration of hydrogen contained in an insulating layer.
  • FIG. 9 is a graph showing a measurement result of electric characteristics of a transistor.
  • each of A and B corresponds to an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).
  • object e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer.
  • source and drain may become switched in the case that a direction of a current flow is changed during circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.
  • FIGS. 1A and 1B a semiconductor device which is one embodiment of the present invention is described with reference to FIGS. 1A and 1B .
  • FIG. 1A is a top view of a transistor 100 included in a semiconductor device.
  • FIG. 1B is a cross sectional view along line A 1 -B 1 of FIG. 1A .
  • the transistor 100 includes, over a substrate 102 , an insulating layer 104 , a source electrode layer 106 a and a drain electrode layer 106 b , an oxide semiconductor layer 108 including a channel region, a gate insulating layer 110 , and a gate electrode layer 112 .
  • the transistor 100 is a transistor having a top-gate structure, in which a gate electrode layer 112 is formed so as to overlap with the oxide semiconductor layer 108 with the gate insulating layer 110 interposed therebetween. Further, the transistor 100 is a bottom-contact transistor in which the source electrode layer 106 a and the drain electrode layer 106 b are provided between the oxide semiconductor layer 108 and the insulating layer 104 .
  • an insulating layer in which the concentration of hydrogen is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 is used as the insulating layer 104 being in contact with the oxide semiconductor layer 108 , whereby diffusion of hydrogen in the oxide semiconductor layer 108 can be prevented and a transistor having favorable electric characteristics can be provided. Accordingly, a transistor having favorable electric characteristics can be provided without increasing the number of manufacturing steps of the transistor.
  • the concentration of hydrogen in the gate insulating layer 110 can be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • the concentration of hydrogen in each of the insulating layer 104 and the gate insulating layer 110 is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 , whereby diffusion of hydrogen in the oxide semiconductor layer 108 can be suppressed.
  • the substrate 102 there is no particular limitation on the substrate 102 as long as it has a resistance for the manufacturing steps performed later.
  • an insulating substrate such as a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate; a semiconductor substrate which is formed using a semiconductor material such as silicon; a conductive substrate which is formed using a conductor such as metal or stainless steel; or a substrate in which the surface of a semiconductor substrate or the surface of a conductive substrate is covered with an insulating material, can be used.
  • a plastic substrate can be used as the substrate 102 as appropriate.
  • a glass substrate whose strain point is greater than or equal to 730° C. is preferably used in the case where heat treatment at a high temperature is performed in the manufacturing steps of the transistor.
  • a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example.
  • barium oxide (BaO) barium oxide
  • a glass substrate containing a larger amount of BaO than B 2 O 3 is preferably used.
  • the insulating layer 104 serves as a base to prevent diffusion of an impurity element from the substrate 102 and also serves as a base to prevent the substrate from being etched by etching in the manufacturing steps of the transistor.
  • the thickness of the insulating layer 104 is preferably greater than or equal to 50 nm.
  • the insulating layer 104 is formed with a single-layer structure using any of oxide insulating layers of silicon oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, aluminum oxide, tantalum oxide, and the like; or a stacked structure including two or more layers selected from these layers.
  • oxide insulating layers of silicon oxide, silicon oxynitride, silicon nitride oxide, hafnium oxide, aluminum oxide, tantalum oxide, and the like.
  • a stacked structure including two or more layers selected from these layers.
  • an insulating layer being in contact with the substrate 102 is formed using a silicon nitride and the insulating layer 104 being in contact with the oxide semiconductor layer 108 is formed using the above-mentioned oxide insulating layer.
  • An oxide insulating layer in which the concentration of hydrogen is reduced is used as the insulating layer 104 being in contact with the oxide semiconductor layer 108 , whereby, diffusion of hydrogen in the oxide semiconductor layer 108 is prevented and a transistor having favorable electric characteristics can be provided because oxygen is supplied to defects in the oxide semiconductor layer 108 from the insulating layer 104 .
  • the concentration of hydrogen in the insulating layer 104 be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • a silicon oxynitride means the one that contains more oxygen than nitrogen and for example, silicon oxynitride includes oxygen, nitrogen, and silicon at concentrations ranging from greater than or equal to 50 atomic % and less than or equal to 70 atomic %, greater than or equal to 0.5 atomic % and less than or equal to 15 atomic %, and greater than or equal to 25 atomic % and less than or equal to 35 atomic %, respectively.
  • silicon nitride oxide means the one that contains more nitrogen than oxygen and for example, silicon nitride oxide includes oxygen, nitrogen, and silicon at concentrations ranging from greater than or equal to 5 atomic % and less than or equal to 30 atomic %, greater than or equal to 20 atomic % and less than or equal to 55 atomic %, and greater than or equal to 25 atomic % and less than or equal to 35 atomic %, respectively.
  • rates of oxygen, nitrogen, and silicon fall within the aforementioned ranges in the cases where measurement is performed using Rutherford backscattering spectrometry (RBS) or hydrogen forward scattering (HFS).
  • RBS Rutherford backscattering spectrometry
  • HFS hydrogen forward scattering
  • the total of the percentages of the constituent elements does not exceed 100 atomic %.
  • a silicon oxide layer formed by sputtering is used as the insulating layer 104 and a silicon oxide layer formed by a plasma enhanced chemical vapor deposition (plasma CVD) is used as the insulating layer 104 .
  • plasma CVD plasma enhanced chemical vapor deposition
  • a target containing a silicon element is preferably used. That is to say, a Si target or SiO 2 target can be used.
  • a SiO 2 target is used in order to reduce the concentration of hydrogen in the obtained oxide silicon layer, more preferably a SiO 2 target in which the concentration of a hydroxyl group contained in the SiO 2 target is less than or equal to 1000 ppm or the concentration of hydrogen measured using secondary ion mass spectrometry (SIMS) is less than or equal to 3.5 ⁇ 10 19 atoms/cm 3 is used.
  • gases to be supplied for forming the insulating layer 104 a rare gas such as argon and oxygen are used. Further, it is preferable to use high-purity gas in which impurities such as hydrogen, water, a hydroxyl group, or hydride are reduced to a concentration of a “ppm” level or a “ppb” level as gases to be supplied.
  • sputtering examples include RF sputtering in which a high-frequency power source is used for a sputtering power supply, DC sputtering, and pulsed DC sputtering in which a bias is applied in a pulsed manner.
  • a multi-source sputtering apparatus in which a plurality of targets of different materials can be placed may be used for forming the insulating layer 104 .
  • films of different materials can be formed to be stacked in the same chamber, or a film of plural kinds of materials can be formed by electric discharge at the same time in the same chamber.
  • a sputtering apparatus provided with a magnet system inside the chamber, which is for magnetron sputtering, and a sputtering apparatus which is used for ECR sputtering in which plasma produced with the use of microwaves is used without using glow discharge.
  • sputtering reactive sputtering in which a target substance and a sputtering gas component are chemically reacted with each other to form a thin compound film thereof, or bias sputtering in which voltage is also applied to a substrate can be used.
  • sputtering can be performed while the substrate is heated using the above-described sputtering apparatus and sputtering as appropriate.
  • the concentration of hydrogen in the obtained oxide silicon layer can be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • Plasma CVD can be used for the formation of the insulating layer 104 .
  • Plasma CVD is a method for forming a film by supplying a deposition gas to be raw materials to a reaction chamber of a plasma CVD apparatus to employ plasma energy.
  • a capacitively coupled high-frequency plasma CVD apparatus using a high-frequency power source an inductively coupled high-frequency plasma CVD apparatus, a microwave plasma CVD apparatus (an electron cyclotron resonant plasma CVD apparatus) which has magnetron that is a microwave generation source and generates plasma using the microwave, and a helicon wave plasma CVD apparatus are given.
  • a CVD apparatus in which glow discharge plasma is utilized for the formation of the film can be used as appropriate. Further, plasma CVD can be also performed while the substrate is heated.
  • the insulating layer 104 in which the concentration of hydrogen is reduced is formed by plasma CVD, a gas in which hydrogen is not contained in its molecular structure is needed to be selected as the deposition gas.
  • the deposition gas not SiH 4 but SiF 4 is used.
  • an oxidizing gas of N 2 O or O 2 with a low content of hydrogen and water is also used so that a film to be deposited is an oxide insulating film.
  • a gas with a low content of hydrogen and water is used also as the other gases to be added (a rare gas such as argon) in consideration of the spread of plasma generated in the plasma CVD apparatus.
  • the oxide silicon layer to be the insulating layer 104 is formed by plasma CVD, impurities such as hydrogen and water which remain in the reaction chamber of the plasma CVD apparatus or adsorb onto the inner wall of the reaction chamber are removed, and then the oxide silicon layer is formed using the above-mentioned gases.
  • the concentration of hydrogen in the insulating layer 104 formed by plasma CVD can be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • the source electrode layer 106 a and the drain electrode layer 106 b are formed over the insulating layer 104 .
  • the source electrode layer 106 a and the drain electrode layer 106 b can be formed with a single layer or a stacked layer using a conductive film of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium, or an alloy material which contains any of these metal materials as a main component, or a nitride of any of these metals.
  • a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium
  • an alloy material which contains any of these metal materials as a main component, or a nitride of any of these metals.
  • aluminum or copper can also be used as such a metal material if it can withstand the temperature of heat treatment to be performed in a later process.
  • Aluminum or copper is preferably used in combination with a refractory metal material in order to avoid problems of heat resistance and corrosion.
  • a refractory metal material molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like can be used.
  • the following structure is preferable as a two-layer structure of the source electrode layer 106 a and the drain electrode layer 106 b : a two-layer structure in which a molybdenum film is stacked over an aluminum film; a two-layer structure in which a molybdenum film is stacked over a copper film; a two-layer structure in which a titanium nitride film or a tantalum nitride film is stacked over a copper film; a two-layer structure in which a titanium nitride film and a molybdenum film are stacked; or a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film.
  • the following structure is preferable: a stacked structure including an aluminum film, an alloy film of aluminum and silicon, an alloy film of aluminum and titanium, or an alloy film of aluminum and neodymium in a middle layer and any of a tungsten film, a tungsten nitride film, a titanium nitride film, and a titanium film in a top layer and a bottom layer.
  • a light-transmitting oxide conductive film of indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, gallium zinc oxide, or the like may be used for the source electrode layer 106 a and the drain electrode layer 106 b.
  • the thickness of the source electrode layer 106 a and the drain electrode layer 106 b is not particularly limited and can be determined as appropriate in consideration of electric resistance and time required for a manufacturing process of the conductive film serving as the source electrode layer 106 a and the drain electrode layer 106 b .
  • the source electrode layer 106 a and the drain electrode layer 106 b can be formed to have thickness of 10 nm to 500 nm.
  • the oxide semiconductor layer 108 which forms a channel region is formed so as to be in contact with part of the upper surfaces of the source electrode layer 106 a and the drain electrode layer 106 b and part of the upper surface of the insulating layer 104 . Because the concentration of hydrogen in the insulating layer 104 is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 as described above, diffusion of hydrogen in the oxide semiconductor layer 108 can be prevented when the oxide semiconductor layer 108 is formed.
  • the thickness of the oxide semiconductor layer 108 is set to 10 nm to 300 nm, preferably 20 nm to 100 nm.
  • the oxide semiconductor layer 108 is formed using an In—Ga—Zn—O-based non-single-crystal film which contains In, Ga, and Zn and has a structure represented as InMO 3 (ZnO) m (m>0).
  • M denotes one or more of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co).
  • M denotes Ga in some cases; meanwhile, M denotes the above metal element such as Ni or Fe in addition to Ga in other cases.
  • the above oxide semiconductor may contain Fe or Ni, another transitional metal element, or an oxide of the transitional metal as an impurity element in addition to the metal element contained as M.
  • a metal oxide contained in the metal oxide target have a relative density of higher than or equal to 80%, preferably higher than or equal to 95%, more preferably higher than or equal to 99.9% is used.
  • the oxide semiconductor layer 108 can be formed using any of the following oxide semiconductors: an oxide of four metal elements such as an In—Sn—Ga—Zn—O-based oxide semiconductor; oxides of three metal elements such as an In—Ga—Zn—O—based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, and a Sn—Al—Zn—O-based oxide semiconductor; oxides of two metal elements such as an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, and an In—Mg—O-based oxide semiconductor; and oxides of one metal element such as an In—O-based oxide semiconductor,
  • an In—Ga—Zn—O-based oxide semiconductor is an oxide semiconductor containing at least In, Ga, and Zn, and there is no particular limitation on the composition ratio thereof.
  • the In—Ga—Zn—O-based oxide semiconductor may contain an element other than In, Ga, and Zn.
  • silicon oxide may be included in the above oxide semiconductor layer.
  • the gate insulating layer 110 is formed so as to cover the source electrode layer 106 a , the drain electrode layer 106 b , and the oxide semiconductor layer 108 .
  • the gate insulating layer 110 is formed using an oxide insulating layer, similarly to the insulating layer 104 .
  • the gate insulating layer 110 is formed with a low hydrogen content, whereby a semiconductor device having favorable electric characteristics can be obtained.
  • the concentration of hydrogen in the gate insulating layer being in contact with the oxide semiconductor layer be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • the gate electrode 112 is formed so as to overlap with the oxide semiconductor layer 108 with the gate insulating layer 110 interposed therebetween.
  • the gate electrode 112 can have a structure similar to that of the source electrode layer 106 a and the drain electrode layer 106 b.
  • an insulating layer serving as a passivation layer or an interlayer insulating layer is preferably formed over the transistor.
  • the concentration of hydrogen in one or both of the insulating layer 104 and the gate insulating layer 110 is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 ; thus, diffusion of hydrogen in the oxide semiconductor layer 108 can be prevented and a semiconductor device having favorable electric characteristics can be obtained.
  • Embodiment 1 Note that a method for manufacturing the semiconductor device described in Embodiment 1 is described in this embodiment with reference to FIGS. 2A to 2D .
  • the insulating layer 104 is formed over the substrate 102 .
  • the material described in Embodiment 1 can be used for the substrate 102 and the insulating layer 104 .
  • a glass substrate is used for the substrate 102 .
  • a silicon oxide layer is formed to have a thickness of 200 nm by RF sputtering using SiO 2 as a target and a rare gas such as argon and oxygen as gases to be supplied when the insulating layer 104 is formed.
  • the inner wall of the reaction chamber in the plasma CVD apparatus is heated to release impurities from the inner wall of the reaction chamber and remove impurities remaining in the reaction chamber or adsorbing onto the inner wall of the reaction chamber. Then, SiF 4 as the deposition gas, N 2 O the oxidizing gas, and argon as the gas to be added are supplied to the reaction chamber, whereby the insulating layer 104 is formed using plasma energy.
  • a plasma CVD apparatus using a high-frequency power source is used.
  • an exhaust process, plasma cleaning using a fluorine compound such as nitrogen trifluoride, or the like is preferably performed.
  • the conductive film serving as the source electrode layer 106 a and the drain electrode layer 106 b is formed.
  • a titanium film with a thickness of 150 nm is formed by DC sputtering using a titanium target.
  • the source electrode layer 106 a and the drain electrode layer 106 b each having a thickness of 150 nm are formed by performing a first photolithography step and an etching step.
  • Either wet etching or dry etching may be used for the etching of the conductive film. Note that dry etching is preferably used in terms of microfabrication of the element. An etching gas and an etchant can be selected as appropriate depending on a material of layers to be etched.
  • the side surfaces of the source electrode layer 106 a and the drain electrode layer 106 b are formed to have a tapered shape. This is in order to prevent disconnection at a step portion because the oxide semiconductor film and the conductive film to be the gate electrode are formed over the source electrode layer 106 a and the drain electrode layer 106 b in a later step.
  • etching may be performed while the resist mask is recessed.
  • the oxide semiconductor film with a thickness of 50 nm is formed by DC sputtering.
  • Oxygen is supplied to defects in the oxide semiconductor layer from the insulating layer 104 because the oxide semiconductor film is formed to be in contact with the insulating layer 104 .
  • an oxide semiconductor layer 107 that is processed into an island shape is formed by performing a photolithography step or an etching step.
  • DC sputtering is used; however, vacuum evaporation, pulse laser deposition, CVD, and the like may be used.
  • the oxide semiconductor described in Embodiment 1 can be used as the oxide semiconductor film.
  • DC sputtering is employed, a flow rate of argon is 30 sccm, a flow rate of oxygen is 15 sccm, and a substrate temperature is a room temperature (15° C. to 35° C.).
  • the relation of Z>1.5X+Y is satisfied.
  • reverse sputtering in which plasma is generated by introduction of an argon gas is preferably performed.
  • the reverse sputtering refers to a method in which an RF power source is used for application of voltage to a substrate in an argon atmosphere and plasma is generated around the substrate to modify a surface.
  • an argon atmosphere instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, or the like may be used.
  • an argon atmosphere to which oxygen, nitrous oxide, or the like is added may be used.
  • an argon atmosphere to which chlorine, carbon tetrafluoride, or the like is added may be used.
  • the substrate is held in a treatment chamber that is maintained at reduced pressure and is heated so that the substrate temperature is higher than or equal to 100° C. and lower than 550° C., preferably higher than or equal to 200° C. and lower than or equal to 400° C.
  • the substrate temperature in forming the oxide semiconductor film may be a room temperature (15° C. to 35° C.). Then, moisture in the treatment chamber is removed, a sputtering gas from which hydrogen, water, or the like has been removed is introduced, and the oxide semiconductor target is used; thus, the oxide semiconductor film is formed.
  • the oxide semiconductor film is formed while the substrate is heated, so that impurities contained in the oxide semiconductor film can be reduced.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, a titanium sublimation pump, or the like can be used.
  • a turbo pump provided with a cold trap may be used. Since it is possible to remove hydrogen, water, or the like from the treatment chamber by evacuating the treatment chamber with a cryopump or the like, the concentration of an impurity in the oxide semiconductor film can be reduced.
  • FIG. 2B The structure provided through the steps up to here is illustrated in FIG. 2B .
  • the oxide semiconductor layer 107 may be subjected to heat treatment in the atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), or in the atmosphere where the dew point under atmospheric pressure is less than or equal to ⁇ 60° C. and the moisture content is small.
  • the oxide semiconductor layer 107 is subjected to heat treatment in the atmosphere at greater than or equal to 100° C. and less than or equal to 400° C. for 10 minutes or more, preferably at 350° C. for 60 minutes.
  • the oxide semiconductor layer 107 is subjected to heat treatment, whereby the oxide semiconductor layer 108 in which moisture and hydrogen are eliminated is formed. At that time, oxygen is supplied to defects in the oxide semiconductor layer 108 from the insulating layer 104 .
  • rapid thermal annealing (RTA) treatment can be performed in an inert gas atmosphere (such as nitrogen, helium, neon, or argon) at a temperature of higher than or equal to 500° C. and lower than or equal to 750° C. (or a temperature lower than or equal to the strain point of the glass substrate) for approximately 1 minute to 10 minutes, preferably at 600° C. for approximately 3 minutes to 6 minutes. Since dehydration or dehydrogenation can be performed in a short time with RTA treatment, the heat treatment can be performed even at a temperature over the strain point of a glass substrate.
  • an inert gas atmosphere such as nitrogen, helium, neon, or argon
  • the inert gas nitrogen or a rare gas such as helium, neon, or argon
  • the purity of nitrogen or the rare gas such as helium, neon, or argon which is introduced into a heat treatment apparatus be set to be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).
  • the timing of the above heat treatment is not limited to after formation of the island-shaped oxide semiconductor layer 108 , and the oxide semiconductor film before being processed into the island-shaped oxide semiconductor layer 108 may be subjected to the heat treatment.
  • the heat treatment may be performed more than once after the oxide semiconductor film 107 is formed.
  • heat treatment is performed for 60 minutes in the atmosphere in the state where the substrate temperature reaches 350° C.
  • rapid heating such as gas rapid thermal annealing (GRTA) using a heated gas or lamp rapid thermal annealing (LRTA) using lamp light, or the like can be used for the heat treatment.
  • GRTA gas rapid thermal annealing
  • LRTA lamp rapid thermal annealing
  • the temperature rise characteristics are preferably set at higher than or equal to 0.1° C./min and lower than or equal to 20° C./min and the temperature drop characteristics are preferably set at higher than or equal to 0.1° C./min and lower than or equal to 15° C./min.
  • the island-shaped oxide semiconductor layer 108 which has been subjected to the heat treatment in an inert gas atmosphere is preferably in an amorphous state, but may be partly crystallized.
  • plasma treatment using oxygen, ozone, or dinitrogen monoxide may be performed on an exposed surface of the oxide semiconductor layer 108 .
  • oxygen can be supplied to defects of the oxide semiconductor layer 108 .
  • the gate insulating layer 110 is formed.
  • the gate insulating layer 110 can be formed in a manner similar to that of the insulating layer 104 .
  • a silicon oxide layer with a thickness of 200 nm is formed by RF sputtering using SiO 2 as a target and a rare gas such as argon and oxygen as gases to be supplied when the gate insulating layer 110 is formed.
  • FIG. 2C The structure obtained through the steps up to here is illustrated in FIG. 2C .
  • heat treatment may be performed.
  • the heat treatment is performed in the atmosphere or an inert gas atmosphere (nitrogen, helium, neon, argon, or the like).
  • the heat treatment is preferably performed at a temperature of greater than or equal to 200° C. and less than or equal to 400° C. In this embodiment, the heat treatment is preferably performed at 350° C. for 1 hour in the atmosphere.
  • RTA treatment for a short time at a high temperature may be performed in a similar manner to the heat treatment performed before forming the gate insulating layer 110 .
  • the timing of this heat treatment is not particularly limited as long as it is after the formation of the gate insulating layer 110 , and can be performed without increasing the number of manufacturing steps by doubling as another step such as a heat treatment for reducing the resistance of a transparent conductive film.
  • a conductive film serving as the gate electrode layer 112 is formed over the gate insulating layer 110 , and a third photolithography step and an etching step are performed, whereby the gate electrode layer 112 is formed.
  • the conductive film can have a structure similar to that of the source electrode layer 106 a and the drain electrode layer 106 b .
  • a titanium film with a thickness of 150 nm is formed by DC sputtering using a titanium target.
  • the gate electrode layer 112 is formed by performing the third photolithography step and the etching step.
  • FIG. 2D The structure obtained through the steps up to here is illustrated in FIG. 2D .
  • the semiconductor device of Embodiment 1 can be manufactured.
  • FIGS. 3A and 3B a semiconductor device which is another embodiment of the present invention is described with reference to FIGS. 3A and 3B .
  • FIG. 3A is a top view of a transistor 200 included in a semiconductor device.
  • FIG. 3B is a cross-sectional view taken along line A 2 -B 2 of FIG. 3A .
  • the transistor 200 include, over the substrate 102 , the insulating layer 104 , an oxide semiconductor layer 208 which forms a channel region, a source electrode layer 206 a and a drain electrode layer 206 b , a gate insulating layer 210 , and a gate electrode layer 212 .
  • the transistor 200 is a transistor having a top-gate structure, in which the gate electrode layer 212 overlaps with the oxide semiconductor layer 208 with the gate insulating layer 210 interposed therebetween. Further, the transistor 200 is a top-contact transistor including the oxide semiconductor layer 208 between the source and drain electrode layers 206 a and 206 b and the insulating layer 104 .
  • the oxide semiconductor layer 208 is subjected to heat treatment in order to remove the diffused hydrogen from the oxide semiconductor layer 208 .
  • manufacturing steps of the transistor are increased, manufacturing cost is increased and yield may be reduced.
  • an insulating layer in which the concentration of hydrogen is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 is used as the insulating layer 104 being in contact with the oxide semiconductor layer 208 , whereby diffusion of hydrogen in the oxide semiconductor layer 208 can be prevented and a transistor having favorable electric characteristics can be provided. Accordingly, a transistor having favorable electric characteristics can be provided without increasing the number of manufacturing steps of the transistor.
  • the concentration of hydrogen in the gate insulating layer 210 can be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • the concentration of hydrogen in each of the insulating layer 104 and the gate insulating layer 210 is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 , whereby diffusion of hydrogen in the oxide semiconductor layer 208 can be suppressed.
  • the substrate 102 in this embodiment is similar to the substrate 102 described in Embodiment 1.
  • the insulating layer 104 has a structure similar to that described in Embodiment 1.
  • the insulating layer 104 serves as a base to prevent diffusion of an impurity element from the substrate 102 and also serves as a base to prevent the substrate from being etched by etching in the manufacturing steps of the transistor.
  • the insulating layer 104 is formed with a single-layer structure using any of oxide insulating layers of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, hafnium oxide, aluminum oxide, tantalum oxide, and the like; or a stacked structure including two or more layers selected from these layers.
  • oxide insulating layers of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, hafnium oxide, aluminum oxide, tantalum oxide, and the like.
  • a stacked structure including two or more layers is adopted, an insulating layer being in contact with the substrate 102 is formed using a silicon nitride and the insulating layer 104 being in contact with the oxide semiconductor layer 108 is formed using the above-mentioned oxide insulating layer.
  • An oxide insulating layer in which the concentration of hydrogen is reduced is used as the insulating layer 104 being in contact with the oxide semiconductor layer 208 , whereby, oxygen is supplied to defects of the oxide semiconductor layer 208 from the insulating layer 104 .
  • a transistor having favorable electric characteristics can be provided.
  • the concentration of hydrogen in the insulating layer 104 be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • a silicon oxide layer formed by sputtering or a silicon oxide layer formed by plasma CVD can be used as described in Embodiment 1.
  • a target containing a silicon element is preferably used. That is to say, a Si target or SiO 2 target can be used.
  • a SiO 2 target is used in order to reduce the concentration of hydrogen in the obtained oxide silicon layer; more preferably a SiO 2 target in which the concentration of a hydroxyl group contained in the SiO 2 target is less than or equal to 1000 ppm or the concentration of hydrogen measured using secondary ion mass spectrometry (SIMS) is less than or equal to 3.5 ⁇ 10 19 atoms/cm 3 is used.
  • gases to be supplied for forming the insulating layer 104 a rare gas such as argon and oxygen are used. Further, it is preferable to use high-purity gas in which impurities such as hydrogen, water, a hydroxyl group, or hydride are reduced to a concentration of a “ppm” level or a “ppb” level as gases to be supplied.
  • the insulating layer 104 can be formed by plasma CVD instead of sputtering.
  • Plasma CVD is a method for forming a film by supplying a deposition gas to be raw materials to a reaction chamber of a plasma CVD apparatus to employ plasma energy.
  • the oxide silicon layer is formed by plasma CVD, a gas in which hydrogen is not contained in its molecular structure as the deposition gas is needed to be selected.
  • the deposition gas not SiH 4 but SiF 4 is used. Further, as a gas for oxidation, N 2 O or O 2 with a low content of hydrogen and water is used. Further, a gas with a low content of hydrogen and water is used also as the other gases to be added (a rare gas such as argon) in consideration of the spread of plasma.
  • the silicon oxide layer is formed by plasma CVD using the gas having the above-described structure after impurities remaining in the reaction chamber or adsorbing onto the inner wall of the reaction chamber are removed.
  • the concentration of hydrogen in the insulating layer 104 formed by plasma CVD can be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • the oxide semiconductor layer 208 which forms a channel region is formed over the insulating layer 104 .
  • the oxide semiconductor layer 208 is similar to the oxide semiconductor layer 108 in Embodiment 1.
  • the concentration of hydrogen in the insulating layer 104 is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 , whereby diffusion of hydrogen in the oxide semiconductor layer 208 is prevented when the oxide semiconductor layer 208 is formed.
  • the gate insulating layer 210 is formed so as to cover the source electrode layer 206 a , the drain electrode layer 206 b , and the oxide semiconductor layer 208 .
  • the gate insulating layer 210 is similar to the gate insulating layer 110 in Embodiment 1. Further, an oxide insulating layer with a low hydrogen content, similarly to the insulating layer 104 , is used as the gate insulating layer 210 , whereby a semiconductor device having favorable electric characteristics can be obtained.
  • the concentration of hydrogen in the gate insulating layer being in contact with the oxide semiconductor layer be less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 .
  • the source electrode layer 206 a and the drain electrode layer 206 b are formed over part of the upper surface of the insulating layer 104 and part of the upper surface of the oxide semiconductor layer 208 .
  • the source electrode layer 206 a and the drain electrode layer 206 b are similar to the source electrode layer 106 a and the drain electrode layer 106 b in Embodiment 1.
  • the gate electrode 212 is formed so as to overlap with the oxide semiconductor layer 208 with the gate insulating layer 210 interposed therebetween.
  • the gate electrode 212 is similar to the gate electrode 112 in Embodiment 1.
  • an insulating layer serving as a passivation layer or an interlayer insulating layer is preferably formed over the transistor 200 .
  • the concentration of hydrogen in the insulating layer 104 and the gate insulating layer 210 is less than 6 ⁇ 10 20 atoms/cm 3 , preferably less than or equal to 5 ⁇ 10 20 atoms/cm 3 , more preferably less than or equal to 5 ⁇ 10 19 atoms/cm 3 , whereby diffusion of hydrogen in the oxide semiconductor layer 208 can be prevented and a semiconductor device having favorable electric characteristics can be obtained.
  • Embodiment 3 a method for manufacturing the semiconductor device illustrated in Embodiment 3 is described with reference to FIGS. 4A to 4D .
  • the insulating layer 104 is formed over the substrate 102 .
  • the substrate 102 and the insulating layer 104 illustrated in Embodiment 3 can be used.
  • a glass substrate is used for the substrate 102 .
  • the insulating layer 104 a silicon oxide layer with a thickness of 200 nm is formed by RF sputtering using SiO 2 as a target and a rare gas such as argon and oxygen as gases to be supplied when the insulating layer 104 is formed.
  • the insulating layer 104 can be formed as described in Embodiment 2 when it is formed by plasma CVD,
  • an oxide semiconductor film with a thickness of 50 nm is formed by sputtering. Because the oxide semiconductor film is formed to be in contact with the insulating layer 104 , oxygen is supplied to defects in the oxide semiconductor layer from the insulating layer 104 . After that, the oxide semiconductor layer 207 that is processed into an island shape is formed by performing the first photolithography step or the etching step.
  • the oxide semiconductor film can be formed as described in Embodiment 2.
  • FIG. 4A The structure obtained through the steps up to here is illustrated in FIG. 4A .
  • the conductive film serving as the source electrode layer 206 a and the drain electrode layer 206 b is formed.
  • a titanium film with a thickness of 150 nm is formed by DC sputtering using a titanium target as in Embodiment 2.
  • the source electrode layer 206 a and the drain electrode layer 206 b each having a thickness of 150 nm are formed by performing a second photolithography step and an etching step.
  • Etching of the conductive film can be performed in a similar manner to that described in Embodiment 2.
  • the oxide semiconductor layer 207 may be subjected to heat treatment in the atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, or the like), or in the atmosphere where the dew point under atmospheric pressure is less than or equal to ⁇ 60° C. and the moisture content is small.
  • the oxide semiconductor layer 207 is subjected to heat treatment in the atmosphere at greater than or equal to 100° C. and less than or equal to 400° C. for 10 minutes or more, preferably at 350° C. for 60 minutes.
  • the oxide semiconductor layer 207 is subjected to heat treatment, whereby the oxide semiconductor layer 208 in which moisture and hydrogen are eliminated is formed. At that time, oxygen is supplied to defects in the oxide semiconductor layer 208 from the insulating layer 104 .
  • the heat treatment is not necessarily performed after the source electrode layer 206 a and the drain electrode layer 206 b are formed, and the heat treatment may be performed on the island-shaped oxide semiconductor film 207 formed by performing the first photolithography step and the etching step before forming the source electrode layer 206 a and the drain electrode layer 206 b .
  • the heat treatment may also be performed plural times after forming the oxide semiconductor layer 207 .
  • heat treatment is performed at 350° C. for 60 minutes in the atmosphere in the state where the substrate temperature reaches 350° C.
  • plasma treatment using oxygen, ozone, or dinitrogen monoxide may be performed on an exposed surface of the oxide semiconductor layer 208 .
  • oxygen can be supplied to defects in the oxide semiconductor layer 208 .
  • the gate insulating layer 210 is formed.
  • the gate insulating layer 210 can be formed in a manner similar to that of the gate insulating layer 104 .
  • a silicon oxide layer with a thickness of 200 nm is formed by RF sputtering using SiO 2 as a target and a rare gas such as argon and oxygen as gases to be supplied when the gate insulating layer 210 is formed.
  • FIG. 4C The structure obtained through the steps up to here is illustrated in FIG. 4C .
  • heat treatment may be performed.
  • the heat treatment can be performed by a method which is similar to that in Embodiment 2, and the heat treatment can also be performed at the timing which is the same as the timing described in Embodiment 2.
  • a conductive film serving as the gate electrode layer 212 is formed over the gate insulating layer 210 . Then, the gate electrode layer 212 is formed by performing the third photolithography step or the etching step.
  • the conductive film can have a structure similar to that of the source electrode layer 206 a and the drain electrode layer 206 b .
  • a titanium film with a thickness of 150 nm is formed by DC sputtering using a titanium target as in Embodiment 2. Then, the gate electrode layer 212 is formed by performing the third photolithography step and the etching step.
  • FIG. 4D The structure obtained through the steps up to here is illustrated in FIG. 4D .
  • Embodiment 3 a semiconductor device illustrated in Embodiment 3 can be manufactured.
  • the transistor described in the above embodiments is manufactured, and a semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistor for a pixel portion and further for a driver circuit. Further, part of or the entire driver circuit including the transistors can be formed over a substrate where the pixel portion is formed; thus, a system-on-panel can be obtained. Further, a semiconductor device including a memory cell can be manufactured using the transistors in which the oxide semiconductor described in the above embodiments is used.
  • the display device includes a display element.
  • a liquid crystal element also referred to as a liquid crystal display element
  • a light-emitting element also referred to as a light-emitting display element
  • the light-emitting element includes, in its category, an element whose luminance is controlled by a current or a voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like.
  • EL inorganic electroluminescent
  • a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.
  • the display device includes a panel in which the display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel.
  • an element substrate which corresponds to one embodiment before the display element is completed in a manufacturing process of the display device, is provided with a means for supplying current to the display element in each of a plurality of pixels.
  • the element substrate may be in a state where only a pixel electrode of the display element is formed, a state where a conductive film to be a pixel electrode is formed but is not etched yet to form the pixel electrode, or any other states.
  • a display device in this specification means an image display device, a display device, or a light source (including a lighting device).
  • the “display device” includes the following modules in its category: a module including a connector such as a flexible printed circuit (FPC), a tape automated bonding (TAB) tape, or a tape carrier package (TCP) attached; a module having a TAB tape or a TCP which is provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) which is directly mounted on a display element by a chip on glass (COG) method.
  • FPC flexible printed circuit
  • TAB tape automated bonding
  • TCP tape carrier package
  • COG chip on glass
  • a display device using the transistor described in the above embodiments can be used for an electronic paper in which electronic ink is driven to perform display.
  • An electronic paper can be used for electronic devices of a variety of fields as long as they can display data.
  • electronic paper can be applied to an electronic book reader (e-book), a poster, a digital signage, a public information display (PID), an advertisement in a vehicle such as a train, displays of various cards such as a credit card, and the like.
  • An example of the electronic device is illustrated in FIG. 5 .
  • FIG. 5 illustrates an e-book reader 2700 as an example the electronic device.
  • the e-book reader 2700 includes two housings, a housing 2701 and a housing 2703 .
  • the housing 2701 and the housing 2703 are combined with a hinge 2711 so that the e-book reader 2700 can be opened and closed with the hinge 2711 as an axis.
  • the e-book reader 2700 can operate like a paper book.
  • a display portion 2705 and a photoelectric conversion device 2706 are incorporated in the housing 2701 .
  • a display portion 2707 and a photoelectric conversion device 2708 are incorporated in the housing 2703 .
  • the display portion 2705 and the display portion 2707 may display one image or different images. In the case where the display portion 2705 and the display portion 2707 display different images, for example, text can be displayed on a display portion on the right side (the display portion 2705 in FIG. 5 ) and graphics can be displayed on a display portion on the left side (the display portion 2707 in FIG. 5 ).
  • FIG. 5 illustrates an example in which the housing 2701 is provided with an operation portion and the like.
  • the housing 2701 is provided with a power switch 2721 , an operation key 2723 , a speaker 2725 , and the like.
  • the operation key 2723 pages can be turned.
  • a keyboard, a pointing device, or the like may also be provided on the surface of the housing, on which the display portion is provided.
  • an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing.
  • the e-book reader 2700 may have a function of an electronic dictionary.
  • the e-book reader 2700 may have a configuration capable of wirelessly transmitting and receiving data. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.
  • a semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines).
  • electronic devices are a television device (also referred to as a television or a television receiver), a monitor of a computer or the like, electronic paper, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile telephone or a mobile phone device), a portable game console, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like.
  • FIG. 6A illustrates a television set 9600 as an example of an electronic device.
  • a display portion 9603 is incorporated in a housing 9601 .
  • the display portion 9603 can display images.
  • the housing 9601 is supported by a stand 9605 .
  • the television set 9600 can be operated with an operation switch of the housing 9601 or a separate remote controller 9610 .
  • Channels and volume can be controlled with an operation key 9609 of the remote controller 9610 so that an image displayed on the display portion 9603 can be controlled.
  • the remote controller 9610 may be provided with a display portion 9607 for displaying data output from the remote controller 9610 .
  • the television set 9600 is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. Moreover, when the display device is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed.
  • FIG. 6B illustrates a digital photo frame 9700 as an example of an electronic device.
  • a display portion 9703 is incorporated in a housing 9701 .
  • the display portion 9703 can display a variety of images.
  • the display portion 9703 can display data of an image taken with a digital camera or the like and function as a normal photo frame.
  • the digital photo frame 9700 is provided with an operation portion, an external connection portion (a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like), a recording medium insertion portion, and the like.
  • an operation portion a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like
  • a recording medium insertion portion a recording medium insertion portion, and the like.
  • these components may be provided on the surface on which the display portion is provided, it is preferable to provide them on the side surface or the back surface for the design of the digital photo frame 9700 .
  • a memory storing data of an image taken with a digital camera is inserted in the recording medium insertion portion of the digital photo frame, whereby the image data can be transferred and then displayed on the display portion 9703 .
  • the digital photo frame 9700 may be configured to transmit and receive data wirelessly.
  • the structure may be employed in which desired image data is transferred wirelessly to be displayed.
  • FIG. 7 is a perspective view illustrating an example of a portable computer.
  • a top housing 9301 having a display portion 9303 and a bottom housing 9302 having a keyboard 9304 can overlap with each other by closing a hinge unit which connects the top housing 9301 and the bottom housing 9302 .
  • the portable computer illustrated in FIG. 7 is conveniently carried.
  • the hinge unit is opened so that a user can input data looking at the display portion 9303 .
  • the bottom housing 9302 includes a pointing device 9306 with which input can be performed, in addition to the keyboard 9304 . Further, when the display portion 9303 is a touch input panel, input can be performed by touching part of the display portion.
  • the bottom housing 9302 includes an arithmetic function portion such as a CPU or hard disk.
  • the bottom housing 9302 includes an external connection port 9305 into which another device such as a communication cable conformable to communication standards of a USB is inserted.
  • the top housing 9301 includes a display portion 9307 and can keep the display portion 9307 therein by sliding it toward the inside of the top housing 9301 ; thus, the top housing 9301 can have a large display screen.
  • the user can adjust the orientation of a screen of the display portion 9307 which can be kept in the top housing 9301 .
  • the display portion 9307 which can be kept in the top housing 9301 is a touch input panel, input can be performed by touching part of the display portion 9307 which can be kept in the top housing 9301 .
  • the display portion 9303 or the display portion 9307 which can be kept in the top housing 9301 are formed with an image display device of a liquid crystal display panel, a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element, or the like.
  • the portable computer in FIG. 7 which can be provided with a receiver and the like, can receive a television broadcast to display an image on the display portion 9303 or the display portion 9307 .
  • the user can watch television broadcast when the whole screen of the display portion 9307 is exposed by sliding the display portion 9307 while the hinge unit which connects the top housing 9301 and the bottom housing 9302 is kept closed. In this case, the hinge unit is not opened and display is not performed on the display portion 9303 .
  • start up of only a circuit for displaying television broadcast is performed. Therefore, power can be consumed to the minimum, which is useful for the portable computer whose battery capacity is limited.
  • the concentration of hydrogen included in the following insulating layers A and B is illustrated with reference to FIG. 8 .
  • the insulating layer A was formed by sputtering using SiO 2 as a target and the insulating layer B was formed by plasma CVD using SiH 4 as a deposition gas.
  • a method for manufacturing samples is described.
  • a silicon oxide layer with a thickness of 200 nm was formed over a silicon substrate by RF sputtering under the following conditions: SiO 2 was used as a target; argon and oxygen were supplied at flow rates of 40 sccm and 10 sccm, respectively; and the power and the pressure were adjusted to 1.5 kW and 0.4 Pa, respectively.
  • the substrate temperature was 100° C.
  • the distance between electrodes in a sputtering apparatus was 60 mm.
  • a silicon oxynitride layer with a thickness of 100 nm was formed over a silicon substrate by plasma CVD in which plasma discharge was performed under the following conditions: SiH 4 as a deposigion gas and N 2 O as an oxynitride gas were supplied with flow rates of 4 sccm and 800 sccm, respectively to gain stability; the pressure in the treatment chamber was 40 Pa; RF power source frequency was 27 MHz; and the power of the RF power source was 50 W. At that time, the substrate temperature was 400° C., and the distance between electrodes in a plasma CVD apparatus was 15 mm.
  • FIG. 8 SIMS measurement results of the insulating layers A and B are shown in FIG. 8 .
  • the vertical axis represents the concentration of hydrogen in the insulating layers A and B
  • the horizontal axis represents the depth in a direction of the substrate from the surfaces of the insulating layers A and B.
  • the solid line shows a concentration profile of the insulating layer A
  • the broken line shows a concentration profile of the insulating layer B.
  • the horizontal axis corresponding to 70 nm to 120 nm represents a quantitative range and the horizontal axis corresponding to 200 nm or more represents the silicon substrate.
  • the horizontal axis corresponding to 10 nm to 60 nm represents a quantitative range and the horizontal axis corresponding to 100 nm or more represents the silicon substrate.
  • the quantitative range in this example means a range where high reliability is obtained with the SIMS measurement results (concentration of hydrogen).
  • the measurement results (concentration of hydrogen) in each quantitative range in insulating layers A and B represent the concentration of hydrogen included in each of the insulating layers A and B.
  • the concentration of hydrogen in the insulating layer A was greater than or equal to 4.9 ⁇ 10 19 atoms/cm 3 and less than or equal to 5.2 ⁇ 10 19 atoms/cm 3
  • the concentration of hydrogen in the insulating layer B was greater than or equal to 6.4 ⁇ 10 20 atoms/cm 3 and less than or equal to 9.6 ⁇ 10 20 atoms/cm 3 .
  • the silicon oxide layer in which diffusion of hydrogen was suppressed was formed because the insulating layer A was formed by sputtering using SiO 2 as the target while being supplied with argon and oxygen. Also, it was found that hydrogen was diffused in the silicon oxynitride layer because the insulating layer B was formed using SiH 4 as the deposition gas.
  • Example A in the top-gate/top-contact transistors described in Embodiment 1, electric characteristics of the following transistors (sample A and sample B) illustrated in Example 1 is described.
  • the transistor (sample A) was formed using silicon oxide of the insulating layer A described in Example 1, and the transistor (sample B) was formed using silicon oxynitride of the insulating layer B described in Example 1.
  • the other structures of the transistors are the same in the sample A and the sample B.
  • a glass substrate (EAGLE XG-2000 manufactured by Corning Incorporated) was used as the substrate 102 .
  • the insulating layer 104 was formed over the substrate 102 .
  • the insulating layer 104 in each of the samples A and B was formed to have a thickness of 200 nm and formed by the method described in Example 1.
  • the conductive film serving as the source electrode layer 106 a and the drain electrode layer 106 b were formed.
  • a titanium film with a thickness of 150 nm was formed by DC sputtering as follows: a titanium target was used; argon with a flow rate of 20 sccm was supplied; and the power and the pressure were adjusted to 12 kW and 0.1 Pa, respectively.
  • the substrate temperature was room temperature (15° C. to 35° C.), and the distance between electrodes in a sputtering apparatus was 400 mm.
  • ICP inductively coupled plasma
  • the oxide semiconductor film was formed with a thickness of 50 nm over the insulating layer 104 , the source electrode layer 106 a , and the drain electrode layer 106 b .
  • the oxide semiconductor film containing indium (In), gallium (Ga), zinc (Zn), and oxygen atoms was formed by DC sputtering without heating the substrate.
  • the gate insulating layer 110 was formed over the island-shaped oxide semiconductor layer 108 .
  • a silicon oxide layer with a thickness of 200 nm was formed by RF sputtering under the following conditions: SiO 2 was used as a target; argon with a flow rate of 25 sccm and oxygen with a flow rate of 25 sccm were supplied; and the power and the pressure were adjusted to 1.5 kW and 0.4 Pa, respectively.
  • the substrate temperature was 100° C.
  • the distance between electrodes in the sputtering apparatus was 60 mm.
  • the structure obtained through the steps up to here is illustrated in FIG. 2C .
  • a conductive film serving as the gate electrode layer 112 was formed after performing heat treatment at 350° C. for 60 minutes in the atmosphere.
  • a titanium film with a thickness of 150 nm was formed by DC sputtering as follows: a titanium target was used; argon with a flow rate of 20 sccm was supplied; and the power and the pressure were adjusted to 12 kW and 0.1 Pa, respectively.
  • the substrate temperature was room temperature (15° C. to 35° C.), and the distance between electrodes in the sputtering apparatus was 400 mm.
  • the measurement result of the samples A and B is shown in FIG. 9 .
  • the solid line shows current-voltage characteristics and field-effect mobility of the sample A when the drain voltage was 10 V
  • the broken line shows current-voltage characteristics and field-effect mobility of the sample B when the drain voltage was 10 V.
  • the transistor of this example was formed so as to have a channel length of 3.0 ⁇ m and a channel width of 10 ⁇ m.
  • the defect was caused in the sample B in which the concentration of hydrogen in the insulating layer was greater than or equal to 6 ⁇ 10 20 atoms/cm 3 because hydrogen was diffused into the oxide semiconductor layer including the channel region in the manufacturing steps of the transistor.
  • the sample A in which the concentration of hydrogen in the insulating layer was less than 6 ⁇ 10 20 atoms/cm 3 had favorable electric characteristics because diffusion of hydrogen in the oxide semiconductor layer including the channel region was prevented in the manufacturing steps of the transistor.
  • the transistor having favorable electric characteristics can be provided by setting the concentration of hydrogen in the insulating layer to less than 6 ⁇ 10 20 atoms/cm 3 .

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US10192995B2 (en) 2015-04-28 2019-01-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US10254608B2 (en) 2015-08-21 2019-04-09 Samsung Display Co., Ltd. Display device
US20190348538A1 (en) * 2015-03-03 2019-11-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, method for manufacturing the same, or display device including the same

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Citations (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198861A (ja) 1984-03-23 1985-10-08 Fujitsu Ltd 薄膜トランジスタ
JPS63210024A (ja) 1987-02-24 1988-08-31 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓５Ｏ↓８で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63210022A (ja) 1987-02-24 1988-08-31 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓３Ｏ↓６で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63210023A (ja) 1987-02-24 1988-08-31 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓４Ｏ↓７で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63215519A (ja) 1987-02-27 1988-09-08 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓６Ｏ↓９で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63239117A (ja) 1987-01-28 1988-10-05 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓２Ｏ↓５で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63265818A (ja) 1987-04-22 1988-11-02 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓７Ｏ↓１↓０で示される六方晶系の層状構造を有する化合物およびその製造法
JPH05251705A (ja) 1992-03-04 1993-09-28 Fuji Xerox Co Ltd 薄膜トランジスタ
JPH08264794A (ja) 1995-03-27 1996-10-11 Res Dev Corp Of Japan 亜酸化銅等の金属酸化物半導体による薄膜トランジスタとｐｎ接合を形成した金属酸化物半導体装置およびそれらの製造方法
US5731856A (en) 1995-12-30 1998-03-24 Samsung Electronics Co., Ltd. Methods for forming liquid crystal displays including thin film transistors and gate pads having a particular structure
US5744864A (en) 1995-08-03 1998-04-28 U.S. Philips Corporation Semiconductor device having a transparent switching element
JP2000044236A (ja) 1998-07-24 2000-02-15 Hoya Corp 透明導電性酸化物薄膜を有する物品及びその製造方法
JP2000150900A (ja) 1998-11-17 2000-05-30 Japan Science & Technology Corp トランジスタ及び半導体装置
US6294274B1 (en) 1998-11-16 2001-09-25 Tdk Corporation Oxide thin film
US20010046027A1 (en) 1999-09-03 2001-11-29 Ya-Hsiang Tai Liquid crystal display having stripe-shaped common electrodes formed above plate-shaped pixel electrodes
JP2002076356A (ja) 2000-09-01 2002-03-15 Japan Science & Technology Corp 半導体デバイス
JP2002075987A (ja) 2000-08-25 2002-03-15 Toyota Central Res & Dev Lab Inc 半導体装置の製造方法
US20020039814A1 (en) * 2000-09-29 2002-04-04 Norio Jada Flat panel display device and method for manufacturing the same
US20020056838A1 (en) 2000-11-15 2002-05-16 Matsushita Electric Industrial Co., Ltd. Thin film transistor array, method of producing the same, and display panel using the same
US6448577B1 (en) * 1990-10-15 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with grain boundaries
US20020132454A1 (en) 2001-03-19 2002-09-19 Fuji Xerox Co., Ltd. Method of forming crystalline semiconductor thin film on base substrate, lamination formed with crystalline semiconductor thin film and color filter
JP2002289859A (ja) 2001-03-23 2002-10-04 Minolta Co Ltd 薄膜トランジスタ
JP2003086000A (ja) 2001-09-10 2003-03-20 Sharp Corp 半導体記憶装置およびその試験方法
JP2003086808A (ja) 2001-09-10 2003-03-20 Masashi Kawasaki 薄膜トランジスタおよびマトリクス表示装置
US20030189401A1 (en) 2002-03-26 2003-10-09 International Manufacturing And Engineering Services Co., Ltd. Organic electroluminescent device
US20030218222A1 (en) 2002-05-21 2003-11-27 The State Of Oregon Acting And Through The Oregon State Board Of Higher Education On Behalf Of Transistor structures and methods for making the same
US20040038446A1 (en) 2002-03-15 2004-02-26 Sanyo Electric Co., Ltd.- Method for forming ZnO film, method for forming ZnO semiconductor layer, method for fabricating semiconductor device, and semiconductor device
JP2004103957A (ja) 2002-09-11 2004-04-02 Japan Science & Technology Corp ホモロガス薄膜を活性層として用いる透明薄膜電界効果型トランジスタ
US20040127038A1 (en) 2002-10-11 2004-07-01 Carcia Peter Francis Transparent oxide semiconductor thin film transistors
JP2004273614A (ja) 2003-03-06 2004-09-30 Sharp Corp 半導体装置およびその製造方法
JP2004273732A (ja) 2003-03-07 2004-09-30 Sharp Corp アクティブマトリクス基板およびその製造方法
WO2004114391A1 (ja) 2003-06-20 2004-12-29 Sharp Kabushiki Kaisha 半導体装置およびその製造方法ならびに電子デバイス
US20050017302A1 (en) 2003-07-25 2005-01-27 Randy Hoffman Transistor including a deposited channel region having a doped portion
US20050199959A1 (en) 2004-03-12 2005-09-15 Chiang Hai Q. Semiconductor device
JP2005285975A (ja) 2004-03-29 2005-10-13 Seiko Epson Corp 半導体装置及びその製造方法、電気光学装置並びに電子機器
US20060043377A1 (en) 2004-03-12 2006-03-02 Hewlett-Packard Development Company, L.P. Semiconductor device
US20060091793A1 (en) 2004-11-02 2006-05-04 3M Innovative Properties Company Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes
US20060110867A1 (en) 2004-11-10 2006-05-25 Canon Kabushiki Kaisha Field effect transistor manufacturing method
US20060108529A1 (en) 2004-11-10 2006-05-25 Canon Kabushiki Kaisha Sensor and image pickup device
US20060108636A1 (en) 2004-11-10 2006-05-25 Canon Kabushiki Kaisha Amorphous oxide and field effect transistor
US20060113549A1 (en) 2004-11-10 2006-06-01 Canon Kabushiki Kaisha Light-emitting device
US20060113536A1 (en) 2004-11-10 2006-06-01 Canon Kabushiki Kaisha Display
US20060113539A1 (en) 2004-11-10 2006-06-01 Canon Kabushiki Kaisha Field effect transistor
US20060113565A1 (en) 2004-11-10 2006-06-01 Canon Kabushiki Kaisha Electric elements and circuits utilizing amorphous oxides
US20060118166A1 (en) 2004-12-06 2006-06-08 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion element, solar battery, and photo sensor
US7061014B2 (en) 2001-11-05 2006-06-13 Japan Science And Technology Agency Natural-superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film
JP2006165527A (ja) 2004-11-10 2006-06-22 Canon Inc 電界効果型トランジスタ
JP2006165529A (ja) 2004-11-10 2006-06-22 Canon Inc 非晶質酸化物、及び電界効果型トランジスタ
US20060169973A1 (en) 2005-01-28 2006-08-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and method of manufacturing semiconductor device
US20060170111A1 (en) 2005-01-28 2006-08-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and method of manufacturing semiconductor device
US20060197092A1 (en) 2005-03-03 2006-09-07 Randy Hoffman System and method for forming conductive material on a substrate
US7105868B2 (en) 2002-06-24 2006-09-12 Cermet, Inc. High-electron mobility transistor with zinc oxide
US20060208977A1 (en) 2005-03-18 2006-09-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and display device, driving method and electronic apparatus thereof
US20060228974A1 (en) 2005-03-31 2006-10-12 Theiss Steven D Methods of making displays
US20060231882A1 (en) 2005-03-28 2006-10-19 Il-Doo Kim Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications
US20060238135A1 (en) 2005-04-20 2006-10-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
US20060246738A1 (en) 2005-04-28 2006-11-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP2006332634A (ja) 2005-04-28 2006-12-07 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US20060284171A1 (en) 2005-06-16 2006-12-21 Levy David H Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US20060284172A1 (en) 2005-06-10 2006-12-21 Casio Computer Co., Ltd. Thin film transistor having oxide semiconductor layer and manufacturing method thereof
EP1737044A1 (en) 2004-03-12 2006-12-27 Japan Science and Technology Agency Amorphous oxide and thin film transistor
US20060292777A1 (en) 2005-06-27 2006-12-28 3M Innovative Properties Company Method for making electronic devices using metal oxide nanoparticles
US20070024187A1 (en) 2005-07-28 2007-02-01 Shin Hyun S Organic light emitting display (OLED) and its method of fabrication
US20070046191A1 (en) 2005-08-23 2007-03-01 Canon Kabushiki Kaisha Organic electroluminescent display device and manufacturing method thereof
US20070054507A1 (en) 2005-09-06 2007-03-08 Canon Kabushiki Kaisha Method of fabricating oxide semiconductor device
US20070052025A1 (en) 2005-09-06 2007-03-08 Canon Kabushiki Kaisha Oxide semiconductor thin film transistor and method of manufacturing the same
JP2007096055A (ja) 2005-09-29 2007-04-12 Semiconductor Energy Lab Co Ltd 半導体装置、及び半導体装置の作製方法
US20070090365A1 (en) 2005-10-20 2007-04-26 Canon Kabushiki Kaisha Field-effect transistor including transparent oxide and light-shielding member, and display utilizing the transistor
US7211825B2 (en) 2004-06-14 2007-05-01 Yi-Chi Shih Indium oxide-based thin film transistors and circuits
US20070108446A1 (en) 2005-11-15 2007-05-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070152217A1 (en) 2005-12-29 2007-07-05 Chih-Ming Lai Pixel structure of active matrix organic light-emitting diode and method for fabricating the same
US20070172591A1 (en) 2006-01-21 2007-07-26 Samsung Electronics Co., Ltd. METHOD OF FABRICATING ZnO FILM AND THIN FILM TRANSISTOR ADOPTING THE ZnO FILM
US20070187760A1 (en) 2006-02-02 2007-08-16 Kochi Industrial Promotion Center Thin film transistor including low resistance conductive thin films and manufacturing method thereof
US20070187678A1 (en) 2006-02-15 2007-08-16 Kochi Industrial Promotion Center Semiconductor device including active layer made of zinc oxide with controlled orientations and manufacturing method thereof
US20070252928A1 (en) 2006-04-28 2007-11-01 Toppan Printing Co., Ltd. Structure, transmission type liquid crystal display, reflection type display and manufacturing method thereof
US7297977B2 (en) 2004-03-12 2007-11-20 Hewlett-Packard Development Company, L.P. Semiconductor device
US20070272922A1 (en) 2006-04-11 2007-11-29 Samsung Electronics Co. Ltd. ZnO thin film transistor and method of forming the same
WO2007138937A1 (en) 2006-05-26 2007-12-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7307279B2 (en) * 2001-10-30 2007-12-11 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US20070287296A1 (en) 2006-06-13 2007-12-13 Canon Kabushiki Kaisha Dry etching method for oxide semiconductor film
JP2008004929A (ja) 2006-05-26 2008-01-10 Semiconductor Energy Lab Co Ltd 不揮発性半導体記憶装置及びその作製方法、半導体装置及びその作製方法、並びに絶縁膜の作製方法
US20080006877A1 (en) 2004-09-17 2008-01-10 Peter Mardilovich Method of Forming a Solution Processed Device
US7323356B2 (en) 2002-02-21 2008-01-29 Japan Science And Technology Agency LnCuO(S,Se,Te)monocrystalline thin film, its manufacturing method, and optical device or electronic device using the monocrystalline thin film
US20080038929A1 (en) 2006-08-09 2008-02-14 Canon Kabushiki Kaisha Method of dry etching oxide semiconductor film
US20080038882A1 (en) 2006-08-09 2008-02-14 Kazushige Takechi Thin-film device and method of fabricating the same
US20080050595A1 (en) 2006-01-11 2008-02-28 Murata Manufacturing Co., Ltd. Transparent conductive film and method for manufacturing the same
US20080073653A1 (en) 2006-09-27 2008-03-27 Canon Kabushiki Kaisha Semiconductor apparatus and method of manufacturing the same
US20080083950A1 (en) 2006-10-10 2008-04-10 Alfred I-Tsung Pan Fused nanocrystal thin film semiconductor and method
US20080106191A1 (en) 2006-09-27 2008-05-08 Seiko Epson Corporation Electronic device, organic electroluminescence device, and organic thin film semiconductor device
US20080128689A1 (en) 2006-11-29 2008-06-05 Je-Hun Lee Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays
US20080129195A1 (en) 2006-12-04 2008-06-05 Toppan Printing Co., Ltd. Color el display and method for producing the same
US7385224B2 (en) 2004-09-02 2008-06-10 Casio Computer Co., Ltd. Thin film transistor having an etching protection film and manufacturing method thereof
WO2008069286A2 (en) 2006-12-05 2008-06-12 Canon Kabushiki Kaisha Display apparatus using oxide semiconductor and production method thereof
US20080166834A1 (en) 2007-01-05 2008-07-10 Samsung Electronics Co., Ltd. Thin film etching method
US7402506B2 (en) 2005-06-16 2008-07-22 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US20080182358A1 (en) 2007-01-26 2008-07-31 Cowdery-Corvan Peter J Process for atomic layer deposition
US7411209B2 (en) 2006-09-15 2008-08-12 Canon Kabushiki Kaisha Field-effect transistor and method for manufacturing the same
JP2007123861A5 (ja) 2006-09-27 2008-09-18
US20080224133A1 (en) 2007-03-14 2008-09-18 Jin-Seong Park Thin film transistor and organic light-emitting display device having the thin film transistor
EP1983566A2 (en) 2007-04-20 2008-10-22 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
US20080258143A1 (en) 2007-04-18 2008-10-23 Samsung Electronics Co., Ltd. Thin film transitor substrate and method of manufacturing the same
US20080258141A1 (en) 2007-04-19 2008-10-23 Samsung Electronics Co., Ltd. Thin film transistor, method of manufacturing the same, and flat panel display having the same
US20080258139A1 (en) 2007-04-17 2008-10-23 Toppan Printing Co., Ltd. Structure with transistor
US20080258140A1 (en) 2007-04-20 2008-10-23 Samsung Electronics Co., Ltd. Thin film transistor including selectively crystallized channel layer and method of manufacturing the thin film transistor
US7453087B2 (en) * 2005-09-06 2008-11-18 Canon Kabushiki Kaisha Thin-film transistor and thin-film diode having amorphous-oxide semiconductor layer
US20080296567A1 (en) * 2007-06-04 2008-12-04 Irving Lyn M Method of making thin film transistors comprising zinc-oxide-based semiconductor materials
US20080296568A1 (en) 2007-05-29 2008-12-04 Samsung Electronics Co., Ltd Thin film transistors and methods of manufacturing the same
US7501293B2 (en) 2002-06-13 2009-03-10 Murata Manufacturing Co., Ltd. Semiconductor device in which zinc oxide is used as a semiconductor material and method for manufacturing the semiconductor device
US20090065771A1 (en) * 2006-03-17 2009-03-12 Canon Kabushiki Kaisha Field effect transistor using oxide film for channel and method of manufacturing the same
US20090073325A1 (en) 2005-01-21 2009-03-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same, and electric device
US20090114910A1 (en) 2005-09-06 2009-05-07 Canon Kabushiki Kaisha Semiconductor device
US20090134399A1 (en) 2005-02-18 2009-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Method for Manufacturing the Same
WO2009072532A1 (en) 2007-12-04 2009-06-11 Canon Kabushiki Kaisha Oxide semiconductor device including insulating layer and display apparatus using the same
US20090152506A1 (en) 2007-12-17 2009-06-18 Fujifilm Corporation Process for producing oriented inorganic crystalline film, and semiconductor device using the oriented inorganic crystalline film
US20090152541A1 (en) 2005-02-03 2009-06-18 Semiconductor Energy Laboratory Co., Ltd. Electronic device, semiconductor device and manufacturing method thereof
CN101464892A (zh) 2008-12-31 2009-06-24 中兴通讯股份有限公司 一种动态数据库的登录方法及装置
JP2009224479A (ja) 2008-03-14 2009-10-01 Fujifilm Corp 薄膜電界効果型トランジスタおよびその製造方法
US7642114B2 (en) 2006-07-19 2010-01-05 Semiconductor Energy Laboratory Co., Ltd. Micro electro mechanical device and manufacturing method thereof
US7674650B2 (en) 2005-09-29 2010-03-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20100065844A1 (en) 2008-09-18 2010-03-18 Sony Corporation Thin film transistor and method of manufacturing thin film transistor
US20100092800A1 (en) 2008-10-09 2010-04-15 Canon Kabushiki Kaisha Substrate for growing wurtzite type crystal and method for manufacturing the same and semiconductor device
US20100109002A1 (en) 2007-04-25 2010-05-06 Canon Kabushiki Kaisha Oxynitride semiconductor
US20100233847A1 (en) 2009-03-12 2010-09-16 Hiroki Ohara Method for manufacturing semiconductor device
US20110053322A1 (en) 2009-06-30 2011-03-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20110068336A1 (en) 2009-09-24 2011-03-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and method for manufacturing the same
US20110089416A1 (en) 2009-10-21 2011-04-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20110309355A1 (en) 2010-06-18 2011-12-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987102A (en) * 1989-12-04 1991-01-22 Motorola, Inc. Process for forming high purity thin films
JPH0529301A (ja) * 1991-07-23 1993-02-05 Seiko Epson Corp Ｃｖｄ法
JP3451380B2 (ja) * 1992-11-24 2003-09-29 東京エレクトロン株式会社 半導体装置の製造方法
TWI288443B (en) * 2002-05-17 2007-10-11 Semiconductor Energy Lab SiN film, semiconductor device, and the manufacturing method thereof
JP5126729B2 (ja) 2004-11-10 2013-01-23 キヤノン株式会社 画像表示装置
JP5064747B2 (ja) 2005-09-29 2012-10-31 株式会社半導体エネルギー研究所 半導体装置、電気泳動表示装置、表示モジュール、電子機器、及び半導体装置の作製方法
US8013331B2 (en) 2006-06-19 2011-09-06 Panasonic Corporation Thin film transistor, method of manufacturing the same, and electronic device using the same
US8809203B2 (en) * 2007-06-05 2014-08-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device using a microwave plasma CVD apparatus
US8049253B2 (en) * 2007-07-11 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5448100B2 (ja) 2008-01-14 2014-03-19 ヴォルテラ セミコンダクター コーポレイション 保護されたチャネルを有するパワートランジスタ
KR100963026B1 (ko) 2008-06-30 2010-06-10 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
JP2010040552A (ja) * 2008-07-31 2010-02-18 Idemitsu Kosan Co Ltd 薄膜トランジスタ及びその製造方法
KR101497425B1 (ko) * 2008-08-28 2015-03-03 삼성디스플레이 주식회사 액정 표시 장치 및 그 제조 방법
JP5537787B2 (ja) * 2008-09-01 2014-07-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5627071B2 (ja) 2008-09-01 2014-11-19 株式会社半導体エネルギー研究所 半導体装置の作製方法
WO2010047077A1 (ja) * 2008-10-23 2010-04-29 出光興産株式会社 薄膜トランジスタ及びその製造方法
WO2011145484A1 (en) * 2010-05-21 2011-11-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Patent Citations (176)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198861A (ja) 1984-03-23 1985-10-08 Fujitsu Ltd 薄膜トランジスタ
JPS63239117A (ja) 1987-01-28 1988-10-05 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓２Ｏ↓５で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63210024A (ja) 1987-02-24 1988-08-31 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓５Ｏ↓８で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63210022A (ja) 1987-02-24 1988-08-31 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓３Ｏ↓６で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63210023A (ja) 1987-02-24 1988-08-31 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓４Ｏ↓７で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63215519A (ja) 1987-02-27 1988-09-08 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓６Ｏ↓９で示される六方晶系の層状構造を有する化合物およびその製造法
JPS63265818A (ja) 1987-04-22 1988-11-02 Natl Inst For Res In Inorg Mater ＩｎＧａＺｎ↓７Ｏ↓１↓０で示される六方晶系の層状構造を有する化合物およびその製造法
US6448577B1 (en) * 1990-10-15 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with grain boundaries
JPH05251705A (ja) 1992-03-04 1993-09-28 Fuji Xerox Co Ltd 薄膜トランジスタ
JPH08264794A (ja) 1995-03-27 1996-10-11 Res Dev Corp Of Japan 亜酸化銅等の金属酸化物半導体による薄膜トランジスタとｐｎ接合を形成した金属酸化物半導体装置およびそれらの製造方法
US5744864A (en) 1995-08-03 1998-04-28 U.S. Philips Corporation Semiconductor device having a transparent switching element
JPH11505377A (ja) 1995-08-03 1999-05-18 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 半導体装置
US5731856A (en) 1995-12-30 1998-03-24 Samsung Electronics Co., Ltd. Methods for forming liquid crystal displays including thin film transistors and gate pads having a particular structure
JP2000044236A (ja) 1998-07-24 2000-02-15 Hoya Corp 透明導電性酸化物薄膜を有する物品及びその製造方法
US6294274B1 (en) 1998-11-16 2001-09-25 Tdk Corporation Oxide thin film
JP2000150900A (ja) 1998-11-17 2000-05-30 Japan Science & Technology Corp トランジスタ及び半導体装置
US7064346B2 (en) 1998-11-17 2006-06-20 Japan Science And Technology Agency Transistor and semiconductor device
US6727522B1 (en) 1998-11-17 2004-04-27 Japan Science And Technology Corporation Transistor and semiconductor device
US20010046027A1 (en) 1999-09-03 2001-11-29 Ya-Hsiang Tai Liquid crystal display having stripe-shaped common electrodes formed above plate-shaped pixel electrodes
JP2002075987A (ja) 2000-08-25 2002-03-15 Toyota Central Res & Dev Lab Inc 半導体装置の製造方法
JP2002076356A (ja) 2000-09-01 2002-03-15 Japan Science & Technology Corp 半導体デバイス
US20020039814A1 (en) * 2000-09-29 2002-04-04 Norio Jada Flat panel display device and method for manufacturing the same
US20020056838A1 (en) 2000-11-15 2002-05-16 Matsushita Electric Industrial Co., Ltd. Thin film transistor array, method of producing the same, and display panel using the same
US20020132454A1 (en) 2001-03-19 2002-09-19 Fuji Xerox Co., Ltd. Method of forming crystalline semiconductor thin film on base substrate, lamination formed with crystalline semiconductor thin film and color filter
JP2002289859A (ja) 2001-03-23 2002-10-04 Minolta Co Ltd 薄膜トランジスタ
JP2003086808A (ja) 2001-09-10 2003-03-20 Masashi Kawasaki 薄膜トランジスタおよびマトリクス表示装置
US6563174B2 (en) 2001-09-10 2003-05-13 Sharp Kabushiki Kaisha Thin film transistor and matrix display device
JP2003086000A (ja) 2001-09-10 2003-03-20 Sharp Corp 半導体記憶装置およびその試験方法
US7307279B2 (en) * 2001-10-30 2007-12-11 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US7061014B2 (en) 2001-11-05 2006-06-13 Japan Science And Technology Agency Natural-superlattice homologous single crystal thin film, method for preparation thereof, and device using said single crystal thin film
US7323356B2 (en) 2002-02-21 2008-01-29 Japan Science And Technology Agency LnCuO(S,Se,Te)monocrystalline thin film, its manufacturing method, and optical device or electronic device using the monocrystalline thin film
US20040038446A1 (en) 2002-03-15 2004-02-26 Sanyo Electric Co., Ltd.- Method for forming ZnO film, method for forming ZnO semiconductor layer, method for fabricating semiconductor device, and semiconductor device
US7049190B2 (en) 2002-03-15 2006-05-23 Sanyo Electric Co., Ltd. Method for forming ZnO film, method for forming ZnO semiconductor layer, method for fabricating semiconductor device, and semiconductor device
US20030189401A1 (en) 2002-03-26 2003-10-09 International Manufacturing And Engineering Services Co., Ltd. Organic electroluminescent device
US20030218222A1 (en) 2002-05-21 2003-11-27 The State Of Oregon Acting And Through The Oregon State Board Of Higher Education On Behalf Of Transistor structures and methods for making the same
US7501293B2 (en) 2002-06-13 2009-03-10 Murata Manufacturing Co., Ltd. Semiconductor device in which zinc oxide is used as a semiconductor material and method for manufacturing the semiconductor device
US7105868B2 (en) 2002-06-24 2006-09-12 Cermet, Inc. High-electron mobility transistor with zinc oxide
JP2004103957A (ja) 2002-09-11 2004-04-02 Japan Science & Technology Corp ホモロガス薄膜を活性層として用いる透明薄膜電界効果型トランジスタ
US20060035452A1 (en) 2002-10-11 2006-02-16 Carcia Peter F Transparent oxide semiconductor thin film transistor
US20040127038A1 (en) 2002-10-11 2004-07-01 Carcia Peter Francis Transparent oxide semiconductor thin film transistors
JP2004273614A (ja) 2003-03-06 2004-09-30 Sharp Corp 半導体装置およびその製造方法
JP2004273732A (ja) 2003-03-07 2004-09-30 Sharp Corp アクティブマトリクス基板およびその製造方法
WO2004114391A1 (ja) 2003-06-20 2004-12-29 Sharp Kabushiki Kaisha 半導体装置およびその製造方法ならびに電子デバイス
US20060244107A1 (en) 2003-06-20 2006-11-02 Toshinori Sugihara Semiconductor device, manufacturing method, and electronic device
US20050017302A1 (en) 2003-07-25 2005-01-27 Randy Hoffman Transistor including a deposited channel region having a doped portion
US7282782B2 (en) 2004-03-12 2007-10-16 Hewlett-Packard Development Company, L.P. Combined binary oxide semiconductor device
US20050199959A1 (en) 2004-03-12 2005-09-15 Chiang Hai Q. Semiconductor device
US20060043377A1 (en) 2004-03-12 2006-03-02 Hewlett-Packard Development Company, L.P. Semiconductor device
EP1737044A1 (en) 2004-03-12 2006-12-27 Japan Science and Technology Agency Amorphous oxide and thin film transistor
US20090278122A1 (en) 2004-03-12 2009-11-12 Japan Science And Technology Agency Amorphous oxide and thin film transistor
US20080254569A1 (en) 2004-03-12 2008-10-16 Hoffman Randy L Semiconductor Device
US7462862B2 (en) 2004-03-12 2008-12-09 Hewlett-Packard Development Company, L.P. Transistor using an isovalent semiconductor oxide as the active channel layer
EP2226847A2 (en) 2004-03-12 2010-09-08 Japan Science And Technology Agency Amorphous oxide and thin film transistor
US20090280600A1 (en) 2004-03-12 2009-11-12 Japan Science And Technology Agency Amorphous oxide and thin film transistor
US20070194379A1 (en) 2004-03-12 2007-08-23 Japan Science And Technology Agency Amorphous Oxide And Thin Film Transistor
US7297977B2 (en) 2004-03-12 2007-11-20 Hewlett-Packard Development Company, L.P. Semiconductor device
JP2005285975A (ja) 2004-03-29 2005-10-13 Seiko Epson Corp 半導体装置及びその製造方法、電気光学装置並びに電子機器
US7211825B2 (en) 2004-06-14 2007-05-01 Yi-Chi Shih Indium oxide-based thin film transistors and circuits
US7385224B2 (en) 2004-09-02 2008-06-10 Casio Computer Co., Ltd. Thin film transistor having an etching protection film and manufacturing method thereof
US20080006877A1 (en) 2004-09-17 2008-01-10 Peter Mardilovich Method of Forming a Solution Processed Device
US20060091793A1 (en) 2004-11-02 2006-05-04 3M Innovative Properties Company Methods and displays utilizing integrated zinc oxide row and column drivers in conjunction with organic light emitting diodes
JP2006165527A (ja) 2004-11-10 2006-06-22 Canon Inc 電界効果型トランジスタ
US7791072B2 (en) 2004-11-10 2010-09-07 Canon Kabushiki Kaisha Display
US20060113536A1 (en) 2004-11-10 2006-06-01 Canon Kabushiki Kaisha Display
US7453065B2 (en) 2004-11-10 2008-11-18 Canon Kabushiki Kaisha Sensor and image pickup device
US20060108636A1 (en) 2004-11-10 2006-05-25 Canon Kabushiki Kaisha Amorphous oxide and field effect transistor
US20060113549A1 (en) 2004-11-10 2006-06-01 Canon Kabushiki Kaisha Light-emitting device
US7601984B2 (en) 2004-11-10 2009-10-13 Canon Kabushiki Kaisha Field effect transistor with amorphous oxide active layer containing microcrystals and gate electrode opposed to active layer through gate insulator
US20060110867A1 (en) 2004-11-10 2006-05-25 Canon Kabushiki Kaisha Field effect transistor manufacturing method
US20060113565A1 (en) 2004-11-10 2006-06-01 Canon Kabushiki Kaisha Electric elements and circuits utilizing amorphous oxides
US20060113539A1 (en) 2004-11-10 2006-06-01 Canon Kabushiki Kaisha Field effect transistor
JP2006165529A (ja) 2004-11-10 2006-06-22 Canon Inc 非晶質酸化物、及び電界効果型トランジスタ
US20060108529A1 (en) 2004-11-10 2006-05-25 Canon Kabushiki Kaisha Sensor and image pickup device
US20060118166A1 (en) 2004-12-06 2006-06-08 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion element, solar battery, and photo sensor
US20090073325A1 (en) 2005-01-21 2009-03-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same, and electric device
US20060170111A1 (en) 2005-01-28 2006-08-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and method of manufacturing semiconductor device
US20060169973A1 (en) 2005-01-28 2006-08-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device, and method of manufacturing semiconductor device
US20090152541A1 (en) 2005-02-03 2009-06-18 Semiconductor Energy Laboratory Co., Ltd. Electronic device, semiconductor device and manufacturing method thereof
US20090134399A1 (en) 2005-02-18 2009-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Method for Manufacturing the Same
US20060197092A1 (en) 2005-03-03 2006-09-07 Randy Hoffman System and method for forming conductive material on a substrate
US20060208977A1 (en) 2005-03-18 2006-09-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and display device, driving method and electronic apparatus thereof
US20060231882A1 (en) 2005-03-28 2006-10-19 Il-Doo Kim Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications
US20060228974A1 (en) 2005-03-31 2006-10-12 Theiss Steven D Methods of making displays
US20060238135A1 (en) 2005-04-20 2006-10-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
US20060246738A1 (en) 2005-04-28 2006-11-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
EP1717847A2 (en) 2005-04-28 2006-11-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US7718547B2 (en) 2005-04-28 2010-05-18 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and method for manufacturing the same
KR20060113485A (ko) 2005-04-28 2006-11-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제조 방법
JP2006332634A (ja) 2005-04-28 2006-12-07 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
CN1870233B (zh) 2005-04-28 2010-05-12 株式会社半导体能源研究所 半导体器件及其制造方法
US20090098720A1 (en) 2005-04-28 2009-04-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US7465677B2 (en) 2005-04-28 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20060284172A1 (en) 2005-06-10 2006-12-21 Casio Computer Co., Ltd. Thin film transistor having oxide semiconductor layer and manufacturing method thereof
US20060284171A1 (en) 2005-06-16 2006-12-21 Levy David H Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US7402506B2 (en) 2005-06-16 2008-07-22 Eastman Kodak Company Methods of making thin film transistors comprising zinc-oxide-based semiconductor materials and transistors made thereby
US20060292777A1 (en) 2005-06-27 2006-12-28 3M Innovative Properties Company Method for making electronic devices using metal oxide nanoparticles
US20070024187A1 (en) 2005-07-28 2007-02-01 Shin Hyun S Organic light emitting display (OLED) and its method of fabrication
US20070046191A1 (en) 2005-08-23 2007-03-01 Canon Kabushiki Kaisha Organic electroluminescent display device and manufacturing method thereof
US20070052025A1 (en) 2005-09-06 2007-03-08 Canon Kabushiki Kaisha Oxide semiconductor thin film transistor and method of manufacturing the same
US20070054507A1 (en) 2005-09-06 2007-03-08 Canon Kabushiki Kaisha Method of fabricating oxide semiconductor device
US7468304B2 (en) 2005-09-06 2008-12-23 Canon Kabushiki Kaisha Method of fabricating oxide semiconductor device
US20090114910A1 (en) 2005-09-06 2009-05-07 Canon Kabushiki Kaisha Semiconductor device
US7453087B2 (en) * 2005-09-06 2008-11-18 Canon Kabushiki Kaisha Thin-film transistor and thin-film diode having amorphous-oxide semiconductor layer
JP2007096055A (ja) 2005-09-29 2007-04-12 Semiconductor Energy Lab Co Ltd 半導体装置、及び半導体装置の作製方法
US7732819B2 (en) 2005-09-29 2010-06-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7674650B2 (en) 2005-09-29 2010-03-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070090365A1 (en) 2005-10-20 2007-04-26 Canon Kabushiki Kaisha Field-effect transistor including transparent oxide and light-shielding member, and display utilizing the transistor
JP2006165528A5 (ja) 2005-11-09 2008-12-25
US20070108446A1 (en) 2005-11-15 2007-05-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20090186437A1 (en) 2005-11-15 2009-07-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20090186445A1 (en) 2005-11-15 2009-07-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20090189156A1 (en) 2005-11-15 2009-07-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20090189155A1 (en) 2005-11-15 2009-07-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20100003783A1 (en) 2005-11-15 2010-01-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20100038639A1 (en) 2005-11-15 2010-02-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20090068773A1 (en) 2005-12-29 2009-03-12 Industrial Technology Research Institute Method for fabricating pixel structure of active matrix organic light-emitting diode
US20070152217A1 (en) 2005-12-29 2007-07-05 Chih-Ming Lai Pixel structure of active matrix organic light-emitting diode and method for fabricating the same
US20080050595A1 (en) 2006-01-11 2008-02-28 Murata Manufacturing Co., Ltd. Transparent conductive film and method for manufacturing the same
US20070172591A1 (en) 2006-01-21 2007-07-26 Samsung Electronics Co., Ltd. METHOD OF FABRICATING ZnO FILM AND THIN FILM TRANSISTOR ADOPTING THE ZnO FILM
US20070187760A1 (en) 2006-02-02 2007-08-16 Kochi Industrial Promotion Center Thin film transistor including low resistance conductive thin films and manufacturing method thereof
US20070187678A1 (en) 2006-02-15 2007-08-16 Kochi Industrial Promotion Center Semiconductor device including active layer made of zinc oxide with controlled orientations and manufacturing method thereof
US20090065771A1 (en) * 2006-03-17 2009-03-12 Canon Kabushiki Kaisha Field effect transistor using oxide film for channel and method of manufacturing the same
US20070272922A1 (en) 2006-04-11 2007-11-29 Samsung Electronics Co. Ltd. ZnO thin film transistor and method of forming the same
US20070252928A1 (en) 2006-04-28 2007-11-01 Toppan Printing Co., Ltd. Structure, transmission type liquid crystal display, reflection type display and manufacturing method thereof
US20080290393A1 (en) * 2006-05-26 2008-11-27 Tetsuya Kakehata Nonvolatile semiconductor memory device and manufacturing method thereof, semiconductor device and manufacturing method thereof, and manufacturing method of insulating film
JP2008004929A (ja) 2006-05-26 2008-01-10 Semiconductor Energy Lab Co Ltd 不揮発性半導体記憶装置及びその作製方法、半導体装置及びその作製方法、並びに絶縁膜の作製方法
WO2007138937A1 (en) 2006-05-26 2007-12-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7955995B2 (en) * 2006-05-26 2011-06-07 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile semiconductor memory device and manufacturing method thereof, semiconductor device and manufacturing method thereof, and manufacturing method of insulating film
KR20090029738A (ko) 2006-05-26 2009-03-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작방법
US20070287296A1 (en) 2006-06-13 2007-12-13 Canon Kabushiki Kaisha Dry etching method for oxide semiconductor film
US7642114B2 (en) 2006-07-19 2010-01-05 Semiconductor Energy Laboratory Co., Ltd. Micro electro mechanical device and manufacturing method thereof
US20080038882A1 (en) 2006-08-09 2008-02-14 Kazushige Takechi Thin-film device and method of fabricating the same
US20080038929A1 (en) 2006-08-09 2008-02-14 Canon Kabushiki Kaisha Method of dry etching oxide semiconductor film
US7411209B2 (en) 2006-09-15 2008-08-12 Canon Kabushiki Kaisha Field-effect transistor and method for manufacturing the same
US20080106191A1 (en) 2006-09-27 2008-05-08 Seiko Epson Corporation Electronic device, organic electroluminescence device, and organic thin film semiconductor device
JP2007123861A5 (ja) 2006-09-27 2008-09-18
US20080073653A1 (en) 2006-09-27 2008-03-27 Canon Kabushiki Kaisha Semiconductor apparatus and method of manufacturing the same
US20080083950A1 (en) 2006-10-10 2008-04-10 Alfred I-Tsung Pan Fused nanocrystal thin film semiconductor and method
US20080128689A1 (en) 2006-11-29 2008-06-05 Je-Hun Lee Flat panel displays comprising a thin-film transistor having a semiconductive oxide in its channel and methods of fabricating the same for use in flat panel displays
US20080129195A1 (en) 2006-12-04 2008-06-05 Toppan Printing Co., Ltd. Color el display and method for producing the same
KR20090095612A (ko) 2006-12-05 2009-09-09 캐논 가부시끼가이샤 산화물 반도체를 이용한 표시장치 및 그 제조방법
US20100045179A1 (en) 2006-12-05 2010-02-25 Canon Kabushiki Kaisha Display apparatus using oxide semiconductor and production method thereof
WO2008069286A2 (en) 2006-12-05 2008-06-12 Canon Kabushiki Kaisha Display apparatus using oxide semiconductor and production method thereof
CN101548383B (zh) 2006-12-05 2011-04-13 佳能株式会社 使用氧化物半导体的显示设备及其制造方法
JP2008141119A (ja) 2006-12-05 2008-06-19 Canon Inc 酸化物半導体を用いた表示装置及びその製造方法
US20080166834A1 (en) 2007-01-05 2008-07-10 Samsung Electronics Co., Ltd. Thin film etching method
US20080182358A1 (en) 2007-01-26 2008-07-31 Cowdery-Corvan Peter J Process for atomic layer deposition
US20080224133A1 (en) 2007-03-14 2008-09-18 Jin-Seong Park Thin film transistor and organic light-emitting display device having the thin film transistor
US20080258139A1 (en) 2007-04-17 2008-10-23 Toppan Printing Co., Ltd. Structure with transistor
US20080258143A1 (en) 2007-04-18 2008-10-23 Samsung Electronics Co., Ltd. Thin film transitor substrate and method of manufacturing the same
US20080258141A1 (en) 2007-04-19 2008-10-23 Samsung Electronics Co., Ltd. Thin film transistor, method of manufacturing the same, and flat panel display having the same
US20080258140A1 (en) 2007-04-20 2008-10-23 Samsung Electronics Co., Ltd. Thin film transistor including selectively crystallized channel layer and method of manufacturing the thin film transistor
EP1983566A2 (en) 2007-04-20 2008-10-22 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
KR20080094558A (ko) 2007-04-20 2008-10-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판의 제작방법
US20110136320A1 (en) 2007-04-20 2011-06-09 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing soi substrate
US7897476B2 (en) 2007-04-20 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
US20080261376A1 (en) 2007-04-20 2008-10-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
JP2008288563A (ja) 2007-04-20 2008-11-27 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
CN101290876B (zh) 2007-04-20 2012-03-28 株式会社半导体能源研究所 Soi基板的制造方法
US20100109002A1 (en) 2007-04-25 2010-05-06 Canon Kabushiki Kaisha Oxynitride semiconductor
US20080296568A1 (en) 2007-05-29 2008-12-04 Samsung Electronics Co., Ltd Thin film transistors and methods of manufacturing the same
US20080296567A1 (en) * 2007-06-04 2008-12-04 Irving Lyn M Method of making thin film transistors comprising zinc-oxide-based semiconductor materials
US20100283049A1 (en) * 2007-12-04 2010-11-11 Canon Kabushiki Kaisha Oxide semiconductor device including insulating layer and display apparatus using the same
WO2009072532A1 (en) 2007-12-04 2009-06-11 Canon Kabushiki Kaisha Oxide semiconductor device including insulating layer and display apparatus using the same
CN101884109B (zh) 2007-12-04 2011-12-28 佳能株式会社 包含绝缘层的氧化物半导体器件和使用该器件的显示装置
JP2009141002A (ja) 2007-12-04 2009-06-25 Canon Inc 絶縁層を有する酸化物半導体素子およびそれを用いた表示装置
US20090152506A1 (en) 2007-12-17 2009-06-18 Fujifilm Corporation Process for producing oriented inorganic crystalline film, and semiconductor device using the oriented inorganic crystalline film
JP2009224479A (ja) 2008-03-14 2009-10-01 Fujifilm Corp 薄膜電界効果型トランジスタおよびその製造方法
US20100065844A1 (en) 2008-09-18 2010-03-18 Sony Corporation Thin film transistor and method of manufacturing thin film transistor
US20100092800A1 (en) 2008-10-09 2010-04-15 Canon Kabushiki Kaisha Substrate for growing wurtzite type crystal and method for manufacturing the same and semiconductor device
CN101464892A (zh) 2008-12-31 2009-06-24 中兴通讯股份有限公司 一种动态数据库的登录方法及装置
US20100233847A1 (en) 2009-03-12 2010-09-16 Hiroki Ohara Method for manufacturing semiconductor device
US20110053322A1 (en) 2009-06-30 2011-03-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20110068336A1 (en) 2009-09-24 2011-03-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and method for manufacturing the same
US20110089416A1 (en) 2009-10-21 2011-04-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20110309355A1 (en) 2010-06-18 2011-12-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Non-Patent Citations (72)

* Cited by examiner, † Cited by third party
Title
Asakuma.N et al., "Crystallization and Reduction of Sol-Gel-Derived Zinc Oxide Films by Irradiation With Ultraviolet Lamp,", Journal of Sol-Gel Science and Technology, 2003, vol. 26, pp. 181-184.
Asaoka.Y et al., "29.1:Polarizer-Free Reflective LCD Combined With Ultra Low-Power Driving Technology,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 395-398.
Chern.H et al., "An Analytical Model for the Above-Threshold Characteristics of Polysilicon Thin-Film Transistors,", IEEE Transactions on Electron Devices, Jul. 1, 1995, vol. 42, No. 7, pp. 1240-1246.
Cho.D et al., "21.2:Al and Sn-Doped Zinc Indium Oxide Thin Film Transistors for AMOLED Back-Plane,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 280-283.
Clark.S et al., "First Principles Methods Using CASTEP,", Zeitschrift fur Kristallographie, 2005, vol. 220, pp. 567-570.
Coates.D et al., "Optical Studies of the Amorphous Liquid-Cholesteric Liquid Crystal Transition:The "Blue Phase",", Physics Letters, Sep. 10, 1973, vol. 45A, No. 2, pp. 115-116.
Costello.M et al., "Electron Microscopy of a Cholesteric Liquid Crystal and Its Blue Phase,", Phys. Rev. A (Physical Review. A), May 1, 1984, vol. 29, No. 5, pp. 2957-2959.
Dembo.H et al., "RFCPUS on Glass and Plastic Substrates Fabricated by TFT Transfer Technology,", IEDM 05: Technical Digest of International Electron Devices Meeting, Dec. 5, 2005, pp. 1067-1069.
Fortunato.E et al., "Wide-Bandgap High-Mobility ZnO Thin-Film Transistors Produced at Room Temperature,", Appl. Phys. Lett. (Applied Physics Letters) , Sep. 27, 2004, vol. 85, No. 13, pp. 2541-2543.
Fung.T et al., "2-D Numerical Simulation of High Performance Amorphous In-Ga-Zn-O TFTs for Flat Panel Display,", AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 251-252, The Japan Society of Applied Physics.
Godo.H et al., "P-9:Numerical Analysis on Temperature Dependence of Characteristics of Amorphous In-Ga-Zn-Oxide TFT,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 1110-1112.
Godo.H et al., "Temperature Dependence of Characteristics and Electronic Structure for Amorphous In-Ga-Zn-Oxide TFT,", AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 41-44.
Hayashi.R et al., "42.1: Invited Paper: Improved Amorphous In-Ga-Zn-O TFTs,", SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 621-624.
Hirao.T et al., "Novel Top-Gate Zinc Oxide Thin-Film Transistors (ZnO TFTs) for AMLCDS,", Journal of the SID, 2007, vol. 15, No. 1, pp. 17-22.
Hosono.H et al., "Working hypothesis to explore novel wide band gap electrically conducting amorphous oxides and examples,", J. Non-Cryst. Solids (Journal of Non-Crystalline Solids), 1996, vol. 198-200, pp. 165-169.
Hosono.H, "68.3:Invited Paper:Transparent Amorphous Oxide Semiconductors for High Performance TFT,", SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1830-1833.
Hsieh.H et al., "P-29:Modeling of Amorphous Oxide Semiconductor Thin Film Transistors and Subgap Density of States,", SID Digest '08 : SID International Symposium Digest of Technical Papers, 2008, vol. 39, pp. 1277-1280.
Ikeda.T et al., "Full-Functional System Liquid Crystal Display Using Cg-Silicon Technology,", SID Digest '04 : SID International Symposium Digest of Technical Papers, 2004, vol. 35, pp. 860-863.
International Search Report (Application No. PCT/JP2011/060792) Dated Jun. 21, 2011.
Janotti.A et al., "Native Point Defects in ZnO,", Phys. Rev. B (Physical Review. B), Oct. 4, 2007, vol. 76, No. 16, pp. 165202-1-165202-22.
Janotti.A et al., "Oxygen Vacancies in ZnO,", Appl. Phys. Lett. (Applied Physics Letters) , 2005, vol. 87, pp. 122102-1-122102-3.
Jeong.J et al., "3.1: Distinguished Paper: 12.1-Inch WXGA AMOLED Display Driven by Indium-Gallium-Zinc Oxide TFTs Array,", SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, No. 1, pp. 1-4.
Jin.D et al., "65.2:Distinguished Paper:World-Largest (6.5'') Flexible Full Color Top Emission AMOLED Display on Plastic Film and Its Bending Properties,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 983-985.
Jin.D et al., "65.2:Distinguished Paper:World-Largest (6.5″) Flexible Full Color Top Emission AMOLED Display on Plastic Film and Its Bending Properties,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 983-985.
Kanno.H et al., "White Stacked Electrophosphorecent Organic Light-Emitting Devices Employing MOO3 as a Charge-Generation Layer,", Adv. Mater. (Advanced Materials), 2006, vol. 18, No. 3, pp. 339-342.
Kikuchi.H et al., "39.1:Invited Paper:Optically Isotropic Nano-Structured Liquid Crystal Composites for Display Applications,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 578-581.
Kikuchi.H et al., "62.2:Invited Paper:Fast Electro-Optical Switching in Polymer-Stabilized Liquid Crystalline Blue Phases for Display Application,", SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1737-1740.
Kikuchi.H et al., "Polymer-Stabilized Liquid Crystal Blue Phases,", Nature Materials, Sep. 2, 2002, vol. 1, pp. 64-68.
Kim.S et al., "High-Performance oxide thin film transistors passivated by various gas plasmas,", 214th ECS Meeting, 2008, No. 2317, ECS.
Kimizuka.N et al., "Spinel,YBFE2O4, and YB2FE3O7 Types of Structures for Compounds in the In2O3 and Sc2O3-A2O3-BO Systems [A; Fe, Ga, or Al; B: Mg, Mn, Fe, Ni, Cu,or Zn] At Temperatures Over 1000° C.,", Journal of Solid State Chemistry, 1985, vol. 60, pp. 382-384.
Kimizuka.N et al., "Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m=3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7, 8, 9, and 16) in the In2O3-ZnGa2O4-ZnO System,", Journal of Solid State Chemistry, Apr. 1, 1995, vol. 116, No. 1, pp. 170-178.
Kitzerow.H et al., "Observation of Blue Phases in Chiral Networks,", Liquid Crystals, 1993, vol. 14, No. 3, pp. 911-916.
Kurokawa.Y et al., "UHF RFCPUS on Flexible and Glass Substrates for Secure RFID Systems,", Journal of Solid-State Circuits , 2008, vol. 43, No. 1, pp. 292-299.
Lany.S et al., "Dopability, Intrinsic Conductivity, and Nonstoichiometry of Transparent Conducting Oxides,", Phys. Rev. Lett. (Physical Review Letters), Jan. 26, 2007, vol. 98, pp. 045501-1-45501-4.
Lee.H et al., "Current Status of, Challenges to, and Perspective View of AM-OLED,", IDW '06 : Proceedings of the 13th International Display Workshops, Dec. 7, 2006, pp. 663-666.
Lee.J et al., "World's Largest (15-Inch) XGA AMLCD Panel Using IGZO Oxide TFT,", SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 625-628.
Lee.M et al., "15.4:Excellent Performance of Indium-Oxide-Based Thin-Film Transistors by DC Sputtering,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 191-193.
Li.C et al., "Modulated Structures of Homologous Compounds InMO3(ZnO)m (M=In,Ga; m=Integer) Described by Four-Dimensional Superspace Group,", Journal of Solid State Chemistry, 1998, vol. 139, pp. 347-355.
Masuda.S et al., "Transparent thin film transistors using ZnO as an active channel layer and their electrical properties,", J. Appl. Phys. (Journal of Applied Physics) , Feb. 1, 2003, vol. 93, No. 3, pp. 1624-1630.
Meiboom.S et al., "Theory of the Blue Phase of Cholesteric Liquid Crystals,", Phys. Rev. Lett. (Physical Review Letters), May 4, 1981, vol. 46, No. 18, pp. 1216-1219.
Miyasaka.M, "Suftla Flexible Microelectronics on Their Way to Business,", SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1673-1676.
Mo.Y et al., "Amorphous Oxide TFT Backplanes for Large Size AMOLED Displays,", IDW '08 : Proceedings of the 6th International Display Workshops, Dec. 3, 2008, pp. 581-584.
Nakamura.M et al., "The phase relations in the In2O3-Ga2ZnO4-ZnO system at 1350° C.,", Journal of Solid State Chemistry, Aug. 1, 1991, vol. 93, No. 2, pp. 298-315.
Nakamura.M, "Synthesis of Homologous Compound with New Long-Period Structure,", NIRIM Newsletter, Mar. 1, 1995, vol. 150, pp. 1-4.
Nomura.K et al., "Amorphous Oxide Semiconductors for High-Performance Flexible Thin-Film Transistors,", Jpn. J. Appl. Phys. (Japanese Journal of Appl. Phys. (Japanese Journal of Applied Physics) , 2006, vol. 45, No. 5B, pp. 4303-4308.
Nomura.K et al., "Carrier transport in transparent oxide semiconductor with intrinsic structural randomness probed using single-crystalline InGaO3(ZnO)5 films,", Appl. Phys. Lett. (Applied Physics Letters) , Sep. 13, 2004, vol. 85, No. 11, pp. 1993-1995.
Nomura.K et al., "Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amporphous Oxide Semiconductors,", Nature, Nov. 25, 2004, vol. 432, pp. 488-492.
Nomura.K et al., "Thin-Film Transistor Fabricated in Single-Crystalline Transparent Oxide Semiconductor,", Science, May 23, 2003, vol. 300, No. 5623, pp. 1269-1272.
Nowatari.H et al., "60.2: Intermediate Connector With Suppressed Voltage Loss for White Tandem OLEDs,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, vol. 40, pp. 899-902.
Oba.F et al., "Defect energetics in ZnO: A hybrid Hartree-Fock density functional study,", Phys. Rev. B (Physical Review. B), 2008, vol. 77, pp. 245202-1-245202-6.
Oh.M et al., "Improving the Gate Stability of ZnO Thin-Film Transistors With Aluminum Oxide Dielectric Layers,", J. Electrochem. Soc. (Journal of the Electrochemical Society), 2008, vol. 155, No. 12, pp. H1009-H1014.
Ohara.H et al., "21.3:4.0 In. QVGA AMOLED Display Using In-Ga-Zn-Oxide TFTs With a Novel Passivation Layer,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 284-287.
Ohara.H et al., "Amorphous In-Ga-Zn-Oxide TFTs with Suppressed Variation for 4.0 inch QVGA AMOLED Display,", AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 227-230, The Japan Society of Applied Physics.
Orita.M et al., "Amorphous transparent conductive oxide InGaO3(ZnO)m (m<4):a Zn4s conductor,", Philosophical Magazine, 2001, vol. 81, No. 5, pp. 501-515.
Orita.M et al., "Mechanism of Electrical Conductivity of Transparent InGaZnO4,", Phys. Rev. B (Physical Review. B), Jan. 15, 2000, vol. 61, No. 3, pp. 1811-1816.
Osada.T et al., "15.2: Development of Driver-Integrated Panel using Amorphous In-Ga-Zn-Oxide TFT,", SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 184-187.
Osada.T et al., "Development of Driver-Integrated Panel Using Amorphous In-Ga-Zn-Oxide TFT,", AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 33-36.
Park.J et al., "Amorphous Indium-Gallium-Zinc Oxide TFTs and Their Application for Large Size AMOLED,", AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 275-278.
Park.J et al., "Dry etching of ZnO films and plasma-induced damage to optical properties,", J. Vac. Sci. Technol. B (Journal of Vacuum Science & Technology B), Mar. 1, 2003, vol. 21, No. 2, pp. 800-803.
Park.J et al., "Electronic Transport Properties of Amorphous Indium-Gallium-Zinc Oxide Semiconductor Upon Exposure to Water,", Appl. Phys. Lett. (Applied Physics Letters) , 2008, vol. 92, pp. 072104-1-072104-3.
Park.J et al., "High performance amorphous oxide thin film transistors with self-aligned top-gate structure,", IEDM 09: Technical Digest of International Electron Devices Meeting, Dec. 7, 2009, pp. 191-194.
Park.J et al., "Improvements in the Device Characteristics of Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors by Ar Plasma Treatment,", Appl. Phys. Lett. (Applied Physics Letters) , Jun. 26, 2007, vol. 90, No. 26, pp. 262106-1-262106-3.
Park.S et al., "Challenge to Future Displays: Transparent AM-OLED Driven by PEALD Grown ZnO TFT,", IMID '07 Digest, 2007, pp. 1249-1252.
Park.Sang-Hee et al., "42.3: Transparent ZnO Thin Film Transistor for the Application of High Aperture Ratio Bottom Emission AM-OLED Display,", SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 629-632.
Prins.M et al., "A Ferroelectric Transparent Thin-Film Transistor,", Appl. Phys. Lett. (Applied Physics Letters) , Jun. 17, 1996, vol. 68, No. 25, pp. 3650-3652.
Sakata.J et al., "Development of 4.0-In. AMOLED Display With Driver Circuit Using Amorphous In-Ga-Zn-Oxide TFTs,", IDW '09 : Proceedings of the 16th International Display Workshops, 2009, pp. 689-692.
Son.K et al., "42.4L: Late-News Paper: 4 Inch QVGA AMOLED Driven by the Threshold Voltage Controlled Amorphous GIZO (Ga2O3-In2O3-ZnO) TFT,", SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 633-636.
Takahashi.M et al., "Theoretical Analysis of IGZO Transparent Amorphous Oxide Semiconductor,", IDW '08 : Proceedings of the 15th International Display Workshops, Dec. 3, 2008, pp. 1637-1640.
Tsuda.K et al., "Ultra Low Power Consumption Technologies for Mobile TFT-LCDs,", IDW '02 : Proceedings of the 9th International Display Workshops, Dec. 4, 2002, pp. 295-298.
Ueno.K et al., "Field-Effect Transistor on SrTiO3 With Sputtered Al2O3 Gate Insulator,", Appl. Phys. Lett. (Applied Physics Letters) , Sep. 1, 2003, vol. 83, No. 9, pp. 1755-1757.
Van de Walle.C, "Hydrogen as a Cause of Doping in Zinc Oxide,", Phys. Rev. Lett. (Physical Review Letters), Jul. 31, 2000, vol. 85, No. 5, pp. 1012-1015.
Written Opinion (Application No. PCT/JP2011/060792) Dated Jun. 21, 2011.

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150053975A1 (en) * 2010-05-21 2015-02-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9443988B2 (en) * 2010-05-21 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9842939B2 (en) 2010-05-21 2017-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9614100B2 (en) 2012-01-18 2017-04-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
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