US6751131B2 - Semiconductor storage device and information apparatus - Google Patents

Semiconductor storage device and information apparatus Download PDF

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US6751131B2
US6751131B2 US10/308,835 US30883502A US6751131B2 US 6751131 B2 US6751131 B2 US 6751131B2 US 30883502 A US30883502 A US 30883502A US 6751131 B2 US6751131 B2 US 6751131B2
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word line
reference cell
signal
redundant
normal
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US20030112664A1 (en
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Kaname Yamano
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Samsung Electronics Co Ltd
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Sharp Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

  • the present invention relates to a non-volatile memory in which data is electrically rewritable, e.g., a semiconductor storage device such as a flash EEPROM or the like, and to an information device using the non-volatile memory, such as a cellular phone terminal or the like.
  • a non-volatile memory in which data is electrically rewritable, e.g., a semiconductor storage device such as a flash EEPROM or the like, and to an information device using the non-volatile memory, such as a cellular phone terminal or the like.
  • a data read operation is performed as follows: as shown in FIG.
  • the same drain voltage is applied to a memory cell RC 0 set at a predetermined threshold value, which is called a “reference cell”, and to a memory cell MC 0 of a memory array on which a data read operation is performed, while the same gate voltage is applied by a reference word line decoder and a normal word line decoder, and a difference between the values of currents flowing through the memory cells RC 0 and MC 0 is amplified by a sense amplifier S/A, and the result of the amplification is read out as stored data.
  • a predetermined threshold value which is called a “reference cell”
  • a memory cell MC 0 of a memory array on which a data read operation is performed while the same gate voltage is applied by a reference word line decoder and a normal word line decoder, and a difference between the values of currents flowing through the memory cells RC 0 and MC 0 is amplified by a sense amplifier S/A, and the result of the amplification is read out as
  • a gate voltage is constantly applied to the reference cell RC 0 while the supply voltage is supplied to the storage device (see FIGS. 9 through 11 ).
  • a gate voltage is applied to the reference cell RC 0 according to an ATD signal which is activated during the data read operation (see FIGS. 12 through 14 ).
  • FIG. 9 is a block diagram showing an exemplary structure of a primary part of a conventional non-volatile semiconductor storage device 10 .
  • FIG. 9 illustrates a method wherein a voltage is constantly applied to each of the word lines of reference cells RC 0 , RC 1 and RC 2 while the supply voltage is supplied to the storage device.
  • the conventional non-volatile semiconductor storage device 10 includes: a memory cell array RA formed by a plurality of reference cells RC 0 -RC 2 (hereinafter, referred to as “reference array RA”): level shifters LS 0 and LS 1 , which form a word line control circuit for controlling the word lines of the reference cells; a memory cell array MA (hereinafter, referred to as “memory array MA”), which is a data storage region; a normal word line predecoder XPDEC; a normal word line decoder XDEC; a redundant word line predecoder XPRDEC; and a redundant word line decoder XRDEC.
  • the reference array RA includes: the reference cell RC 0 used in a data read operation; the reference cell RC 1 used for verifying deletion of data; and the reference cell RC 2 used for verification in a data write operation.
  • a reference cell word line RWL 0 is connected to the gates of the reference cells RC 0 and RC 1 , and a reference cell word line RWL 1 is connected to the gate of the reference cell RC 2 .
  • a bit line RBL 0 is connected to the drain of the reference cell RC 0 ; a bit line RBL 1 is connected to the drain of the reference cell RC 1 ; and a bit line RBL 2 is connected to the drain of the reference cell RC 2 .
  • the sources of the reference cells RC 0 -RC 2 are all connected to a common source line RHS.
  • the level shifters LS 0 and LS 1 are powered by a node voltage HWL for word lines.
  • the level shifter LS 0 receives a reference cell selection signal SEL 0 , and outputs a voltage based on the received reference cell selection signal SEL 0 to the reference cell word line RWL 0 , thereby selecting the word line RWL 0 .
  • the level shifter LS 1 receives a reference cell selection signal SEL 1 , and outputs a voltage based on the received reference cell selection signal SEL 1 to the reference cell word line RWL 1 , thereby selecting the word line RWL 1 .
  • the reference cell selection signals SEL 0 and SEL 1 are exclusively activated, such that one of the signals SEL 0 and SEL 1 is ON (e.g., when the supply voltage VCC is supplied to the storage device 10 ) while the other is OFF. For example, when the reference cell selection signal SEL 0 is ON, the potential of the reference cell word line RWL 0 rises, whereby the reference cell word line RWL 0 is selected. When the reference cell selection signal SEL 1 is ON, the potential of the reference cell word line RWL 1 rises, whereby the reference cell word line RWL 1 is selected.
  • the memory array MA includes a plurality of memory cells as memory elements arranged in a matrix along row and column directions.
  • a memory array normal word line MWL is connected to the gate of the memory cell MC 0
  • a memory array redundant word line ReWL is connected to the gate of the memory cell MC 1 .
  • a common bit line MBL is connected to each of the drains of the memory cells MC 0 and MC 1
  • a source line MHS is connected to each of the sources of the memory cells MC 0 and MC 1 .
  • the source lines RHS and MHS are generally kept at the ground level, but controlled to be at a different level when the storage device is in a special mode, such as a test mode or the like. For example, in a deletion mode, the source lines RHS and MHS are at a high voltage level.
  • a redundancy determination signal MD, an address signal ADD and a word line enabling ATD signal SPW are input to the normal word line predecoder XPDEC. Based on these signals, the normal word line predecoder XPDEC outputs a normal word line selection signal SX to the normal word line decoder XDEC.
  • the normal word line decoder XDEC is powered by the node voltage HWL for word lines. Further, the normal word line decoder XDEC receives a normal word line selection signal SX which is output from the normal word line predecoder XPDEC, and outputs a voltage to a predetermined memory array normal word line MWL according to the normal word line selection signal SX, thereby selecting the predetermined memory array normal word line MWL.
  • the redundant word line predecoder XPRDEC receives the address signal ADD, the word line enabling ATD signal SPW, and a redundant word line address signal BADD. According to these signals, the redundant word line predecoder XPRDEC outputs a redundancy determination signal MD to the normal word line predecoder XPDEC, and a redundant word line selection signal RX to the redundant word line decoder XRDEC.
  • the redundant word line decoder XRDEC is powered by the node voltage HWL for word lines. Further, the redundant word line decoder XRDEC receives a redundant word line selection signal RX which is output from the redundant word line predecoder XPRDEC, and outputs a voltage to a predetermined memory array redundant word line ReWL according to the redundant word line selection signal RX, thereby selecting the predetermined memory array redundant word line ReWL.
  • a word line selection operation is now described with reference to the timing chart of FIG. 10, which is performed by a word line control circuit for the reference cells, a normal word line control circuit for the memory array, and a redundant word line control circuit for the memory array when a non-redundant memory array normal word line is selected.
  • FIG. 10 shows, from the top to the bottom of FIG. 10, supply voltage VCC; the node voltage HWL for word lines; a chip enabling signal CE# which is a control signal for activating the storage device 10 ; an output enabling signal OE# which is a control signal for permitting data output; the word line enable ATD signal SPW which is output from an address transition detection circuit (not shown); the potential of the reference cell word line RWL 0 ; the normal word line selection signal SX; the potential of the memory array normal word line MWL; and the potential of the memory array redundant word line ReWL.
  • the chip enabling signal CE# and the output enabling signal OE# are at the ground level, a data read operation can be performed.
  • the chip enabling signal CE# and the output enabling signal OE# are control signals generally employed in a semiconductor memory, and therefore are omitted from the block diagram of FIG. 9 .
  • a memory in which data is electrically rewritable e.g., the non-volatile semiconductor storage device 10 (such as a flash EEPROM)
  • data can be read out unless a data write command or data deletion command is issued immediately after the supply voltage is started to be applied. That is, the chip enabling signal CE# for activating the semiconductor chip and the output enabling signal OE# for permitting data output from an output pad are decreased to the ground level, whereby information stored in the memory cell MC 0 can be read out.
  • the supply voltage VCC begins to rise.
  • the node voltage HWL for word lines which is used for reading of data, begins to rise.
  • the reference cell selection signal SEL 0 is ON while the reference cell selection signal SEL 1 is OFF (ground level), the word line RWL 0 of the reference cell RC 0 is charged through the level shifter LS 0 with the node voltage HWL for word lines (about DC 5 V). Furthermore, the bit line RBL 0 is selected, and the common source line RHS of the reference cell RC 0 is controlled so as to be at the ground level. This voltage-controlled state occurs when a read command is issued.
  • the storage device 10 At time t 2 which occurs immediately after the storage device 10 is powered on with supply voltage VCC, the storage device 10 is in a data readable state. That is, in this state, data can be read out from the storage device 10 by decreasing the chip enabling signal CE# and the output enabling signal OE# to the ground level.
  • the word line enable ATD signal SPW rises in response to the chip enabling signal CE# reaching the ground level.
  • the normal word line selection signal SX rises to the supply voltage level.
  • the potential of the predetermined memory array normal word line MWL rises in response to the rising of the normal word line selection signal SX. Note that since the memory array redundant word line ReWL is not selected in this example, the potential of the memory array redundant word line ReWL remains at the ground level.
  • the word line enable ATD signal SPW falls to the ground level at time t 6 . Accordingly, the potential of the predetermined memory array normal word line MWL falls to the ground level at time t 7 .
  • the reference cell word line RWL 0 of the reference cell RC 0 always remains high.
  • a word line selection operation is described with reference to the timing chart of FIG. 11, which is performed by a word line control circuit for reference cells, a normal word line control circuit for memory array, and a redundant word line control circuit for memory array when a redundant word line is selected.
  • a redundancy determination signal MD and a redundant word line selection signal RX are considered in addition to the various signals described above, and a redundant word line is considered in place of the memory array normal word line MWL.
  • the operation from time to through time t 3 is totally the same as that described in FIG. 10, and therefore, the description thereof is herein omitted.
  • the following description of the word line selection operation begins with time t 4 .
  • the normal word line selection signal SX rises to the supply voltage level at time t 4 , and accordingly, the potential of the memory array normal word line MWL begins to rise.
  • a redundancy determination signal MD is issued, and the normal word line predecoder XPDEC receives the redundancy determination signal MD and lowers the normal word line selection signal SX back to the ground level.
  • the normal word line decoder XDEC receives the lowered normal word line selection signal SX and lowers the potential of the memory array normal word line MWL back to the ground level.
  • the redundant word line selection signal RX output from the redundant word line predecoder XPRDEC reaches the supply voltage level.
  • the potential of the memory array redundant word line ReWL rises in substitution for the memory array normal word line MWL.
  • the memory array normal word line MWL is switched to the memory array redundant word line ReWL after the potential of the memory array normal word line MWL begins to rise.
  • the normal word line predecoder XPDEC undesirably issues the normal word line selection signal SX while-the redundant word line predecoder XPRDEC is considering whether the word lines should be switched, and accordingly, a certain length of time is required for canceling the normal word line selection signal SX by the redundancy determination signal MD.
  • the word line enable ATD signal SPW falls to a low level (GND level) at time t 6 . Accordingly, the redundant word line selection signal RX falls at time t 7 , and as a result, the potential of the memory array redundant word line ReWL falls to the ground level.
  • FIG. 9 shows also the reference cell RC 1 used for verifying deletion of data and the reference cell RC 2 used for verification in a data write operation. These cells are now briefly described below.
  • a verifying operation is performed for determining whether or not writing of data is normally performed.
  • the reference cell selection signal SEL 1 is ON (high level) whereas the reference cell selection signal SEL 0 is OFF (low level).
  • the bit line RBL 2 is selected so that the bit line RBL 0 of the reference cell RC 0 for reading data is unselected.
  • the reference cell RC 2 becomes accessible.
  • the common source line RHS is at the ground level, and the node voltage HWL for word lines is increased to, e.g., about 6 V, so as to perform a verifying operation.
  • a verifying operation is performed for determining whether or not the deletion operation has been normally completed.
  • the reference cell selection signal SEL 0 is ON (high level) whereas the reference cell selection signal SEL 1 is OFF (low level).
  • the bit line RBL 1 is selected so that the reference cell RC 1 for verifying deletion of data becomes accessible.
  • the common source line RHS is at the ground level as in the write verifying operation, and the node voltage HWL for word lines is increased to, e.g., about 5 V, so as to perform a verifying operation.
  • FIG. 12 is a block diagram showing another exemplary structure of a primary part of a conventional non-volatile semiconductor storage device 11 .
  • FIG. 12 illustrates a method wherein a voltage is applied to a reference cell word line RWL of a reference cell RC according to the word line enable ATD signal SPW which is activated during a data read operation.
  • the conventional non-volatile semiconductor storage device 11 includes: a memory cell array RA including a reference cell RC (hereinafter, referred to as “reference array RA”); a reference word line control circuit CU; a memory cell array MA (hereinafter, referred to as “memory array MA”), which is a data storage region; a normal word line predecoder XPDEC; a normal word line decoder XDEC; a redundant word line predecoder XPRDEC; and a redundant word line decoder XRDEC.
  • a memory cell array RA including a reference cell RC (hereinafter, referred to as “reference array RA”); a reference word line control circuit CU; a memory cell array MA (hereinafter, referred to as “memory array MA”), which is a data storage region; a normal word line predecoder XPDEC; a normal word line decoder XDEC; a redundant word line predecoder XPR
  • the arrangement of the memory array normal word line MWL, a circuit system for selectively controlling the memory array redundant word line ReWL, and the circuit structure of the memory array MA, and operations thereof, are the same as those in the non-volatile semiconductor storage device 10 shown in FIG. 9, and therefore, descriptions thereof are herein omitted.
  • the reference array RA includes the reference cell RC used for reading data.
  • a reference cell word line RWL is connected to the gate of the reference cell RC; a bit line RBL is connected to the drain of the reference cell RC; and a source line RHS is connected to the source of the reference cell RC.
  • the source line RHS is generally kept at the ground level, but controlled to be at a different level when the storage device is in a special mode, such as a test mode or the like. For example, in a deletion mode, the source line RHS is at a high voltage level.
  • reference cells used for writing of data or a deletion verifying processing may be provided in other reference arrays, or may be provided in the reference array RA of FIG.
  • the reference word line control circuit CU is powered with the node voltage HWL for word lines.
  • the reference word line control circuit CU controls the potential of the reference cell word line RWL.
  • the reference word line control circuit CU receives the word line enable ATD signal SPW which is issued when data is read out and a test word line selection signal SD for selectively controlling the reference cell word line RWL in a forcible manner during the test mode.
  • the reference word line control circuit CU outputs a voltage to a predetermined reference cell word line RWL based on the above signals, thereby selecting the predetermined reference cell word line RWL.
  • a word line selection operation is described with reference to the timing chart of FIG. 13, which is performed by a word line control circuit for the reference cells, a normal word line control circuit for the memory array, and a redundant word line control circuit for the memory array when a non-redundant normal word line is selected.
  • FIG. 13 shows, from the top to the bottom of FIG. 13, supply voltage VCC; the node voltage HWL for word lines; a chip enabling signal CE# which is an input control signal for enabling a read or write operation in the storage device 10 (the storage device 10 can be operated when the chip enabling signal CE# is at the ground level); an output enabling signal OE# (data can be read out when the output enabling signal OE# is at the ground level); the word line enable ATD signal SPW; the potential of the reference cell word line RWL; the normal word line selection signal SX; the potential of the memory array normal word line MWL; and the potential of the memory array redundant word line ReWL.
  • the supply voltage VCC begins to rise.
  • the node voltage HWL for word lines which is used for reading of data, begins to rise.
  • the non-volatile semiconductor storage device 11 e.g., flash EEPROM or the like
  • the non-volatile semiconductor storage device 11 is in a data readable state immediately after it is powered ON. That is, in this state, a data read operation can be carried out by decreasing the chip enabling signal CE# to the ground level.
  • the word line enable ATD signal SPW rises in response to the falling of the chip enabling signal CE#.
  • the reference cell word line RWL is charged with the node voltage HWL for word lines at time t 4 , and at the same time, the normal word line predecoder XPDEC issues the normal word line selection signal SX.
  • the normal word line predecoder XDEC raises the potential of the memory array normal word line MWL according to an output of the normal word line selection signal SX. Note that the potential of the memory array normal word line MWL rises with a slight delay behind the rising of the reference cell word line RWL due to a decoding operation.
  • the word line enable ATD signal SPW falls to the ground level at time t 6 . Accordingly, the reference cell word line RWL and the memory array normal word line MWL fall to the ground level at time t 7 .
  • a word line selection operation is described with reference to the timing chart of FIG. 14, which is performed by a word line control circuit for the reference cells, a normal word line control circuit for the memory array, and a redundant word line control circuit for the memory array when a redundant word line is selected.
  • a redundancy determination signal MD and a redundant word line selection signal RX are considered in addition to the various signals described above, and a redundant word line is considered in place of the memory array normal word line MWL.
  • the operation from time t 0 through time t 3 is totally the same as that described in FIG. 13, and therefore, the description thereof is herein omitted.
  • the following description of the word line selection operation begins with time t 4 .
  • the normal word line selection signal SX rises to the supply voltage level at time t 4 , and accordingly, the potential of the memory array normal word line MWL begins to rise.
  • a redundancy determination signal MD is issued, and the normal word line selection signal SX decreases back to the ground level in response to the redundancy determination signal MD at time t 5 .
  • the potential of the memory array normal word line MWL decreases back to the ground level.
  • the redundant word line selection signal RX rises to the supply voltage level.
  • the potential of the memory array redundant word line ReWL rises in substitution for the memory array normal word line MWL.
  • the reason why the memory array normal word line MWL slightly pulses between time t 4 and time t 5 is the same as that described in connection with the example illustrated in FIG. 11 .
  • the word line enable ATD signal SPW falls to a low level at time t 6 . Accordingly, the redundant word line selection signal RX and the potential of the reference cell word line RWL fall to the ground level at time t 7 , and as a result, the potential of the memory array redundant word line ReWL falls to the ground level.
  • reading of stored information (data) from the memory cell can be carried out as follows: the same voltage is applied to the reference cell RC and a memory cell MC 0 from which data is to be read out, and a difference between the values of currents flowing through the memory cells RC and MC 0 is sensed by a sense amplifier S/A, which is formed by a differential amplifier, whereby reading of data is achieved.
  • a risk of erroneous reading of data can be avoided by starting a sensing operation after a word line of a reference array and a word line for a memory array reach a predetermined voltage.
  • a reduction in read access time cannot be achieved because of the latency required until the word line of the reference array and the word line for the memory array reach a desired voltage.
  • the sense amplifier S/A is activated so as to begin a sensing operation before both of the above word lines reach a desired voltage, whereby an increase in access speed is achieved.
  • the left part shows a reference cell RC of a non-volatile memory such as a flash memory
  • the right part shows a memory cell MC of then on-volatile memory.
  • agate voltage VgsR which is applied to the reference cell RC
  • a gate voltage VgsM which is applied to the memory cell MC
  • a current IdsM flows between a drain and source of the reference cell MC.
  • FIG. 16 shows a graph of the voltage levels VgsR and VgsM of the word lines during reading of data from the memory cells RC and MC, where the horizontal axis represents time t, and the vertical axis represents voltage level V.
  • t(a) represents the time when a sensing operation starts (hereinafter, “sensing start time”)
  • t(b) represents the time when both the voltage level of the reference cell word line RWL of the memory cell RC and the voltage level of the memory array normal word line MWL of the memory cell MC (or the memory array redundant word line ReWL) reach a predetermined voltage level.
  • the voltage level VgsR of the word line of the reference cell RC is at the predetermined voltage level in either of the examples of FIGS. 9 and 12.
  • Part (a) of FIG. 17 shows the relationships between the gate voltages Vgs applied to the gate electrodes of the reference cell RC and the memory cell MC (horizontal axis) and the currents Ids which flow between the source and drain of the cells RC and MC (vertical axis), respectively, at time t(a) of FIG. 16, i.e., before the potential of the memory array normal word line MWL or the memory array redundant word line ReWL which was set in FIG. 16 reaches the predetermined voltage.
  • Part (b) of FIG. 17 shows the relationships between the gate voltages Vgs (horizontal axis) and the currents Ids which flow between the source and drain of the cells RC and MC (vertical axis), respectively, at time t(b) of FIG. 16, i.e., after the potential of the memory array normal word line MWL or the memory array redundant word line ReWL which was set in FIG. 16 has reached the predetermined voltage.
  • the voltage VgsR of the reference cell word line RWL which is applied to the reference cell RC is generally at the predetermined voltage.
  • the gate voltage VgsM of the memory array normal word line MWL (or the memory array redundant word line ReWL) applied to the gate of the memory cell MC, from which data is to be read is lower than the word line voltage VgsR applied to the reference cell RC (t(a); VgsR>VgsM).
  • the difference ⁇ Ids(a) between the current IdsR flowing through the reference cell RC and the current IdsM flowing through the memory cell MC becomes as small as possible as shown in part (a) of FIG. 17 .
  • the difference cannot be correctly sensed by the sense amplifier S/A so that the storage device results in an erroneous operation, e.g., unintended data is read out.
  • a semiconductor storage device includes: a memory array including a plurality of memory cells; a reference array including a plurality of reference cells; a decoder section for selecting a memory cell from the memory cells and a reference cell from the reference cells based on address information; and a comparison/output section for comparing a read voltage level from the memory cell selected by the decoder section and a read voltage level from the reference cell selected by the decoder section so as to output a result of the comparison in the form of data, wherein the decoder section simultaneously outputs a selection signal to a word line of the memory cell and a selection signal to a word line of the reference cell.
  • the memory array includes one or more memory cells respectively connected to a normal word line, and one or more memory cells respectively connected to a redundant word line; and the reference array includes a first reference cell which is compared with the memory cells connected to the normal word line, and a second reference cell which is compared with the memory cells connected to the redundant word line.
  • the decoder section when the normal word line is selected, the decoder section selects a first word line connected to the first reference cell simultaneously with selection of the normal-word line; and when the redundant word line is selected, the decoder section selects a second word line connected to the second reference cell simultaneously with selection of the redundant word line.
  • the decoder section includes: a selection determination section for determining which of the normal word line and the redundant word line is to be selected based on address information; a normal word line control section for selecting the normal word line according to the address information when it is determined that the normal word line is to be selected; a redundant word line control section for selecting the redundant word line according to the address information when it is determined that the redundant word line is to be selected: a first reference word line control section for selecting the first word line when it is determined that the normal word line is to be selected; and a second reference word line control section for selecting the second word line when it is determined that the redundant word line is to be selected.
  • the first reference word line control section when it is determined that the normal word line is to be selected, receives a selection signal for the normal word line or a signal indicating that the normal word line is to be selected, and selects the first word line, using as a trigger, the selection signal for the normal word line or the signal indicating that the normal word line is to be selected; and when it is determined that the redundant word line is to be selected, the second reference word line control section receives a selection signal for the redundant word line or a signal indicating that the redundant word line is to be selected, and selects the second word line, using as a trigger, the selection signal for the redundant word line or the signal indicating that the redundant word line is to be selected.
  • a first test signal can be input to the first reference word line control section, and the first reference cell is enforcedly selected in response to the first test signal; and a second test signal can be input to the second reference word line control section, and the second reference cell is enforcedly selected in response to the second test signal.
  • an address transition detection signal which is output in response to detection of a change in the address information, can be input to both the first reference word line control section and the second reference word line control section; and when the address transition detection signal is input, control of reference word lines can be performed.
  • the first reference cell and the second reference cell are set to the same threshold value.
  • the first reference cell and the second reference cell are commonly connected to the same bit line.
  • the load capacitance of a first word line connected to the first reference cell and the load capacitance of a second word line connected to the second reference cell are equal to the load capacitance of the normal word line and the load capacitance of the redundant word line, respectively.
  • the load capacitances of the first word line, the second word line, the normal word line and the redundant word line may be equal.
  • an information apparatus for performing a data read operation using one of the above semiconductor storage devices.
  • the potential of the word line of a reference array rises simultaneously with and in synchronization with a selection signal for selecting the normal word line of the memory array.
  • the potential of the word line of a reference array likewise rises simultaneously with and in synchronization with a selection signal for selecting the redundant word line of the memory array.
  • the load capacitances of the first and second word lines of the reference array are identical to those of the normal word line and redundant word line of the memory array, respectively.
  • the rising edges of the potentials of the word lines occur at the same time, and accordingly, a read access time can be further shortened without causing an erroneous operation.
  • a semiconductor storage device of the present invention can readily be applied to an information apparatus.
  • high-speed data reading can be achieved.
  • the invention described herein makes possible the advantages of providing (1) a semiconductor storage device wherein a read access time can be shortened without causing an erroneous operation, and (2) an information apparatus using such a semiconductor storage device.
  • FIG. 1 is a block diagram showing an exemplary basic structure of a non-volatile semiconductor storage device according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing an exemplary specific structure of the non-volatile semiconductor storage device of FIG. 1 .
  • FIG. 3 is a circuit diagram showing a specific example of the reference word line control circuit used for selection of normal word lines and the reference word line control circuit used for selection of redundant word lines of FIG. 2 .
  • FIG. 4 is a circuit diagram showing another specific example of the reference word line control circuit used for selection of normal word lines and the reference word line control circuit used for selection of redundant word lines of FIG. 2 .
  • FIG. 5 is a block diagram showing a primary part of a memory array word line control circuit and a reference array word line control circuit of the non-volatile semiconductor storage device of FIG. 2 .
  • FIG. 6 is a timing chart illustrating a word line selection operation when a normal word line is selected in the non-volatile semiconductor storage device of FIG. 2 .
  • FIG. 7 is a timing chart illustrating a word line selection operation when a redundant word line is selected in the non-volatile semiconductor storage device of FIG. 2 .
  • FIG. 8 is a block diagram showing an exemplary basic structure of a conventional non-volatile semiconductor storage device.
  • FIG. 9 is a block diagram showing an exemplary specific structure of a conventional non-volatile semiconductor storage device.
  • FIG. 10 is a timing chart illustrating a word line selection operation when a non-redundant, memory array normal word line is selected in the non-volatile semiconductor storage device of FIG. 9 .
  • FIG. 11 is a timing chart illustrating a word line selection operation when a redundant word line is selected in the non-volatile semiconductor storage device of FIG. 9 .
  • FIG. 12 is a block diagram showing another exemplary specific structure of a conventional non-volatile semiconductor storage device.
  • FIG. 13 is a timing chart illustrating a word line selection operation when a non-redundant, memory array normal word line is selected in the non-volatile semiconductor storage device of FIG. 12 .
  • FIG. 14 is a timing chart illustrating a word line selection operation when a redundant word line is selected in the non-volatile semiconductor storage device of FIG. 12 .
  • FIG. 15 shows the control voltage and driving current in each of a reference cell and a memory cell during a data read operation.
  • FIG. 16 illustrates a sensing timing with respect to the rising of the potential of a reference cell word line and the potential of a memory array normal word line (or a memory array redundant word line).
  • FIG. 17 shows the currents flowing through a memory cell and a reference cell at time t(a) in FIG. 16 (part (a) of FIG. 17) and at time t(b) in FIG. 16 (part (b) of FIG. 17 ).
  • FIG. 18 is a block diagram showing a basic structure of an information apparatus including a semiconductor storage device of the present invention.
  • the present invention is applied to a non-volatile semiconductor device used in an information apparatus.
  • FIG. 1 is a block diagram showing an exemplary basic structure of a non-volatile semiconductor storage device according to an embodiment of the present invention.
  • the non-volatile semiconductor storage device 20 includes: a memory cell array RA having a plurality of reference cells RC 0 and RC 1 (hereinafter, referred to as a “reference array RA”); a memory cell array MA (hereinafter, referred to as a “memory array MA”) which is a data storage region and is a main array of the storage device 20 ; a comparison/output section 21 , such as a sense amplifier S/A formed by a differential amplifier; and a decoder section 22 for selecting predetermined memory cell and reference cell based on an input address signal ADD.
  • a memory cell array RA having a plurality of reference cells RC 0 and RC 1
  • a memory cell array MA hereinafter, referred to as a “memory array MA” which is a data storage region and is a main array of the storage device 20
  • a comparison/output section 21 such as a sense amplifier S/A formed by a differential amplifier
  • a decoder section 22 for
  • the reference array RA at least two reference cell word lines used for reading data from the reference array RA, e.g., the word lines RWL 0 and RWL 1 .
  • the reference cell word line RWL 0 and RWL 1 are connected to reference cells RC 0 and RC 1 , respectively.
  • the reference cells RC 0 and RC 1 are commonly connected to the bit line RBL and have the same threshold value.
  • the reference cell word line RWL 0 is activated when a non-redundant memory array normal word line MWL (described later) of the memory array MA is selected
  • the reference cell word line RWL 1 is activated when a memory array redundant word line ReWL (described later) of the memory array MA is selected.
  • the memory array MA forms an information storage region and generally includes a plurality of memory cells MC as storage elements arranged in a matrix along the row and column directions.
  • a memory cell MC 0 for data storage and a redundant memory cell MC 1 which is provided for substituting the memory cell MC 0 are illustrated for the simplicity of description.
  • the memory array normal word line MWL is connected to the gate of the memory cell MC 0
  • the memory array redundant word line ReWL is connected to the gate of the memory cell MC 1 .
  • the drains of the memory cells MC 0 and MC 1 are commonly connected to a bit line MBL.
  • the comparison/output section 21 compares the read voltage (or current) level of the memory cell MC 0 (or MC 1 ) selected by the decoder section 22 with the read voltage (or current) level of the reference cell RC 0 (or RC 1 ) selected by the decoder section 22 , and outputs data which represents a result of the comparison.
  • the sense amplifier S/A applies the same gate voltage to both the memory cell MC 0 (or MC 1 ) and the reference cell RC 0 (or RC 1 ) selected by the decoder section 22 , and amplifies a difference between the values of the electric currents flowing through the memory cell MC 0 (or MC 1 ) and the reference cell RC 0 (or RC 1 ), and outputs the result of amplification in the form of data.
  • the decoder section 22 selects the reference cell word line RWL 0 (first word line) connected to the reference cell RC 0 , together with the memory array normal word line MWL. In the case of selecting the memory array redundant word line ReWL, the decoder section 22 selects the reference cell word line RWL 1 (second word line) connected to the reference cell RC 1 , together with the memory array redundant word line ReWL.
  • the decoder section 22 simultaneously and synchronously outputs selection signals to both the word lines MWL and RWL 0 (or ReWL and RWL 1 ) of the memory cell MC 0 (or MC 1 ) and the reference cell RC 0 (or RC 1 ) so as to raise the word line potentials, such that the timings of reading of data from the memory cell MC 0 (or MC 1 ) and the reference cell RC 0 (or RC 1 ) are concurrent and synchronous.
  • FIGS. 2 through 7 A specific example of a non-volatile semiconductor storage device 20 according to the present invention is now described with reference to FIGS. 2 through 7.
  • FIG. 2 is a block diagram showing an exemplary specific structure of the non-volatile semiconductor storage device 20 of FIG. 1 .
  • a non-volatile semiconductor storage device 30 which is an exemplary specific structure of the non-volatile semiconductor storage device 20 , includes: a reference array RA, a memory array MA, an address transition detection circuit ATD, a normal word line predecoder XPDEC, a normal word line decoder (normal word line control section) XDEC, a normal word line selection signal transition detection circuit XREGS, a redundant word line predecoder XPRDEC, a redundant word line decoder (redundant word line control section) XRDEC, a redundant word line selection signal transition detection circuit XREDS, a bit line decoder YDEC, switching sections YSM and YSR (hereinafter “bit line selection transistors YSM and YSR”), a sense amplifier S/A as the comparison/output section 21 (FIG.
  • the decoder section 22 of FIG. 1 is formed by the following elements shown in FIG.
  • the normal word line predecoder XPDEC the normal word line decoder (normal word line control section) XDEC, the normal word line selection signal transition detection circuit XREGS, the redundant word line predecoder XPRDEC, the redundant word line decoder (redundant word line control section) XRDEC, the redundant word line selection signal transition detection circuit XREDS, the bit line decoder YDEC, the bit line selection transistors YSM and YSR, the reference word line control circuit RREGU used for selection of normal word lines, and the reference word line control circuit RREDU used for selection of redundant word lines.
  • a reference cell word line (first word line) RWL 0 is connected to the gate of the reference cell (first reference cell) RC 0
  • a reference cell word line (second word line) RWL 1 is connected to the gate of the reference cell (second reference cell) RC 1
  • a bit line RBL is commonly connected to the drains of the reference cell RC 0 and RC 1
  • a source line RHS is commonly connected to the sources of the reference cell RC 0 and RC 1 .
  • a memory array normal word line MWL is connected to the gate of the memory cell MC 0
  • a memory array redundant word line ReWL is connected to the gate of the memory cell MC 1
  • a bit line MBL is commonly connected to the drains of the memory cell MC 0 and MC 1
  • a source line MHS is commonly connected to the sources of the memory cell MC 0 and MC 1 .
  • the source lines RHS and MHS are generally maintained at a ground level, but controlled to be at a different level when the storage device is in a special mode, such as a test mode or the like. For example, in a deletion mode, the source lines RHS and MHS are at a high voltage level.
  • the load capacitances of the reference cell word lines RWL 0 and RWL 1 , the memory array normal word line MWL, and the memory array redundant word line ReWL are set to the same (or substantially the same) load capacitance such that the rising times of the potentials of these word lines becomes equal.
  • the address transition detection circuit ATD receives an address signal ADD and a chip enable signal CE#.
  • the address transition detection circuit ATD has a plurality of address signal lines. When at least one of the address signal lines transitions (i.e., when the address signal ADD is input), or when the chip enable signal CE# decreases to the ground level, a required pulse signal, e.g., a word line enable ATD signal SPW, which is also an address transition detection signal, is output to the normal word line predecoder XPDEC, the redundant word line predecoder XPRDEC, the reference word line control circuit RREGU used for selection of normal word lines, and the reference word line control circuit RREDU used for selection of redundant word lines. Further, the address transition detection circuit ATD outputs a sense amplifier enable signal SAEN, as another required pulse signal, to the sense amplifier S/A.
  • SAEN sense amplifier enable signal
  • the normal word line predecoder XPDEC receives the address signal ADD and the word line enable ATD signal SPW as well as a redundancy determination signal MD.
  • the normal word line predecoder XPDEC outputs a normal word line selection signal SX based on the received address signal ADD to the normal word line decoder XDEC and the normal word line selection signal transition detection circuit XREGS.
  • the normal word line decoder XDEC is powered by a node voltage HWL for word lines.
  • the normal word line decoder XDEC receives the normal word line selection signal SX from the normal word line predecoder XPDEC, and outputs a voltage to a predetermined memory array normal word line MWL (raises the potential of the word line MWL) according to the normal word line selection signal SX, thereby selecting the predetermined memory array normal word line MWL.
  • the redundant word line predecoder XPRDEC receives the address signal ADD, the word line enabling ATD signal SPW, and a redundant word line address signal BADD.
  • the redundant word line predecoder XPRDEC performs redundancy determination based on the address signal ADD, and outputs a redundancy determination signal MD to the normal word line predecoder XPDEC, and a redundant word line selection signal RX to the redundant word line decoder XRDEC and the redundant word line selection signal transition detection circuit XREDS.
  • the redundant word line predecoder XPRDEC and the normal word line predecoder XPDEC forms a selection determination section.
  • the selection determination section determines based on the address signal ADD which of the predetermined memory array normal word line MWL and the memory array redundant word line ReWL is to be selected.
  • the redundant word line predecoder XPRDEC determines based on the address signal ADD whether or not a memory array normal word line MWL selected based on the normal word line selection signal SX from the normal word line predecoder XPDEC needs to be replaced with the predetermined memory array redundant word line ReWL, and only when such replacement is necessary, the redundant word line predecoder XPRDEC issues a redundancy determination signal MD to the normal word line predecoder XPDEC. In response to the redundancy determination signal MD from the redundant word line predecoder XPRDEC, the normal word line predecoder XPDEC cancels the output of the normal word line selection signal SX. On the other hand, the redundant word line predecoder XPRDEC outputs a redundant word line selection signal RX for selecting the memory array redundant word line ReWL.
  • the redundant word line decoder XRDEC is powered by the node voltage HWL for word lines. Further, the redundant word line decoder XRDEC receives a redundant word line selection signal RX from the redundant word line predecoder XPRDEC, and outputs a voltage to a predetermined memory array redundant word line ReWL (raises the potential of the word line ReWL) according to the redundant word line selection signal RX, thereby selecting the predetermined memory array redundant word line ReWL.
  • bit line decoder YDEC One output terminal of the bit line decoder YDEC is connected to a bit line selection gate line RYSEL for reference array.
  • the bit line selection gate line RYSEL is connected to a gate electrode of the bit line selection transistor YSR.
  • the other output terminal of the bit line decoder YDEC is connected to a bit line selection gate line MYSEL for memory array.
  • the bit line selection gate line MYSEL is connected to a gate electrode of the bit line selection transistor YSM.
  • the bit line decoder YDEC performs a decode operation for selecting any reference array bit line RBL and any memory array bit line MBL based on the input address signal ADD.
  • the bit line selection transistors YSR and YSM select, based on a selection signal from the bit line decoder YDEC, any of a plurality of bit lines RBL in the reference array RA and any of a plurality of bit lines MBL in the memory array MA, whereby connecting the selected bit lines RBL and MBL respectively to the input terminals of the sense amplifier S/A. That is, the bit line selection transistor YSR connects an end of any of the bit lines RBL of the reference array RA to one of the input terminals of the sense amplifier S/A.
  • the bit line selection transistor YSM connects an end of any of the bit lines MBL of the memory array MA to the other input terminal of the sense amplifier S/A.
  • the sense amplifier S/A is activated in response to receipt of the sense amplifier enable signal SAEN from the address transition detection circuit ATD, and outputs a result of a sensing operation through a line SAOUT. That is, the sense amplifier S/A amplifies a difference between the values of the electric currents flowing through the memory cell MC 0 (or MC 1 ) and the reference cell RC 0 (or RC 1 ), and outputs the result of amplification in the form of data.
  • the reference word line control circuit RREGU which will be described later in detail with reference to FIGS.
  • the reference word line control circuit RREDU used for selection of redundant word lines receives: the node voltage HWL for word lines; the word line enabling ATD signal SPW; the test control signal STEN; a redundant word line selection control signal SDR for controlling the memory array redundant word line ReWL of the memory array MA; and a test word line selection signal SD 1 , which is another enforced selection signal used in a test.
  • the reference word line control circuit RREDU which will be described later in detail with reference to FIGS. 3 and 4, raises the potential of the reference cell word line RWL 1 based on the redundant word line selection control signal SDR which is input when the memory array redundant word line ReWL of the memory array MA is selected, so as to select the reference cell word line RWL 1 .
  • FIG. 3 is a circuit diagram showing a specific example (inverter-type word line driver) of the reference word line control circuit RREGU and the reference word line control circuit RREDU of FIG. 2 .
  • the upper part in the broken line box represents the reference word line control circuit RREGU 1 used for selection of normal word lines
  • the lower part in the broken line box represents the reference word line control circuit RREDU 1 used for selection of redundant word lines.
  • the reference word line control circuit RREGU 1 used for selection of normal word lines is formed by an inverter C 0 , an AND logical circuit C 1 , a P-type transistor P 0 , N-type transistors N 0 -N 3 , and a word line drive inverter DRV 0 .
  • the reference word line control circuit RREDU 1 used for selection of redundant word lines is formed by an inverter C 0 ′, an AND logical circuit C 1 ′, a P-type transistor P 0 ′, N-type transistors N 0 ′-N 3 ′, and a word line drive inverter DRV 1 .
  • the resistance of the P-type transistor P 0 (or P 0 ′) is set to a very high resistance value.
  • all of the N-type transistors N 0 -N 2 (or N 0 ′-N 2 ′) which are serially connected to the drain side of the P-type transistor P 0 (or P 0 ′) are ON, or when only the N-type transistor N 3 (or N 3 ′) is ON, an input node SX 0 (or SX 1 ) of the word line drive inverter DRV 0 (or DRV 1 ) is decreased to the ground level, and the potential of the reference cell word line RWL 0 (or RWL 1 ) rises.
  • reference marks in parentheses denote elements used when the reference word line control circuit RREDU 1 used for selection of redundant word lines is activated.
  • Each of the reference word line control circuit RREGU 1 used for selection of normal word lines and the reference word line control circuit RREDU 1 used for selection of redundant word lines receives the node voltage HWL for word lines, the test control signal STEN, and the word line enabling ATD signal SPW.
  • the reference word line control circuit RREGU 1 used for selection of normal word lines further receives the test word line selection signal (first test signal) SD 0 and the normal word line selection control signal SDM.
  • the reference word line control circuit RREDU 1 used for selection of redundant word lines further receives the test word line selection signal (second test signal) SD 1 and the redundant word line selection control signal SDR.
  • the test control signal STEN is zero (low level) when data is read from a memory cell. Due to the AND logical circuit C 1 (or C 1 ), the N-type transistor N 3 (or N 3 ′) is OFF regardless of the output state of the test reference word line selection signal SD 0 (or SD 1 ). On the other hand, the N-type transistors N 0 and N 0 ′ are ON due to the operation of the inverters C 0 and C 0 ′.
  • the word line enabling ATD signal SPW is at a high level (supply voltage level) when data is read from a memory cell, and therefore, both the N-type transistors N 1 and N 1 ′ are ON.
  • the normal word line selection control signal SDM is at high level, and therefore, the N-type transistor N 2 is ON.
  • the node SX 0 is decreased to the ground level, and a selection signal is output from the word line drive inverter DRV 0 to the reference cell word line RWL 0 , whereby the potential of the reference cell word line RWL 0 rises.
  • the redundant word line selection control signal SDR is at high level, and therefore, the N-type transistor N 2 ′ is ON.
  • the node SX 1 is decreased to the ground level, and a selection signal is output from the word line drive inverter DRV 1 to the reference cell word line RWL 1 , whereby the potential of the reference cell word line RWL 1 rises.
  • test control signal STEN In a test mode, i.e., in the case where a reference cell is manually and enforcedly accessed, the test control signal STEN is 1 (high level).
  • the N-type transistors N 0 and N 0 ′ are OFF due to the operation of the inverters C 0 and C 0 ′. Therefore, control cannot be exerted over reading of data regardless of the states of the word line enabling ATD signal SPW, the normal word line selection control signal SDM, and the redundant word line selection control signal SDR.
  • the test reference word line selection signals SD 0 and SD 1 transition according to the input address signal ADD.
  • the test reference word line selection signal SD 0 is 1, the N-type transistor N 3 is turned ON so that the node SX 0 is decreased to the ground level. Accordingly, a selection signal is output from the word line drive inverter DRV 0 to the reference cell word line RWL 0 , whereby the potential of the reference cell word line RWL 0 rises.
  • the test reference word line selection signal SD 1 is 1
  • the N-type transistor N 3 ′ is turned ON so that the node SX 1 is decreased to the ground level. Accordingly, a selection signal is output from the word line drive inverter DRV 1 to the reference cell word line RWL 1 , whereby the potential of the reference cell word line RWL 1 rises.
  • the word line driver is an inverter-type driver where the P-type transistors P 0 and P 0 ′ are used as high-resistance elements, but the present invention is not limited thereto.
  • the present invention can be implemented with a different type of word line driver.
  • a latch-type word line driver of FIG. 4 which is different from the inverter-type word line driver of FIG. 3, may be employed. Control of reference word line decoding with such a latch-type word line driver will be described below with reference to FIG. 4 .
  • FIG. 4 is a circuit diagram showing another specific example (latch-type word line driver) of the reference word line control circuit RREGU and the reference word line control circuit RREDU of FIG. 2 .
  • the upper part in the broken line box represents the reference word line control circuit RREGU 2 used for selection of normal word lines
  • the lower part in the broken line box represents the reference word line control circuit RREDU 2 used for selection of redundant word lines.
  • the reference word line control circuit RREGU 2 used for selection of normal word lines is formed by an inverter C 0 , an AND logical circuit C 1 , an NOR circuit C 2 , P-type transistors P 0 and P 1 , N-type transistors N 0 -N 4 , and a word line drive inverter DRV 0 .
  • the reference word line control circuit RREDU 2 used for selection of redundant word lines is formed by an inverter C 0 ′, an AND logical circuit C 1 ′, an NOR circuit C 2 ′, P-type transistors P 0 ′ and P 1 ′, N-type transistors N 0 ′-N 4 ′, and a word line drive inverter DRV 1 .
  • Each of the reference word line control circuit RREGU 2 used for selection of normal word lines and the reference word line control circuit RREDU 2 used for selection of redundant word lines receives the node voltage HWL for word lines, the test control signal STEN, and the word line enabling ATD signal SPW.
  • the reference word line control circuit RREGU 2 used for selection of normal word lines further receives the test reference word line selection signal SD 0 and the normal word line selection control signal SDM.
  • the reference word line control circuit RREDU 2 used for selection of redundant word lines further receives the test reference word line selection signal SDI and the redundant word line selection control signal SDR.
  • the test control signal STEN is zero (low level) when data is read from a memory cell. Due to the AND logical circuit C 1 (or C 1 ′), the N-type transistor N 4 (or N 4 ′) is OFF regardless of the output state of the test reference word line selection signal SD 0 (or SD 0 ′). On the other hand, the N-type transistors N 1 and N 1 ′ are ON due to the operation of the inverters C 0 and C 0 ′.
  • the word line enabling ATD signal SPW is at a high level (supply voltage level) when data is read from a memory cell, and therefore, both the N-type transistors N 2 and N 2 ′ are ON.
  • the normal word line selection control signal SDM When the memory array normal word line MWL is selected, the normal word line selection control signal SDM is at high level, and therefore, the N-type transistor N 3 is ON. Accordingly, the node SX 0 is decreased to the ground level, and the P-type transistor P 0 is turned ON, whereby the node SY 0 is increased to a high voltage HWL level for word lines, and the P-type transistor P 1 is turned OFF. Since the normal word line selection control signal SDM is at high level, the N-type transistor N 0 is OFF due to the operation of the NOR circuit C 2 . Thus, the node SY 0 is not decreased to the ground level, and therefore, a through current is not produced.
  • the node SX 1 is decreased to the ground level for the same reason as described above, and a selection signal is output from the word line drive inverter DRV 1 to the reference cell word line RWL 1 , whereby the potential of the reference cell word line RWL 1 rises.
  • test control signal STEN is 1 (high level).
  • the N-type transistors N 1 and N 1 ′ are OFF due to the operation of the inverters C 0 and C 0 ′. Therefore, control cannot be exerted over reading of data regardless of the output states of the word line enabling ATD signal SPW, the normal word line selection control signal SDM, and the redundant word line selection control signal SDR.
  • the test reference word line selection signals SD 0 and SD 1 transition according to the input address signal ADD.
  • the test reference word line selection signal SD 0 is 1
  • the N-type transistor N 4 is turned ON so that the node SX 0 is decreased to the ground level.
  • the P-type transistor P 0 is turned ON
  • the P-type transistor P 1 is turned OFF for the same reason as described above.
  • the test reference word line selection signal SD 0 is 1 (high level)
  • the N-type transistor N 0 is OFF due to the operation of the AND logical circuit C 1 and the NOR circuit C 2 .
  • the potential of the reference cell word line RWL 0 rises.
  • the test reference word line selection signal SD 1 is 1 (high level)
  • the N-type transistor N 4 ′ is turned ON while the N-type transistor N 0 ′ is turned OFF, and the P-type transistor P 0 ′ is turned ON while the P-type transistor P 11 is turned OFF.
  • the node SX 1 is decreased to the ground level, and the potential of the reference word line RWL 1 rises.
  • the circuitry including two reference cell word lines RWL 0 and RWL 1 can readily be controlled with a simple circuit structure and without depending on the type of a word line driver. Further, even if the number of reference cell word lines is 3 or more, a control circuit of the present invention can be implemented by extending the above-described circuit structure example.
  • the above-described circuit structures illustrated in FIGS. 3 and 4 are merely examples of the present invention. According to the present invention, any circuit structure may be employed so long as the above-described features of the circuit which are necessary for implementing the present invention are provided.
  • the normal word line selection signal transition detection circuit XREGS and the redundant word line selection signal transition detection circuit XREDS of FIG. 2 and a method of selecting among a memory array normal word line (or a memory array redundant word line) and a reference cell word line for reading data from a memory cell, are described in detail with reference to FIG. 5 .
  • FIG. 5 is a block diagram showing a primary part of a memory array/reference array word line control circuit of the non-volatile semiconductor storage device of FIG. 2 .
  • the normal word line predecoder XPDEC transmits a normal word line selection signal SX to the normal word line decoder XDEC through a group of 2 n normal word line selection signal lines.
  • the normal word line decoder XDEC raises the potential of a desired main memory normal word line MWL based on the normal word line selection signal SX.
  • the normal word line selection signal transition detection circuit XREGS detects this transition so as to output the normal word line selection control signal SDM to the reference word line control circuit RREGU which is used for selecting normal word lines.
  • the normal word line selection control signal SDM indicates whether any one of the memory array normal word lines MWL is selected.
  • the reference word line control circuit RREGU raises the potential of the reference cell word line RWL 0 .
  • the number of signal lines, i (where i is a natural number), included in the signal line group for transmitting the normal word line selection control signal SDM may be smaller than the number of signal lines, 2 n , included in the signal line group for transmitting the normal word line selection signal SX.
  • the normal word line selection control signal SDM which indicates selection of the memory array normal word lines MWL is input from the normal word line selection signal transition detection circuit XREGS to the reference word line control circuit RREGU, whereby the reference word line control circuit RREGU raises the potential of the reference cell word line RWL 0 .
  • the present invention is not limited to such a structure.
  • the normal word line selection signal SX may be directly input to the reference word line control circuit RREGU through a signal line group including 2 n signal lines, whereby the reference word line control circuit RREGU raises the potential of the reference cell word line RWL 0 .
  • the signal line group for transmitting the normal word line selection signal SX may include only one signal line or a plurality of signal lines in consideration of the structure and layout area of the reference word line control circuit RREGU.
  • the number of signal lines can be considerably reduced when the normal word line selection signal transition detection circuit XREGS is provided, as compared with when the normal word line selection signal SX is directly input to the reference word line control circuit RREGU through a signal line group including 2 n signal lines without providing the normal word line selection signal transition detection circuit XREGS.
  • the address signal ADD used for selection of word lines is also input to the redundant word line predecoder XPRDEC.
  • the redundant word line predecoder XPRDEC outputs a redundant word line selection signal RX to the redundant word line decoder XRDEC, and further outputs a redundancy determination signal MD, which indicates whether or not a normal word line is to be replaced with a redundant word line, to the normal word line predecoder XPDEC.
  • a redundant word line selection signal RX to the redundant word line decoder XRDEC
  • MD redundancy determination signal
  • the number of signal lines included in a signal line group for transmitting the redundant word line selection signal RX is m (where m is a natural number).
  • the number “m” is equal to the number of redundant word lines.
  • This signal line group is connected to the redundant word line decoder XRDEC.
  • the redundant word line decoder XRDEC raises the potential of a desired memory array redundant word line ReWL based on the redundant word line selection signal RX transmitted through the above signal line group.
  • the redundant word line selection signal transition detection circuit XREDS detects this transition so as to output the redundant word line selection control signal SDR to the reference word line control circuit RREDU which is used for selecting redundant word lines.
  • the redundant word line selection control signal SDR indicates that any of the memory array redundant word lines ReWL is selected.
  • the reference word line control circuit RREDU raises the potential of the reference cell word line RWL 1 .
  • the number of signal lines, j (where j is a natural number), included in the signal line group for transmitting the redundant word line selection control signal SDR may be smaller than the number of signal lines, m, included in the signal line group for transmitting the redundant word line selection signal RX.
  • the redundant word line selection control signal SDR which indicates selection of the memory array redundant word lines ReWL is input from the redundant word line selection signal transition detection circuit XREDS to the reference word line control circuit RREDU, whereby the reference word line control circuit RREDU raises the potential of the reference cell word line RWL 1 .
  • the present invention is not limited to such a structure.
  • the redundant word line selection signal RX may be directly input to the reference word line control circuit RREDU through a signal line group including m signal lines, whereby the reference word line control circuit RREDU raises the potential of the reference cell word line RWL 1 .
  • the signal line group for transmitting the redundant word line selection signal RX may include only one signal line or a plurality of signal lines in consideration of the structure and layout area of the reference word line control circuit RREDU.
  • the number of signal lines can be considerably reduced when the redundant word line selection signal transition detection circuit XREDS is provided, as compared with when the redundant word line selection signal RX is directly input to the reference word line control circuit RREDU through a signal line group including m signal lines without providing the redundant word line selection signal transition detection circuit XREDS.
  • the normal word line selection signal transition detection circuit XREGS detects a transition of the normal word line selection signal SX and then outputs the normal word line selection control signal SDM to the reference word line control circuit RREGU which is used for selection of normal word lines.
  • the normal word line selection signal transition detection circuit XREGS is provided, there is a concern that the output timing of the normal word line selection control signal SDM is delayed with respect to that of the normal word line selection signal SX, and accordingly, a time difference is caused between the rising times of the potential of the reference cell word line RWL 0 and the potential of the memory array normal word line MWL.
  • the redundant word line selection signal transition detection circuit XREDS detects a transition of the redundant word line selection signal RX and then outputs the redundant word line selection control signal SDR to the reference word line control circuit RREDU which is used for selection of redundant word lines.
  • the redundant word line selection signal transition detection circuit XREDS is provided, the output timing of the redundant word line selection control signal SDR is delayed with respect to that of the redundant word line selection signal RX.
  • FIG. 6 shows, from the top to the bottom of FIG. 6, supply voltage VCC; the node voltage HWL for word lines; a chip enabling signal CE# which is a control signal for activating the storage device; an output enabling signal OE# which is a control signal for permitting data output; the word line enable ATD signal SPW which is output from an address transition detection circuit ATD; the normal word line selection control signal SDM; the redundant word line selection control signal SDR; the potential of the reference cell word line RWL 0 ; the potential of the reference cell word line RWL 1 ; the normal word line selection signal SX; the potential of the memory array normal word line MWL; and the potential of the memory array redundant word line ReWL.
  • the chip enabling signal CE# and the output enabling signal OE# are at the ground level, a data read operation can be performed.
  • the node voltage HWL for word lines begins to rise at time t 1 .
  • the non-volatile semiconductor storage device 30 such as a flash EEPROM, is in a data readable state. That is, in this state, data can be read out from the storage device 30 by decreasing the chip enabling signal CE# to the ground level.
  • the word line enable ATD signal SPW rises in response to falling of the chip enabling signal CE#.
  • the normal word line predecoder XPDEC raises the normal word line selection signal SX and outputs this raised signal SX to the normal word line decoder XDEC and the normal word line selection signal transition detection circuit XREGS.
  • the normal word line decoder XDEC begins to raise the potential of the predetermined memory array normal word line MWL.
  • the normal word line selection signal transition detection circuit XREGS detects a transition of the normal word line selection signal SX (high level voltage), and then outputs the normal word line selection control signal SDM to the reference word line control circuit RREGU which is used for selection of normal word lines.
  • the reference word line control circuit RREGU detects that the normal word line selection control signal SDM reaches the supply voltage level, and begins to raise the potential of a predetermined reference cell word line RWL 0 .
  • the operation time of the normal word line selection signal transition detection circuit XREGS is compensated for by the wire capacitance of the word lines to some extent, and therefore, the rise timing of the predetermined potential of the reference cell word line RWL 0 and the rise timing of the predetermined memory array normal word line MWL occur at substantially the same time.
  • the potential of the reference cell word line RWL 0 is raised in response to a trigger signal, i.e., the normal word line selection signal SX which is used for selecting the memory array normal word line MWL or the normal word line selection control signal SDM which indicates selection of the memory array normal word lines MWL, whereby a difference in the rise timings of both the potential of the reference cell word line RWL 0 and the potential of the memory array normal word line MWL can be eliminated as much as possible to a negligible level, while the load capacitances of the reference cell word line RWL 0 and the memory array normal word line MWL become equal to each other.
  • the sense amplifier S/A commits erroneous reading is considerably reduced even at the start of a data read operation.
  • the timing of the start of a data read operation occurs earlier, and as a result, the data read speed can be further increased without causing erroneous reading of data.
  • a data read operation performed when a redundant word line is selected is described with reference to the timing chart of FIG. 7 .
  • a redundancy determination signal MD and a redundant word line selection signal RX are considered in addition to the various signals described above, and a redundant word line is considered in place of the memory array normal word line MWL.
  • the operation from time t 0 through time t 3 is totally the same as that described in FIG. 6, and therefore, the description thereof is herein omitted.
  • the following description begins with time t 4 .
  • the normal word line selection signal SX rises to the supply voltage level at time t 4 .
  • the normal word line selection signal transition detection circuit XREGS detects the transition of the normal word line selection signal SX (high level voltage) so as to raise the normal word line selection control signal SDM. In response to this operation, both the reference cell word line RWL 0 and the memory array normal word line MWL begin to rise.
  • the redundancy determination signal MD is output from the redundant word line predecoder XPRDEC to the normal word line predecoder XPDEC at time t 4 .
  • Both the normal word line selection signal SX and the normal word line selection control signal SDM which indicates selection of a normal word line decrease to a low level.
  • the reference cell word line RWL 0 and the potential of the memory array normal word line MWL transition to the ground level.
  • the redundant word line predecoder XPRDEC outputs the redundant word line selection signal RX to the redundant word line decoder XRDEC and the redundant word line selection signal transition detection circuit XREDS.
  • the redundant word line selection signal transition detection circuit XREDS detects a transition of the redundant word line selection signal RX (high level voltage) and outputs the redundant word line selection control signal SDR to the reference word line control circuit RREDU.
  • the reference word line control circuit RREDU begins to raise the potential of the reference cell word line RWL 1 in response to the rising of the redundant word line selection control signal SDR.
  • the redundant word line decoder XRDEC begins to raise the potential of the predetermined memory array redundant word line ReWL in response to the rising of the redundant word line selection signal RX.
  • the memory array normal word line MWL is canceled and switched to the predetermined memory array redundant word line ReWL.
  • the normal word line predecoder XPDEC undesirably issues the normal word line selection signal SX while the redundant word line predecoder XPRDEC is considering whether the predetermined memory array normal word line MWL is switched to the predetermined memory array redundant word line ReWL based on the address signal ADD, and accordingly, a certain length of time is required for canceling the normal word line selection signal SX by the redundancy determination signal MD.
  • both the reference cell word line RWL 1 and the memory array redundant word line ReWL fall to the ground level at time t 7 .
  • the normal word line selection signal SX is generally canceled after a redundancy determination process is completed, and thereafter, selection of redundant word lines is performed.
  • the rise timing of the potential of the memory array redundant word line ReWL is inevitably delayed with respect to the rise timing of the potential of the predetermined memory array normal word line MWL. Therefore, in the case of using a conventional reference word line control method, a considerable time difference is produced between the rise timing of the potential of the reference cell word line RWL and the rise timing of the potential of the memory array redundant word line ReWL.
  • a delay time produced by replacement of the memory array normal word line MWL with the memory array redundant word line ReWL is compensated for by performing similar replacement in the reference array RA among a plurality of reference cell word lines RWL (in the above example, two reference cell word lines RWL 0 and RWL 1 ). That is, a selection determination section formed by the normal word line predecoder XPDEC and the redundant word line predecoder XPRDEC determines which of the memory array normal word line MWL and the memory array redundant word line ReWL is to be selected based on address information.
  • the normal word line decoder XDEC selects the memory array normal word line MWL (or the memory array redundant word line ReWL), and at the same time, the reference word line control circuit RREGU which is used for selection of normal word lines (or the reference word line control circuit RREDU which is used for selection of redundant word lines) selects the reference cell word lines RWL 0 (or RWL 1 ).
  • the reference word line control circuit RREGU which is used for selection of normal word lines
  • RREDU which is used for selection of redundant word lines
  • the potential of the reference cell word lines RWL 0 (or RWL 1 ) and the potential of the memory array normal word line MWL (or the memory array redundant word line ReWL) are raised in a synchronous manner.
  • the sensing timing of the sense amplifier S/A is set to occur prior to the rise timing of the word lines by the address transition detection circuit ATD, high speed reading of data can be achieved without causing an erroneous operation.
  • a considerable sensing margin can be obtained for achieving secure data reading.
  • a semiconductor storage device of this embodiment can be readily incorporated in an information apparatus, represented by a cellular telephone terminal or a PDA (personal digital assistant), and in such an information apparatus, a high-speed data reading effect of the present invention can be obtained.
  • an information apparatus represented by a cellular telephone terminal or a PDA (personal digital assistant)
  • a high-speed data reading effect of the present invention can be obtained.
  • character information and image information used in an e-mail system, or the like can be transmitted/received as well as sound information.
  • These information are stored in a non-volatile semiconductor storage device, such as a flash memory, and moreover, the amount of such information to be processed has been increasing along with the development of functions of cellular telephone terminals. Accordingly, there is a growing demand for further increasing the speed of processing such information.
  • a semiconductor storage device of the present invention can be readily incorporated in an information and control code storage section, and satisfy the above-described demands for high-speed information processing.
  • the information apparatus 40 includes: an information and control code storage section; a manipulation input section, such as manipulation keys or the like; a display section for displaying an initial image, results of information processing, or the like, such as a liquid crystal display device; a transmission/reception section for transmitting/receiving information; and a CPU (central processing unit) for performing read/write processing (memory operation) on the information and control code storage section in response to an input manipulation instruction from the manipulation input section based on a predetermined information processing program and relevant data when certain information is transmitted or received, while performing various information processing.
  • a semiconductor storage device of the present invention can readily be employed as the information and control code storage section, and in such a case, a high-speed data read effect of the present invention can be achieved in the information apparatus 40 .
  • the potential of a word line of a reference cell and the potential of a word line of a memory cell from which data is to be read out are raised in a synchronous manner. Even when reading of data is started before the potential of an intended word line reaches a predetermined voltage as in a conventional device, the data read speed can be increased without causing an erroneous operation. Further, due to such an improvement of the data read speed, a considerable sensing margin can be obtained for achieving secure data reading.
  • a first word line (or a second word line) of a reference array and a normal word line (or a redundant word line) of a memory array have the same load capacitance.
  • the rise timings of these word lines are also the same, and as a result, the read access time can be further reduced without causing an erroneous operation.
  • a semiconductor storage device of the present invention can be readily employed in an information apparatus, and in such a case, a high-speed data read effect of the present invention can be achieved in a data read operation of the information apparatus.

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JP5494455B2 (ja) * 2010-12-09 2014-05-14 富士通セミコンダクター株式会社 半導体記憶装置
JP2011151404A (ja) * 2011-03-03 2011-08-04 Spansion Llc 半導体装置
KR102162701B1 (ko) * 2013-07-30 2020-10-07 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 이를 이용하는 반도체 시스템
JP6356837B1 (ja) * 2017-01-13 2018-07-11 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置および読出し方法
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TW200304149A (en) 2003-09-16
DE60223894T2 (de) 2008-10-23
CN1427417A (zh) 2003-07-02
US20030112664A1 (en) 2003-06-19
JP2003187587A (ja) 2003-07-04
SG131754A1 (en) 2007-05-28
JP3983048B2 (ja) 2007-09-26
KR100459604B1 (ko) 2004-12-03
DE60223894D1 (de) 2008-01-17
DE60223894T8 (de) 2009-02-12

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