US20120170364A1 - Method Of Programming A Nonvolatile Memory Device - Google Patents

Method Of Programming A Nonvolatile Memory Device Download PDF

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Publication number
US20120170364A1
US20120170364A1 US13/305,183 US201113305183A US2012170364A1 US 20120170364 A1 US20120170364 A1 US 20120170364A1 US 201113305183 A US201113305183 A US 201113305183A US 2012170364 A1 US2012170364 A1 US 2012170364A1
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program
level cells
level
voltage
msb
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Joon-Suc JANG
Dong-Hun KWAK
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JANG, JOON-SUC, KWAK, DONG-HUN
Publication of US20120170364A1 publication Critical patent/US20120170364A1/en
Priority to US14/274,041 priority Critical patent/US9281069B2/en
Priority to US15/003,072 priority patent/US9818475B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

Definitions

  • Example embodiments relate to nonvolatile memory devices. More particularly, example embodiments relate to methods of programming nonvolatile memory devices including multi-level cells.
  • Memory cells of a nonvolatile memory device may be classified into single level cells (SLCs) that store one bit of data per memory cell and multi-level cells (MLCs) that store more than one bit of data per memory cell.
  • SLCs single level cells
  • MLCs multi-level cells
  • the MLCs may store multiple bits of data by using multiple threshold voltage distributions to represent different states of multi-bit data. For example, two-bit MLCs may use four threshold voltage distributions to represent respective logical states “11”, “10”, “01” and “00”.
  • the threshold voltage distributions of the MLCs must be separated by adequate sensing margins.
  • certain aspects of newer flash memory devices such as increasing integration density, may cause the threshold voltage distributions to widen due to electrical coupling between adjacent memory cells or a program disturb.
  • Some example embodiments provide a method of programming a nonvolatile memory device capable of narrowing threshold voltage distributions.
  • a least significant bit (LSB) program operation is performed to program.
  • LSBs of the multi-bit data in the multi-level cells, and a most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the multi-level cells.
  • MSB pre-program operation is performed on first multi-level cells that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the multi-level cells to the plurality of target program states corresponding to the multi-bit data.
  • the first multi-level cells may be programmed to an intermediate program state corresponding to the highest target program state by applying a one-shot pulse to the first multi-level cells.
  • an incremental step pulse may be applied to the first multi-level cells, and a pre-program verify voltage may be applied to the first multi-level cells to verify whether the first multi-level cells are programmed to an intermediate program state corresponding to the highest target program state.
  • the first multi-level cells may be programmed to a first intermediate program state corresponding to the highest target program state, the first intermediate program state may be divided into a plurality of sections, and the first multi-level cells may be programmed to a second intermediate program state narrower than the first intermediate program state by, for each of the first multi-level cells, increasing a threshold voltage of the first multi-level cell by one of a plurality of different voltage amounts based on which of the plurality of sections the first multi-level cell corresponds to.
  • a first one-shot pulse may be applied to the first multi-level cells.
  • At least one division voltage may be applied to the first multi-level cells to determine which of the plurality of sections each first multi-level cell exists in.
  • the plurality of sections may include a first section, a second section and a third section.
  • a first voltage of low level may be applied to bitlines coupled to the first multi-level cells in the first section
  • a forcing voltage may be applied to bitlines coupled to the first multi-level cells in the second section
  • a second voltage of high level may be applied to bitlines coupled to the first multi-level cells in the third section
  • a second one-shot pulse may be applied to a selected wordline coupled to the first multi-level cells.
  • the first voltage may be a low power supply voltage
  • the second voltage may be a high power supply voltage
  • the forcing voltage may have a voltage level higher than that of the first voltage and lower than that of the second voltage.
  • the second one-shot pulse is applied to the selected wordline such that threshold voltages of the first multi-level cells in the third section may not be substantially increased, and increments of threshold voltages of the first multi-level cells in the second section may be smaller than increments of threshold voltages of the first multi-level cells in the first section.
  • a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the multi-level cells
  • a most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the multi-level cells.
  • an MSB pre-program is performed on first multi-level cells that are to be programmed to at least one target program state among a plurality of target program states
  • an MSB main program operation is performed to program the multi-level cells to the plurality of target program states corresponding to the multi-bit data.
  • the at least one target program state may include a highest target program state among the plurality of target program states.
  • the at least one target program state may include all the plurality of target program states.
  • the multi-level cells may be programmed to a plurality of intermediate program states corresponding to the plurality of target program states by sequentially applying a plurality of one-shot pulses respectively corresponding to the plurality of intermediate program states to the multi-level cells.
  • an incremental step pulse may be applied to the multi-level cells, and a plurality of pre-program verify voltages may be sequentially applied to the multi-level cells to verify whether the multi-level cells are programmed to a plurality of intermediate program states respectively corresponding to the plurality of target program states.
  • the multi-level cells may be programmed to a first plurality of intermediate program states respectively corresponding to the plurality of target program states, each of the first plurality of intermediate program states may be divided into a plurality of sections, and the multi-level cells may be programmed to a second plurality of intermediate program states respectively narrower than the first plurality of intermediate program states by increasing threshold voltages of the multi-level cells by different voltage levels according to the plurality of sections.
  • a method of programming multi-bit data in a plurality of multi-level cells of a nonvolatile memory device may include programming least significant bits (LSBs) of the multi-bit data in the multi-level cells; and programming most significant bits (MSBs) of the multi-bit data in the plurality of multi-level cells, for each of the plurality of multi-level cells, by verifying a threshold voltage of the multi-level cell using a verification voltage of a target voltage level, from among a plurality of target voltage levels, corresponding to the multi-level cell.
  • LSBs least significant bits
  • MSBs most significant bits
  • Programming the MSBs may include performing a MSB pre-program operation, for each of first multi-level cells from among the plurality of multi-level cells, by verifying a threshold voltage of the first multi-level cell using a verification voltage of an intermediate voltage level corresponding to the first multi-level cell, the corresponding intermediate voltage level being lower than the corresponding target voltage level.
  • an MSB main program operation may be performed, for each of the plurality of multi-level cells, by verifying a threshold voltage of the multi-level cell using the verification voltage of the target voltage level that corresponds to the multi-level cell.
  • a method of programming multi-bit data in a plurality of multi-level cells of a nonvolatile memory device may include programming least significant bits (LSBs) of the multi-bit data in the multi-level cells; and performing a most significant bit (MSB) pre-program operation by, for each of first multi-level cells from among the plurality of multi-level cells applying a first programming pulse to the first multi-level cell, determining a threshold voltage region, from among a plurality of threshold voltage regions, to which the first multi-level cell belongs, and applying, to the first multi-level cell, a second programming pulse having a voltage level selected from among a plurality of different voltage levels based on the region from among the plurality of regions to which the first multi-level cell corresponds.
  • MSBs of the multi-bit data may be programmed in the multi-level cells.
  • the method of programming the nonvolatile memory device may reduce the increase in width of each threshold voltage distribution, and may narrow the threshold voltage distributions.
  • FIG. 1 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments.
  • FIG. 2 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • FIG. 3 is a diagram illustrating another example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • FIG. 4 is a diagram illustrating still another example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • FIG. 5 is a diagram illustrating still another example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • FIG. 6 is a diagram illustrating still another example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • FIG. 7 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments.
  • FIG. 8 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 7 .
  • FIG. 9 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments.
  • FIG. 10 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 9 .
  • FIG. 11 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments.
  • FIG. 12 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 11 .
  • FIG. 13 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments.
  • FIG. 14 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 13 .
  • FIG. 15 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments.
  • FIG. 16 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 15 .
  • FIG. 17 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments.
  • FIG. 18 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 17 .
  • FIG. 19 is a diagram for describing a program order of rows of multi-level cells according to example embodiments.
  • FIG. 20 is a block diagram illustrating a nonvolatile memory device according to example embodiments.
  • FIG. 21 is a block diagram illustrating a memory system according to example embodiments.
  • FIG. 22 is a diagram illustrating a memory card including a memory system according to example embodiments.
  • FIG. 23 is a diagram illustrating a solid state drive including a memory system according to example embodiments.
  • FIG. 24 is a diagram illustrating a computing system according to example embodiments.
  • FIG. 1 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments.
  • a least significant bit (LSB) program is performed to program LSBs of the multi-bit data in the multi-level cells (S 110 ).
  • the multi-bit data indicate data of which each has more than one bit
  • the multi-level cells indicate nonvolatile memory cells storing more than one bit of data per memory cell.
  • a first voltage of low level e.g., a low power supply voltage or a ground voltage
  • a second voltage of high level e.g., a high power supply voltage
  • a program voltage may be applied to a selected wordline coupled to the multi-level cells.
  • the LSB program may be performed using an incremental step pulse program (ISPP) method.
  • ISPP incremental step pulse program
  • an incremental step pulse which increases by a predetermined voltage level per program loop, may be applied to the multi-level cells, and verify voltages corresponding to the LSBs of the multi-bit data may be applied to verify whether the LSBs of the multi-bit data are properly programmed in the multi-level cells.
  • a pre-program operation may be further performed before the ISPP operation.
  • the pre-program operation may be referred to as an LSB pre-program, and the ISPP operation may be referred to as an LSB main program.
  • a most significant bit (MSB) program is performed to program MSBs of the multi-bit data in the multi-level cells (S 120 ).
  • the MSB program may include an MSB pre-program and an MSB main program.
  • the MSB pre-program may be performed such that the multi-level cells that are to be programmed to at least one target program state may be programmed to at least one intermediate program state lower than the at least one target program state (S 130 ).
  • the MSB pre-program may be performed on the multi-level cells that are to be programmed to the highest target program state among a plurality of target program states corresponding to the multi-bit data.
  • the MSB pre-program may be performed on all the multi-level cells that are to be programmed to the plurality of target program states.
  • the MSB pre-program may be performed on the multi-level cells that are to be programmed to one or more target program states corresponding to one or more values of the multi-bit data.
  • the MSB main program may be performed such that the multi-level cells are programmed to the target program states corresponding to the multi-bit data (S 150 ).
  • the MSB main program may be performed using an ISPP method.
  • an incremental step pulse which increases by a predetermined voltage level per program loop, may be applied to the multi-level cells, and verify voltages corresponding to the multi-bit data may be applied to verify whether the multi-level cells are properly programmed to the target program states corresponding to the multi-bit data.
  • the MSB main program is performed after the MSB pre-program that programs the multi-level cells to at least one intermediate program state, thereby reducing the increase in width of threshold voltage distributions due to coupling or a disturb.
  • the undesired increase of a threshold voltage distribution of an erase state may be reduced. Accordingly, the threshold voltage distributions of the multi-level cells may be narrowed.
  • FIG. 2 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or a first intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 110 ). For example, if multi-bit data to be programmed in a multi-level cell has an LSB of “1”, the multi-level cell may be programmed to the erase state E 0 by the LSB program. If multi-bit data to be programmed in a multi-level cell has an LSB of “0”, the multi-level cell may be programmed to the first intermediate state IP 1 by the LSB program.
  • An MSB pre-program may be performed such that multi-level cells that are to be programmed to the highest target program state P 3 may be programmed to an intermediate program state P 3 ′ corresponding to the highest target program state P 3 (S 130 ). For example, among the multi-level cells having the first intermediate state IP 1 , threshold voltages of the multi-level cells to be programmed to a second target program state P 2 may not be increased by the MSB pre-program, and threshold voltages of the multi-level cells to be programmed to a third target program state P 3 (i.e., the highest target program state) may be increased by the MSB pre-program.
  • An MSB main program may be performed such that each multi-level cell may have one of the erase state E 0 , a first target program state P 1 , the second target program state P 2 and the target third program state P 3 according to corresponding multi-bit data (S 150 ).
  • a portion of the multi-level cells having the erase state E 0 may be programmed to the first target program state P 1 using a first verify voltage VVRF 1 according to the multi-bit data
  • the multi-level cells having the first intermediate state IP 1 may be programmed to the second target program state P 2 using a second verify voltage VVRF 2
  • the multi-level cells having the intermediate program state P 3 ′ corresponding to the third target program state P 3 may be programmed to the third target program state P 3 using a third verify voltage VVRF 3 .
  • the erase state E 0 , the first target program state P 1 , the second target program state P 2 and the third target program state P 3 may correspond to values of the multi-bit data “11”, “01”, “00” and “10”, respectively.
  • various logic vales of the multi-bit data may be allocated to the respective target states E 0 , P 1 , P 2 and P 3 .
  • An undesired threshold voltage shift of a multi-level cell having the erase state E 0 may be caused mainly by a program disturb and coupling. While multi-level cells coupled to the same wordline as the multi-level cell having the erase state E 0 are programmed to the first and second target program states P 1 and P 2 , the program disturb may occur. In a case where multi-level cells adjacent to the multi-level cell having the erase state E 0 are programmed to the highest target program state P 3 , the coupling may occur. An amount of the threshold voltage shift caused by the program disturb may change depending on a threshold voltage level of the multi-level cell having the erase state E 0 .
  • the threshold voltage of the multi-level cell may be less affected by the program disturb than a multi-level cell having a relatively low threshold voltage.
  • an amount of the threshold voltage shift caused by the coupling may change less, or not at all, even if the threshold voltage level of the multi-level cell having the erase state E 0 changes.
  • the MSB pre-program is performed on the multi-level cells that are to be programmed to the highest target program state P 3 .
  • the multi-level cell having the erase state E 0 may be first affected by the coupling, and then may be later affected by the program disturb. Accordingly, since the multi-level cell is affected by the program disturb after the threshold voltage of the multi-level cell is increased by the coupling, the overall threshold voltage shift of the multi-level cell may be reduced.
  • the multi-level cells to be programmed to the highest target program state P 3 since the multi-level cells to be programmed to the highest target program state P 3 have threshold voltages substantially close to the third verify voltage VVRF 3 corresponding to the highest target program state P 3 by the MSB pre-program, the multi-level cells may be programmed to the highest target program state P 3 by initial program pulses having relatively low voltage levels during the MSB main program. Accordingly, the MSB main program may be rapidly completed, and a width of each target state E 0 , P 1 , P 2 and P 3 may be reduced.
  • FIG. 3 is a diagram illustrating another example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or a first intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 110 ).
  • An MSB pre-program may be performed such that multi level cells that are to be programmed to first through third target program states P 1 , P 2 and P 3 may be programmed to intermediate program states P 1 ′, P 2 ′ and P 3 ′ corresponding to the first through third target program states P 1 , P 2 and P 3 , respectively (S 130 ).
  • multi-level cells to be programmed to the first target program state P 1 may be programmed to the intermediate program state P 1 ′ corresponding to the first target program state P 1
  • multi-level cells to be programmed to the second target program state P 2 may be programmed to the intermediate program state P 2 ′ corresponding to the second target program state P 2
  • multi-level cells to be programmed to the third target program state P 3 may be programmed to the intermediate program state P 3 ′ corresponding to the third target program state P 3 .
  • An MSB main program may be performed such that each multi-level cell may have one of the erase state E 0 , the first target program state P 1 , the second target program state P 2 and the third target program state P 3 according to corresponding multi-bit data (S 150 ).
  • the multi-level cells having the intermediate program state P 1 ′ corresponding to the first target program state P 1 may be programmed to the first target program state P 1
  • the multi-level cells having the intermediate program state P 2 ′ corresponding to the second target program state P 2 may be programmed to the second target program state P 2
  • the multi-level cells having the intermediate program state P 3 ′ corresponding to the third target program state P 3 may be programmed to the third target program state P 3 .
  • a threshold voltage of the memory cell may be undesirably increased by coupling with the adjacent memory cells.
  • the multi-level cells to be programmed to the target program states P 1 , P 2 and P 3 have threshold voltages substantially close to verify voltages VVRF 1 , VVRF 2 and VVRF 3 respectively corresponding to the target program states P 1 , P 2 and P 3 by the MSB pre-program, increments of the threshold voltages of the multi-level cells during the MSB main program may be substantially small. Accordingly, the undesired threshold voltage shift caused by the coupling may be reduced, and the target states E 0 , P 1 , P 2 and P 3 may have narrow widths.
  • the second memory cell may have a threshold voltage close to a third verify voltage VVRF 3 by the MSB pre-program, and an increment of the threshold voltage of the second memory cell during the MSB main program may be substantially small. Accordingly, during the MSB main program, even if the first memory cell is programmed before the second memory cell is programmed, the undesired threshold voltage shift caused by the coupling with the second memory cell may be reduced since an increment of the threshold voltage of the second memory cell is small.
  • FIG. 4 is a diagram illustrating still another example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or a first intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 110 ).
  • An intermediate significant bit (ISB) program (which may also be referred to as a center significant bit (CSB) program) may be performed such that each multi-level cell may have one of the erase state E 0 , a second intermediate state IP 2 , a third intermediate state IP 3 and a fourth intermediate state IP 4 according to an ISB and the LSB of corresponding multi-bit data.
  • the erase state E 0 , the second intermediate state IP 2 , the third intermediate state IP 3 and the fourth intermediate state IP 4 may correspond to the ISB and the LSB “11”, “01”, “00” and “10”, respectively, but not limited thereto.
  • various logic vales of the ISB and the LSB may be allocated to the respective states E 0 , IP 2 , IP 3 and IP 4 .
  • the ISB program may be performed using an ISPP method.
  • an incremental step pulse which increases by a predetermined voltage level per program loop, may be applied to the multi-level cells, and verify voltages may be applied to verify whether the multi-level cells are properly programmed to the second through fourth intermediate states IP 2 , IP 3 and IP 4 .
  • An MSB pre-program may be performed such that the multi level cells that are to be programmed to the highest target program state P 7 may be programmed to an intermediate program state P 7 ′ corresponding to the highest target program state P 7 (S 130 ).
  • threshold voltages of the multi-level cells to be programmed to a sixth target program state P 6 may not be increased by the MSB pre-program, and threshold voltages of the multi-level cells to be programmed to a seventh target program state P 7 (i.e., the highest target program state) may be increased by the MSB pre-program.
  • An MSB main program may be performed such that each multi-level cell may have one of the erase state E 0 , a first target program state P 1 , a second target program state P 2 , a third target program state P 3 , a fourth target program state P 4 , a fifth target program state P 5 , the sixth target program state P 6 and the seventh target program state P 7 according to corresponding multi-bit data (S 150 ).
  • a portion of the multi-level cells having the erase state E 0 may be programmed to the first target program state P 1 using a first verify voltage VVRF 1 according to the multi-bit data
  • the multi-level cells having the second intermediate state IP 2 may be programmed to the second target program state P 2 using a second verify voltage VVRF 2 or the third target program state 93 using a third verify voltage VVRF 3
  • the multi-level cells having the third intermediate state IP 3 may be programmed to the second target program state P 4 using a fourth verify voltage VVRF 4 or the fifth target program state P 5 using a fifth verify voltage VVRF 5
  • the multi-level cells having the fourth intermediate state IP 4 may be programmed to the sixth target program state P 6 using a sixth verify voltage VVRF 6
  • the multi-level cells having the intermediate program state P 7 ′ corresponding to the seventh target program state P 7 may be programmed to the seventh target program state P 7 using a seventh verify voltage VVRF 7 .
  • the erase state E 0 , the first target program state P 1 , the second target program state P 2 , the third target program state P 3 , the fourth target program state P 4 , the fifth target program state P 5 , the sixth target program state P 6 and the seventh target program state P 7 may correspond to the multi-bit data “111”, “011”, “001”, “101”, “100”, “000”, “010” and “110”, respectively, but not limited thereto.
  • various logic vales of the multi-bit data may be allocated to the respective target states E 0 , P 1 , P 2 , P 3 , P 4 , P 5 , P 6 and P 7 .
  • an overall threshold voltage shift of a multi-level cell having the erase state E 0 may be reduced, and a width of each target state E 0 , P 1 , P 2 , P 3 , P 4 , P 5 , P 6 and P 7 may be reduced.
  • FIG. 5 is a diagram illustrating still another example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • LSB program may be performed such that each multi-level cell may have an erase state E 0 or a first intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 110 ).
  • An ISB program may be performed such that each multi-level cell may have one of the erase state E 0 , a second intermediate state IP 2 , a third intermediate state IP 3 and a fourth intermediate state IP 4 according to an ISB and the LSB of corresponding multi-bit data.
  • An MSB pre-program may be performed such that multi level cells that are to be programmed to target program states P 1 , P 2 , P 3 , P 4 , P 5 , P 6 and P 7 may be programmed to intermediate program states P 1 ′, P 2 ′, P 3 ′, P 4 ′, P 5 ′, P 6 ′ and P 7 ′ corresponding to the target program states P 1 , P 2 , P 3 , P 4 , P 5 , P 6 and P 7 (S 130 ).
  • multi-level cells to be programmed to a first target program state P 1 may be programmed to an intermediate program state P 1 ′ corresponding to the first target program state P 1
  • multi-level cells to be programmed to a second target program state P 2 may be programmed to an intermediate program state P 2 ′ corresponding to the second target program state 92
  • multi-level cells to be programmed to a third target program state P 3 may be programmed to an intermediate program state P 3 ′ corresponding to the third target program state P 3
  • multi-level cells to be programmed to a fourth target program state P 4 may be programmed to an intermediate program state P 4 ′ corresponding to the fourth target program state P 4
  • multi-level cells to be programmed to a fifth target program state P 5 may be programmed to an intermediate program state P 5 ′ corresponding to the fifth target program state P 5
  • multi-level cells to be programmed to a sixth target program state P 6 may be programmed to an intermediate program state P 6 ′corresponding to the
  • An MSB main program may be performed such that each multi-level cell may have one of the erase state E 0 , the first target program state P 1 , the second target program state P 2 , the third target program state P 3 , the fourth target program state P 4 , the fifth target program state P 5 , the sixth target program state P 6 and the seventh target program state P 7 according to corresponding multi-bit data (S 150 ).
  • the MSB pre-program since the MSB pre-program is performed on the multi-level cells to be programmed to the target program states P 1 , P 2 , P 3 , P 4 , P 5 , P 6 and P 7 , the undesired threshold voltage shift caused by the coupling may be reduced, and the target states E 0 , P 1 , P 2 , P 3 , P 4 , P 5 , P 6 and P 7 may have narrow widths.
  • the ISB program may include a pre-program and a main program.
  • FIG. 6 is a diagram illustrating still another example of threshold voltage distributions of multi-levels cells programmed by a program method according to example embodiments.
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or a first intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 110 ).
  • An ISB program may be performed such that each multi-level cell may have one of the erase state E 0 , a second intermediate state IP 2 , a third intermediate state IP 3 and a fourth intermediate state IP 4 according to an ISB and the LSB of corresponding multi-bit data.
  • the ISB program may include an ISB pre-program and an ISB main program.
  • the multi-level cells may be programmed to intermediate states IP 2 ′, IP 3 ′ and IP 4 ′respectively corresponding to the second through fourth intermediate states IP 2 , IP 3 and IP 4 .
  • the multi-level cells programmed to the intermediate states IP 2 ′, IP 3 ′ and IP 4 ′ may be further programmed to the second through fourth intermediate states IP 2 , IP 3 and IP 4 , respectively.
  • FIG. 6 illustrates an example where the ISB pre-program is performed on the multi-level cells to be programmed to the second through fourth intermediate states IP 2 , IP 3 and IP 4
  • the ISB pre-program may be performed on multi-level cells to be programmed to one or more intermediate states IP 2 , IP 3 and IP 4 .
  • An MSB pre-program may be performed such that multi level cells to be programmed to target program states P 1 , P 2 , P 3 , P 4 , P 5 , P 6 and P 7 may be programmed to intermediate program states P 1 ′, P 2 ′, P 3 ′, P 4 ′, P 5 ′, P 6 ′ and P 7 ′ corresponding to the target program states P 1 , P 2 , P 3 , P 4 , P 5 , P 6 and P 7 (S 130 ).
  • An MSB main program may be performed such that each multi-level cell may have one of the erase state E 0 , the first target program state P 1 , the second target program state P 2 , the third target program state P 3 , the fourth target program state P 4 , the fifth target program state P 5 , the sixth target program state P 6 and the seventh target program state P 7 according to corresponding multi-bit data (S 150 ).
  • FIGS. 2 and 3 illustrate examples where the multi-level cells store two bits of data per memory cell
  • FIGS. 4 through 6 illustrate examples where the multi-level cells store three bits of data per memory cell
  • the program method according to example embodiments may be also applied to multi-level cells storing four or more bits of data.
  • FIG. 7 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments
  • FIG. 8 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 7 .
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or an intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 210 ).
  • an MSB program may be performed to program MSBs of the multi-bit data in the multi-level cells (S 220 ).
  • the MSB program may include an MSB pre-program and an MSB main program.
  • the MSB pre-program may be performed by applying a one-shot pulse OSP to the multi-level cells that are to be programmed to the highest target program state P 3 (S 230 ).
  • the one-shot pulse OSP may represent a pulse applied once.
  • a first voltage of low level e.g., a low power supply voltage or a ground voltage
  • a second voltage of high level e.g., a high power supply voltage
  • the one-shot pulse OSP may be applied to a selected wordline coupled to the multi-level cells.
  • the multi-level cells to be programmed to the highest target program state P 3 may have an intermediate program state P 3 ′ corresponding to the highest target program state P 3 .
  • An MSB main program may be performed such that each multi-level cell has one of the erase state E 0 , a first target program state P 1 , a second target program state P 2 and the third target program state P 3 according to the multi-bit data (S 250 ).
  • FIG. 9 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments
  • FIG. 10 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 9 .
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or an intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 310 ).
  • an MSB program may be performed to program MSBs of the multi-bit data in the multi-level cells (S 320 ).
  • the MSB program may include an MSB pre-program and an MSB main program.
  • the MSB pre-program may be performed by applying a plurality of one-shot pulses OSP 1 , OSP 2 and OSP 3 to the multi-level cells that are to be programmed to target program states P 1 , P 2 and P 3 (S 330 ).
  • the multi-level cells to be programmed to a first target program state P 1 may be programmed to an intermediate program state P 1 ′ corresponding to the first target program state P 1 by applying a first one-shot pulse OSP 1
  • the multi-level cells to be programmed to a second target program state P 2 may be programmed to an intermediate program state P 2 ′ corresponding to the second target program state P 2 by applying a second one-shot pulse OSP 2
  • the multi-level cells to be programmed to a third target program state P 3 may be programmed to an intermediate program state P 3 ′ corresponding to the third target program state P 3 by applying a third one-shot pulse OSP 3 .
  • the first through third one-shot pulses OSP 1 , OSP 2 and OSP 3 may be sequentially applied.
  • a first voltage of low level may be applied to bitlines coupled to the multi-level cells to be programmed to the first target program state P 1
  • a second voltage of high level may be applied to bitlines coupled to the other multi-level cells
  • the first one-shot pulse OSP 1 may be applied to a selected wordline.
  • the first voltage may be applied to bitlines coupled to the multi-level cells to be programmed to the second target program state P 2
  • the second voltage may be applied to bitlines coupled to the other multi-level cells
  • the second one-shot pulse OSP 2 may be applied to the selected wordline.
  • the first voltage may be applied to bitlines coupled to the multi-level cells to be programmed to the third target program state P 3
  • the second voltage may be applied to bitlines coupled to the other multi-level cells
  • the third one-shot pulse OSP 3 may be applied to the selected wordline.
  • An MSB main program may be performed such that each multi-level cell has one of the erase state E 0 , the first target program state P 1 , the second target program state P 2 and the third target program state P 3 according to the multi-bit data (S 350 ).
  • FIG. 11 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments
  • FIG. 12 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 11 .
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or an intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 410 ).
  • an MSB program may be performed to program MSBs of the multi-bit data in the multi-level cells (S 420 ).
  • the MSB program may include an MSB pre-program and an MSB main program.
  • the MSB pre-program may be performed on the multi-level cells that are to be programmed to the highest target program state P 3 using an ISPP method (S 430 ).
  • a first voltage of low level may be applied to bitlines coupled to the multi-level cells to be programmed to the highest target program state P 3
  • a second voltage of high level may be applied to bitlines coupled to the other multi-level cells
  • an incremental step pulse may be applied to a selected wordline.
  • a pre-program verify voltage VPREVRF By applying a pre-program verify voltage VPREVRF to the selected wordline, it may be verified whether the multi-level cells are properly programmed to the intermediate program state P 3 ′ corresponding to the highest target program state P 3 .
  • the first voltage may be again applied to bitlines coupled to the multi-level cells having threshold voltages lower than the pre-program verify voltage VPREVRF
  • the second voltage may be again applied to bitlines coupled to the other multi-level cells
  • the incremental step pulse that is increased by a step voltage may be again applied to the selected wordline.
  • the pre-program verify voltage VPREVRF may be again applied to the selected wordline.
  • applying the incremental step pulse and applying the pre-program verify voltage VPREVRF may be repeated until the threshold voltages of all the multi-level cells to be programmed to the highest target program state P 3 become equal to or higher than the pre-program verify voltage VPREVRF.
  • the multi-level cells to be programmed to the highest target program state P 3 may have the intermediate program state P 3 ′ corresponding to the highest target program state P 3 .
  • the pre-program verify voltage VPREVRF corresponding to the intermediate program state P 3 ′ may be lower than a verify voltage VVRF 3 corresponding to the highest target program state P 3 . Further, in some embodiments, a voltage level of an initial step pulse of the MSB pre-program may be lower than that of an initial step pulse of an MSB main program.
  • the MSB main program may be performed such that each multi-level cell has one of the erase state E 0 , a first target program state P 1 , a second target program state P 2 and the third target program state P 3 according to the multi-bit data (S 450 ).
  • FIG. 13 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments
  • FIG. 14 is a diagram illustrating an example of threshold voltage distributions of multi-level cells programmed by a program method of FIG. 13 .
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or an intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 510 ).
  • an MSB program may be performed to program MSBs of the multi-bit data in the multi-level cells (S 520 ).
  • the MSB program may include an MSB pre-program and an MSB main program.
  • the MSB pre-program may be performed on the multi-level cells that are to be programmed to target program states P 1 , P 2 and P 3 using an ISPP method (S 530 ).
  • the multi-level cells to be programmed to a first target program state P 1 may be programmed to an intermediate program state P 1 ′ corresponding to the first target program state P 1
  • the multi-level cells to be programmed to a second target program state P 2 may be programmed to an intermediate program state P 2 ′ corresponding to the second target program state P 2
  • the multi-level cells to be programmed to a third target program state P 3 may be programmed to an intermediate program state P 3 ′ corresponding to the third target program state P 3 .
  • pre-programming the memory cells to be programmed to the first through third target program states P 1 , P 2 and P 3 may be simultaneously performed. For example, by applying a single incremental step pulse, pre-programming the memory cells to be programmed to the first through third target program states P 1 , P 2 and P 3 may be performed.
  • the MSB pre-program of the ISPP manner may include a verify step using first through third pre-program verify voltages VPREVRF 1 , VPREVRF 2 and VPREVRF 3 .
  • threshold voltages of the multi-level cells to be programmed to the first target program state P 1 may become equal to or higher than the first pre-program verify voltage VPREVRF 1
  • threshold voltages of the multi-level cells to be programmed to the second target program state P 2 may become equal to or higher than the second pre-program verify voltage VPREVRF 2
  • threshold voltages of the multi-level cells to be programmed to the third target program state P 3 may become equal to or higher than the third pre-program verify voltage VPREVRF 3 .
  • the first through third pre-program verify voltages VPREVRF 1 , VPREVRF 2 and VPREVRF 3 corresponding to the intermediate program states P 1 ′, P 2 ′ and P 3 ′ may be lower than first through third verify voltages VVRF 1 , VVRF 2 and VVRF 3 corresponding to the first through third target program states P 1 , P 2 and P 3 , respectively.
  • a voltage level of an initial step pulse of the MSB pre-program may be lower than that of an initial step pulse of an MSB main program.
  • the MSB main program may be performed such that each multi-level cell has one of the erase state E 0 , the first target program state P 1 , the second target program state P 2 and the third target program state P 3 according to the multi-bit data (S 550 ).
  • FIG. 15 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments
  • FIG. 16 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 15 .
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or an intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 610 ).
  • an MSB program may be performed to program MSBs of the multi-bit data in the multi-level cells (S 620 ).
  • the MSB program may include an MSB pre-program and an MSB main program.
  • the MSB pre-program may include a first pre-program step (S 631 ), a division step (S 633 ), and a second pre-program step (S 635 ).
  • the multi-level cells that are to be programmed to the highest target program state P 3 may be pre-programmed to a first intermediate program state P 3 ′′ corresponding to the highest target program state P 3 by applying a first one-shot pulse OSP 1 to the multi-level cells to be programmed to the highest target program state P 3 (S 631 ).
  • a first voltage of low level may be applied to bitlines coupled to the multi-level cells to be programmed to the highest target program state P 3
  • a second voltage of high level may be applied to bitlines coupled to the other multi-level cells
  • the first one-shot pulse OSP 1 may be applied to a selected wordline.
  • the first intermediate program state P 3 ′′ may be divided into a plurality of sections S 1 , S 2 and S 3 by applying at least one division voltage V 1 and V 2 to the multi-level cells 661 , 662 and 663 programmed to the first intermediate program state P 3 ′′ (S 633 ).
  • the least one division voltage V 1 and V 2 may include a first division voltage V 1 and a second division voltage V 2
  • the first intermediate program state P 3 ′′ may be divided into a first section S 1 including threshold voltages lower than the first division voltage V 1 , a second section S 2 including threshold voltages between the first division voltage V 1 and the second division voltage V 2 , and a third section S 2 including threshold voltages higher than the second division voltage V 2 .
  • the first division voltage V 1 and the second division voltage V 2 By sequentially applying the first division voltage V 1 and the second division voltage V 2 to the selected wordline, it may be determined which of the first through third sections S 1 , S 2 and S 3 each multi-level cell 661 , 662 and 663 pre-programmed to the first intermediate program state P 3 ′′ exist in.
  • the multi-level cells pre-programmed to the first intermediate program state P 3 ′′ may be further pre-programmed to a second intermediate program state P 3 ′ narrower than the first intermediate program state P 3 ′′ by increasing threshold voltages of the multi-level cells by different voltage levels according to the plurality of sections S 1 , S 2 and S 3 (S 635 ).
  • the first voltage of low level may be applied to bitlines coupled to the multi-level cells 661 in the first section S 1
  • a forcing voltage may be applied to bitlines coupled to the multi-level cells 662 in the second section S 2
  • the second voltage of high level may be applied to bitlines coupled to the multi-level cells 663 in the third section S 3 and the other multi-level cells
  • a second one-shot pulse OSP 2 may be applied to the selected wordline.
  • the first voltage of low level may be a low power supply voltage or a ground voltage
  • the second voltage of high level may be a high power supply voltage
  • the forcing voltage may be higher than the first voltage and lower than the second voltage.
  • the forcing voltage may have a voltage level corresponding to a voltage level difference between the first voltage V 1 for separating the first section S 1 and the second section S 2 and the second voltage V 2 for separating the second section S 2 and the third section S 3 .
  • the forcing voltage By the forcing voltage, channel voltages of the multi-level cells 662 in the second section S 2 may be increased, and thus an effective voltage level of the second one-shot pulse OSP 2 may be decreased for the multi-level cells 662 in the second section S 2 . Accordingly, increments of the threshold voltages of the multi-level cells 662 in the second section S 2 may be smaller than those of the multi-level cells 661 in the first section S 1 . Further, since the second voltage of high level is applied to the bitlines coupled to the multi-level cells 663 in the third section S 3 , threshold voltages of the multi-level cells 663 in the third section S 3 may not be increased.
  • the MSB pre-program may be performed on the multi-level cells 661 , 662 and 663 to be programmed to the highest target program state P 3 by applying the first one-shot pulse OSP 1 , by dividing into the plurality of sections S 1 , S 2 and S 3 , and by applying the second one-shot pulse OSP 2 (S 630 ). Since the threshold voltages of the multi-level cells 661 , 662 and 663 are increased by different voltage levels according to the plurality of sections S 1 , S 2 and S 3 , the multi-level cells 661 , 662 and 663 may be pre-programmed to the second intermediate program state P 3 ′ having a narrow width.
  • the MSB main program may be performed such that each multi-level cell has one of the erase state E 0 , a first target program state P 1 , a second target program state P 2 and the third target program state P 3 according to the multi-bit data (S 650 ).
  • FIG. 17 is a flow chart illustrating a method of programming a nonvolatile memory device according to example embodiments
  • FIG. 18 is a diagram illustrating an example of threshold voltage distributions of multi-levels cells programmed by a program method of FIG. 17 .
  • an LSB program may be performed such that each multi-level cell may have an erase state E 0 or an intermediate state IP 1 according to an LSB of corresponding multi-bit data (S 710 ).
  • an MSB program may be performed to program MSBs of the multi-bit data in the multi-level cells (S 720 ).
  • the MSB program may include an MSB pre-program and an MSB main program.
  • the MSB pre-program may include a first pre-program step (S 731 ), a division step (S 733 ), and a second pre-program step (S 735 ).
  • the multi-level cells may be pre-programmed to first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′ corresponding target program states P 1 , P 2 and P 3 by applying a first plurality of one-shot pulses OSP 1 _ 1 , OSP 1 _ 2 and OSP 1 _ 3 to the multi-level cells (S 731 ).
  • the first one-shot pulses OSP 1 _ 1 , OSP 1 _ 2 and OSP 1 _ 3 may have different voltage levels, and may be sequentially applied to a selected wordline.
  • each first intermediate program state P 1 ′′, P 2 ′′ and P 3 ′′ may be divided into a plurality of sections (S 733 ).
  • one first intermediate program state P 1 ′′ corresponding to a first target program state P 1 may be divided into three sections using first and second division voltages V 1 _ 1 and V 2 _ 1
  • another first intermediate program state P 2 ′′ corresponding to a second target program state 92 may be divided into three sections using third and fourth division voltages V 1 _ 2 and V 2 _ 2
  • the other first intermediate program state P 3 ′′ corresponding to a third target program state P 3 may be divided into three sections using fifth and sixth division voltages V 1 _ 3 and V 2 _ 3 .
  • the multi-level cells pre-programmed to the first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′ may be further pre-programmed to second intermediate program states P 1 ′, P 2 ′ and P 3 ′ respectively narrower than the first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′ by increasing threshold voltages of the multi-level cells by different voltage levels according to the plurality of sections (S 735 ).
  • a first voltage of low level may be applied to bitlines coupled to the multi-level cells in first sections of the first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′
  • a forcing voltage may be applied to bitlines coupled to the multi-level cells in second sections of the first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′
  • a second voltage of high level may be applied to bitlines coupled to the multi-level cells in third sections of the first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′.
  • a second plurality of one-shot pulses OSP 2 _ 1 , OSP 2 _ 2 and OSP 2 _ 3 having different voltage levels may be sequentially applied to the selected wordline.
  • Increments of the threshold voltages of the multi-level cells in the second sections of the first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′ may be smaller than those of the multi-level cells in the first sections S 1 of the first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′, respectively. Further, threshold voltages of the multi-level cells in the third sections S 3 of the first intermediate program states P 1 ′′, P 2 ′′ and P 3 ′′ may not be increased.
  • the MSB pre-program may be performed on the multi-level cells by applying the first one-shot pulses OSP 1 _ 1 , OSP 1 _ 2 and OSP 1 _ 3 , by dividing each first intermediate program state P 1 ′′, P 2 ′′ and P 3 ′′ into the plurality of sections, and by applying the second one-shot pulses OSP 2 _ 1 , OSP_ 2 and OSP 2 _ 3 (S 730 ).
  • the threshold voltages of the multi-level cells are increased by different voltage levels according to the plurality of sections, and thus the multi-level cells may be pre-programmed to the second intermediate program states P 1 ′, P 2 ′ and P 3 ′ having narrow widths.
  • the MSB main program may be performed such that each multi-level cell has one of the erase state E 0 , the first target program state P 1 , the second target program state P 2 and the third target program state P 3 according to the multi-bit data (S 750 ).
  • widths of the target states E 0 , P 1 , P 2 and P 3 may be reduced.
  • FIGS. 7 through 18 illustrate examples where multi-level cells store two bits of data
  • the program method according to example embodiments may be also applied to multi-level cells storing three or more bits of data.
  • FIG. 19 is a diagram for describing a program order of rows of multi-level cells according to example embodiments.
  • an MSB program may be performed on multi-level cells coupled to the current wordline.
  • an LSB program for a first wordline WL 1 may be performed, and then an LSB program for a second wordline WL 2 may be performed. After that, an MSB program for the first wordline WL 2 may be performed.
  • Each LSB program and/or each MSB program may include a pre-program and a main program. In some embodiments, the pre-program and the main program may be performed in one sequence.
  • an MSB program for the second wordline WL 2 may be performed.
  • FIG. 20 is a block diagram illustrating a nonvolatile memory device according to example embodiments.
  • a nonvolatile memory device 800 includes a memory cell array 810 , a page buffer unit 820 , a row decoder 830 , a voltage generator 840 and a control circuit 850 .
  • the memory cell array 810 may include multi-level cells coupled to a plurality of wordlines and a plurality of bitlines. Each multi-level cell may store multi-bit data having at least two bits.
  • the non-volatile memory device 800 may be configured to program the multi-bit data in the multi-level cells using, for example, any of the program methods discussed above with respect to FIGS. 1 through 19 .
  • a program operation for the multi-level cells may include an LSB program and an MSB program.
  • the MSB program may include a pre-program and a main program.
  • the pre-program may be performed on multi-level cells to be programmed to at least one program state.
  • the pre-program may be performed on multi-level cells to be programmed to the highest target program state, or may be performed on multi-level cells to be programmed to all program states.
  • the pre-program may be performed by using a one-shot pulse, by using an ISPP, or by increasing threshold voltages according to a plurality of sections. Accordingly, in a program method according to example embodiments, widths of respective target states may be reduced.
  • the page buffer unit 820 may operate as write drivers or sense amplifiers according to operation modes.
  • the page buffer unit 820 may operate as the sense amplifiers in a read mode, and may operate as the write drivers in a write mode.
  • the page buffer unit 820 may include page buffers that are coupled to the bitlines and temporarily store the multi-bit data. Each page buffer may include be coupled to a corresponding bitline.
  • the page buffers may include data storage latches that temporarily store the multi-bit data.
  • the row decoder 830 may select a wordline in response to a row address.
  • the row decoder 830 may apply wordline voltages from the voltage generator 840 to selected and non-selected wordlines.
  • the row decoder 830 may apply a program voltage to the selected wordline, and may apply a pass voltage to the non-selected wordlines.
  • the voltage generator 840 may be controlled by the control circuit 850 to generate the wordline voltages, such as the program voltage, the pass voltage, a pre-program verify voltage, a verify voltage, a read voltage, etc.
  • the control circuit 850 may control the page buffer unit 820 , the row decoder 830 and the voltage generator 840 to program the multi-bit data in the memory cell array 810 .
  • the control circuit 850 may control the page buffer unit 820 , the row decoder 830 and the voltage generator 840 to perform the LSB program, the MSB pre-program and the MSB main program.
  • the control circuit 850 may control the row decoder 830 and the voltage generator 840 to apply the one-shot pulse, the incremental step pulse, the pre-program verify voltage or the verify voltage to the selected wordline.
  • the nonvolatile memory device 800 may perform a pre-program for at least one program state. Accordingly, the multi-level cells of the nonvolatile memory device 800 according to example embodiments may be programmed to target program states having narrow widths.
  • FIG. 21 is a block diagram illustrating a memory system according to example embodiments.
  • a memory system 900 includes a memory controller 910 and a nonvolatile memory device 920 .
  • the nonvolatile memory device 920 includes a memory cell array 921 and a page buffer unit 922 .
  • the page buffer unit 922 may include page buffers that are coupled to bitlines and temporarily store multi-bit data.
  • the memory cell array 921 may include multi-level cells coupled to wordlines and the bitlines.
  • the memory controller 910 and a nonvolatile memory device 920 may be configured to program multi-level cells to have narrow threshold voltage distributions by an LSB program, a pre-program and a main program according to, for example, any of the processes discussed above with reference to FIGS. 1-19 .
  • FIG. 22 is a block diagram illustrating a memory card including memory system according to example embodiments.
  • a memory card 1000 may include a memory controller 1020 and a nonvolatile memory device 1030 .
  • the memory controller 1020 may be, for example, the memory controller 910 discussed above with reference to FIG. 20 .
  • the nonvolatile memory device 1030 may be, for example, the nonvolatile memory device 920 discussed above with reference to FIG. 20 .
  • the memory system 1000 may be implemented as a memory card, such as a multimedia card (MMC), an embedded multimedia card (eMMC), a hybrid embedded multimedia card (hybrid eMMC), a secure digital (SD) card, a micro-SD card, a memory stick, an ID card, a personal computer memory card international association (PCMCIA) card, a chip card, a USB card, a smart card, a compact flash (CF) card, etc.
  • the memory system 1000 may be coupled to the host, such as a desktop computer, a laptop computer, a mobile phone, a smart phone, a music player, a personal digital assistants (PDA), a portable multimedia player (PMP), a digital television, a digital camera, a portable game console, etc.
  • the host such as a desktop computer, a laptop computer, a mobile phone, a smart phone, a music player, a personal digital assistants (PDA), a portable multimedia player (PMP), a digital television, a digital camera, a portable game console, etc.
  • PDA personal digital assistants
  • PMP portable multimedia player
  • FIG. 23 is a diagram illustrating a solid state drive including a memory system according to example embodiments.
  • a memory system 1100 includes a memory controller 1110 and a plurality of nonvolatile memory devices 1120 .
  • the memory system 1100 may be a solid state drive (SSD).
  • the memory controller 1110 may receive data from a host (not shown). The memory controller 1110 may store the received data in the plurality of nonvolatile memory devices 1120 .
  • the plurality of nonvolatile memory devices 1120 may include multi-level cells.
  • the multi-level cells may be programmed to have narrow threshold voltage distributions by an LSB program, a pre-program and a main program.
  • the memory system 1100 may be coupled to the host, such as a mobile device, a mobile phone, a smart phone, a PDA, a PMP, a digital camera, a portable game console, a music player, a desktop computer, a notebook computer, a speaker, a video, a digital television, etc.
  • the host such as a mobile device, a mobile phone, a smart phone, a PDA, a PMP, a digital camera, a portable game console, a music player, a desktop computer, a notebook computer, a speaker, a video, a digital television, etc.
  • the memory controller 1110 may be, for example, the memory controller 910 discussed above with reference to FIG. 20 . Any or all of the nonvolatile memory devices 1120 may be, for example, the nonvolatile memory device 920 discussed above with reference to FIG. 20 .
  • FIG. 24 is a diagram illustrating a computing system according to example embodiments.
  • a computing system 1200 includes a processor 1210 , a memory 1220 , a user interface 1230 and the memory system 900 discussed above with reference to FIG. 20 .
  • the computing system 1200 may further include a modem 1240 , such as a baseband chipset.
  • the processor 1210 may perform various computing functions, such as executing specific software for performing specific calculations or tasks.
  • the processor 1210 may be a microprocessor, a central processing unit (CPU), a digital signal processor, or the like.
  • the processor 1210 may be coupled to the memory 1220 via a bus 1250 , such as an address bus, a control bus and/or a data bus.
  • the memory 1220 may be implemented by a DRAM, a mobile DRAM, a SRAM, a PRAM, a FRAM, a RRAM, a MRAM and/or a flash memory.
  • the processor 1210 may be coupled to an extension bus, such as a peripheral component interconnect (PCI) bus, and may control the user interface 1230 including at least one input device, such as a keyboard, a mouse, a touch screen, etc., and at least one output device, a printer, a display device, etc.
  • the modem 1240 may perform wired or wireless communication with an external device.
  • the nonvolatile memory device 920 may be controlled by a memory controller 910 to store data processed by the processor 1210 or data received via the modem 1240 .
  • the computing system 1200 may further include a power supply, an application chipset, a camera image processor (CIS), etc.
  • the nonvolatile memory devices 920 may include multi-level cells.
  • the multi-level cells may be programmed to have narrow threshold voltage distributions by an LSB program, a pre-program and a main program.
  • At least some example embodiments may be applied to any nonvolatile memory device including multi-level cells, and devices and systems including the nonvolatile memory device.
  • at least some example embodiments may be applied to various electronic devices, such as a memory card, a solid state drive, a desktop computer, a laptop computer, a mobile phone, a smart phone, a music player, a PDA, a PMP, a digital television, a digital camera, a portable game console, etc.

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DE102011055714A1 (de) 2012-07-05
CN107093453A (zh) 2017-08-25
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CN102543192B (zh) 2017-03-01
CN102543192A (zh) 2012-07-04
DE102011055714B4 (de) 2018-09-20
US20160141025A1 (en) 2016-05-19
US9281069B2 (en) 2016-03-08
US9818475B2 (en) 2017-11-14
KR101798013B1 (ko) 2017-11-16
US20140247657A1 (en) 2014-09-04
CN107093453B (zh) 2020-08-18
DE102011055714B8 (de) 2018-11-22
JP5921870B2 (ja) 2016-05-24

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