TWI267864B - Method and device for programming control information - Google Patents

Abstract

Method and device for programming control information, such as a flag, a control flag, a mark, a control mark. The method and device may perform a lower-speed programming of a given cell type in a first area of memory array, confirm a result of the lower-speed programming of given cell type in the first area of memory array, and perform a higher-speed programming of the given cell type in a second area of memory array after confirming the result of the lower-speed programming, wherein an initial programming voltage of the higher-speed programming may be different from that of the lower-speed programming. The first and second programming may be different, for example, the first programming may be a lower-speed operation, such as the writing of data, and the second programming may be a higher-speed operation, such as the writing of control information. The first and second programming methods may also be different, for example, the first programming method may be a programming method that does not permit over-programming and the second programming method may be a programming method that does permit over-programming.

Description

1267864 16693pif.doc IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method and apparatus for programming control information. ^ [Prior Art] Recently, many applications of various applications, such as MASS STORAGE, CODE MEMORY, and other multimedia (MULTIMEDIA) applications, are increasingly needed. More than a high density memory device. Applications that can be stored in large quantities can include MEMORY CARD (eg, used by MOBILE COMPUTER ", solid state memory (SOLID-STATE MEMORY) (eg · robust and / or reliable storage disk) (STORAGE DISK)), digital camera (DIGITAL CAMERA) (for example, for recording still or moving images and sounds), and sound (VOICE) or audio (AUDIO) recording for recording approximate CD (CD) quality sound. (RECORDER).

Code memory applications can include basic input/output systems (BASIC

# INPUT/0UTpUT SYSTEMS) (BIOS) or network (NETWORK) applications (such as memory in a personal computer (PERSONAL COMPUTER), other terminal (TERMINAL), router (ROUTER), or hub (HUB) ), MOBILE PHONE applications (such as CODE and / or DATA), or other ELECTRONIC HANDHELD INFORMATION DEVICE applications (eg personal digital assistant (personal digital) ASSISTANT) (PDA), Palm Work System (PALM OPERATING 1267864 16693pif.doc SYSYTEM) (POS), or PERSONAL COMMUNICATIONS ASSISTANT (PCA)). Typically, a variety of applications for mass storage use lower cost, higher density, and/or better programmed/erased (PR/G) (P/E) CYCLING ENDURANCE memory. The code memory application uses faster random access (RANDOM ACCESS) and/or EXECUTABLE IN PLACE (XIP). Prior art memories may include DYNAMIC RANDOM ACCESS MEMORY (DRAM), STANA RANDOM ACCESS MEMORY

- (SRAM) and NON-VOLATILE MEMORY (NVM). Non-electrical memory can include MASK READ ONLY MEMORY (ROM), ERASABLE PROGRAMMABLE READ ONLY MEMORY (EPROM), and electronic erasable program Read-only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ

• 〇NLY memory) (eeprom), flash memory (FLASH MEMORY) (for example: FLASh ERASE MEMORY (EEPROM), and FERRO-ELECTRIC MEMORY). Sexual memory still does not lose data when power disappears, but usually does not allow random access and is usually slower than VOLATILE MEMORY. We can erase programmable programmable read-only memory by merging (epr〇m) and electronic erasable programmable read-only memory (eepr〇m) to form a flash 1268864 16693pif.doc memory. Flash memory can be NANd or NOR flash memory. In memory, erasing and stylization can be performed by applying different voltages to each flash memory cell. NAND flash memory can include strings (STRING) connected in series (eg, 16 cells). A string can be formed. This string can include one or more string select transistors (STRING SELECT TRANSISTOR). NAND flash memory can have a relatively small "on," ("0N,") cell current ( Cell CURRENT), and thus a relatively slow sensing time (sensing, TIME) ( For example: 10_25ms). NAND flash memory can be sensed by a single page (PAGE UNIT) (for example: 512 bytes (BYTE)), and simultaneously latch this page unit to a page buffer (PAGE BUFFER) ), to perform a job. NAND flash memory can read data from a page buffer latch (pAGE bUFFEr LATCH) at a fairly high speed (for example: 50ns). NAND flash memory can be worn Tunnel (TUNNELING) (for example: F〇Wold_N〇RDHEIM (FN) tunneling) to perform

# PROGRAM AND/OR ERASE operation. Stylized work can include loading a series of data into the page buffer quite quickly (for example: 50ns), where each cell (for example: 512)

The bytes are all stylized at the same time. The erase job may be erased for the block unit (BLOCK UNIT), where several pages (for example, 32 pages of 16K bytes) are erased at the same time.

We can perform reliable Fowluo DeHai (FN) tunneling at about l〇mV/cm, which results in reduced power consumption (p〇WER 1267864 16693pif.doc CONSUMPTION) and reduced temperature dependence (TEMPERATUR DEPENDENCE) More consistent stylization/erase work, and/or easier device/voltage calibration (DEVICE/VOLTAGE SCALING). NAND flash memory staging can utilize the coupling between a gate (GATE) and a channel (CHANNEL). For example, a cell to be programmed may have a larger voltage difference (VOLTAGE DIFFERENCE) between the gate and the channel than the cell that is not intended to be programmed. The NAND flash memory program can also utilize a threshold voltage distribution (THRESHOLD VOLTAGE DISTRIBUTION), an example of which is shown in Figure 1. Figure 1 shows the word line voltage (WORD LINE VOLTAGE) VW0RDLINE (for example: 0 ¥), the read voltage (Sin 8) ¥ 〇 1 ^ ^ ^) ¥ concealed, and unprogrammed (UNPROGRAMMED) (or Erased cell and stylization

Schematic diagram of the relationship between the cell voltage distribution (CEll VOLTAGE DISTRIBUTION) Vth and the like of (PROGRAMMED) cells. In Figure i, the x-axis direction represents the threshold voltage of the STORAGE CELL, and the γ-axis direction represents the number of cells at a definite threshold voltage. Traditionally, the cell voltage distribution Vth is controlled by an incremental step pulse program (ISPREMENT STEP PULSE PR 〇 GRAM) (ISPP). Various examples of the incremental stepping program ISPP are shown in Figures 2A and 2B. Figure 2A shows an example of a prior art incremental stepping pulse program ispp where the pulse width (PULSE WIDTH) and the amplitude (amputude) remain the same. As shown, 'voltage Vq (for example: 18V) is applied during the programization period (programPERI0D) (for example, 3 squeaking) and another voltage Vi (for example, 1.2V) is applied to the verification period (VERIFY pERI〇D) During the period, 1668864 16693pif.doc (for example: 5ps). Figure 2B shows an example of a prior art incremental stepping pulse program ispp where the pulse width remains the same, but the amplitude has been changed. As shown, the electrical MV〇 (eg, 15V) is applied during the first stylized period (eg, 30 nets)' and increments for each successive stylized period (eg, at 0.5V) until the final The voltage (FINAL v0LTAGE) Vn (for example, 19V). Another voltage VK (e.g., 1.2 V) is applied during each verification period (e.g., 5 μδ). In both Figures 2A and 2B, the total duration (1 DURATION) is about 250 ps. The variation of the cell voltage vth and the period of the graph of Fig. 2 are less than the variation of the cell voltage Vth of Fig. 2A and the number of cycles. Figure 3 illustrates the problem of over-provisioning - (OVER-pR 〇 GRAMMING) of a prior art. If the cell threshold voltage Vth is higher than Vread, the normal e-beat operation of the NAND cell string may not be properly performed. The prior art program exists to avoid excessive stylization during the incremental stepping program ISPP. The prior art program also uses a flag (FLAG) or other flag (MARK) to indicate that the NORMAL CELL PROGRAM φ operation has been properly completed. The use of flags or other flags is due to the relatively long programming time of the NAND flash memory (approximately 250μ8 as described above). During such a long stylized time, a power interruption (POWER-OFF) or other similar interruption may occur. A flag or other flag is used to confirm that the stylization has been completed. 4A is an example of a completed flag or other flag (eg, CONFIRM MARK), and FIG. 4B is an example of an unfinished standard stylized work and/or flag or other flag 0 1267864 16693pif.doc In prior art procedures, when performing standard cell stylization or various tasks, a decision is made based on whether the work is completed, and if so, a flag or other flag is written. This flag or other flag can be written to the memory area (SPARE CELL REGION). FIG. 5A illustrates a prior art standard cell stylization and confirmation cell programming (CONFIRM CELL PROGRAM), and a prior art standard cell programming time (NORMAL CELL PROGRAM TIME) and stone ^ cell programming time (CONFIRM) Schematic of CELL PROGRAM TIME). As shown, the standard cell programming time of the prior art and the validation of the monthly package spears are both a stylized cycle and a cycle of verification cycles (LOOP). Figure 5B is a schematic illustration of a prior art standard cell stylization and validation stylized write memory location (MEMORY LOCATION). As shown in Figure 5B, for programmatic writes: 1 page / 1 programmed time = 512 bytes / 1 programmed time == 4k bits / 250ps (200ps - 300ps) = 16·4 bits Yuan / lps. For the confirmation flag write: 1 bit / 1 stylized time = 1 bit / 250ps = 0 · 004 bits / lps 〇 As can be seen from the above, the confirmation flag is written less than the programmed write effectiveness. SUMMARY OF THE INVENTION Embodiments of the present invention are directed to a semiconductor device (SEMICONDUCTOR DEVICE) having a reduced programming time (REDUCED PROGRAM TIME), such as a semiconductor memory device 1268864 16693 pif. doc (SEMICONDUCTOR MEMORY DEVICE), including: Flash memory. Embodiments of the present invention are directed to a PROGRAMMING METHOD with reduced stylized time. Embodiments of the present invention are directed to a memory cell array (MEMORY CELL ARRAY) having reduced stylized time, such as a non-electrical memory cell array. Embodiments of the present invention are directed to a control circuit (C0NTR0L CIRCUIT) having a reduced program time, such as a PROGRAM CONTROL CIRCUIT. In various embodiments, the present invention is directed to a stylized method comprising: executing a program of a lower rate (LOWER-SPEED) of a cell type (CELL TYPE) assigned in a first region of a memory array (MEMORY ARRAY) And confirming the lower rate privateization result of the cell type given in the first region of the memory array, and after confirming the stylization of the lower rate, performing the cell type given in the second region of the memory array is faster • (HIGHER_SPEED) is stylized, where the higher speed stylized initial programmed voltage (INITIAL PROGRAMMING VOLT AGE) is different from the lower stylized initial programmed voltage. In various embodiments, the present invention is directed to a stylized method comprising: performing a first-stylization of a cell type in a first region of a memory using a first stylized method, and confirming that the first region of the memory is in the first region Give the result of the pattern-stylization, and when the first-stylized result is correct, perform this by using a second stylized method different from the first-stylization method.

12 1267864 16693pif.doc The second programming of the cell type given, where the higher-speed stylized initialized voltage is different from the lower stylized initial programmed voltage. Performing a lower-rate stylization of the cell type given in the first region of the non-electric memory cell array, confirming the stylized result of the lower rate of the cell type given in the first region, and when When the result of the lower speed stylization is correct, the non-electric memory cell array is executed in a second region. In each of the embodiments, the present invention is directed to a non-electric memory cell array semiconductor memory. Difficult to set, the towel, the non-electric memory cell array contains - the first region and the second region with the controller

The assigned cell type is a higher speed stylized, where the higher stylized initial stylized voltage is different from the lower rate stylized initial stylized voltage. In various embodiments, the present invention is directed to a semiconductor memory device including a non-electric memory cell array, wherein the non-electric memory cell array includes a first region and a second region. The first area includes a plurality of memory cell strings (MEMORY CELL STRING), where a string includes a plurality of memory cells, and the number of cells to be programmed in the string is smaller than all memory cells in the string, and The threshold voltage of a programmed cell is independent of a Vread voltage level; and a second region includes a plurality of memory cell strings, where all memory cells in the string can be programmed to zero for the present invention. The above and other objects, features and advantages will be apparent from the following description. 13 1267864 16693pif.doc [Embodiment] In the embodiment, the present invention is directed to a programmatic method for writing a flag (FLAG), a control flag (CONTROL FLAG), a flag (MARK), and a control target (CONTROL). MARK), or other methods and apparatus for controlling information (CONTROL INFORMATION), wherein the stylized method is different from the stylized method for writing cell data (CELL DATA). In an embodiment, the present invention is directed to a method and apparatus for writing a flag, a control flag, a flag, a control flag, or other control information in a stylized manner, wherein the stylized method has a flag and a control flag. a more efficient method for marking, marking, controlling, or other control information; and a method and apparatus for writing cellular data in a stylized manner, wherein the stylized method is more efficient. In one embodiment, the present invention is directed to a method and apparatus for writing a flag, control flag, flag, control flag, or other control information in a stylized manner, wherein for this flag, control flag, flag , the control flag, Lu or other control information, the stylization method is faster; and a method and device for writing the cell data in a programmatic manner, wherein the programmatic method is slow. In one embodiment, the present invention is directed to a method and apparatus for writing a flag, a control flag, a flag, a control flag, or other control information in a stylized manner, wherein the stylized method is written The stylized method of incoming data has fewer stylized voltage pulses (PROGRAMMING VOLTAC} £ PULSE). In an embodiment, the invention is directed to a programmatic method of writing 14 1267864 16693pif.doc

Method and apparatus for flagging, controlling flags, flags, control flags, or other control information 'where the stylized method has an initial programmed voltage pulse (INITIAL PROGRAMMING VOLTAGE PULSE) than a stylized method of writing cell data There is also a high initial stylized voltage pulse.

In an embodiment, the present invention is directed to a method and apparatus for writing a flag, control flag, flag, control flag, or other control information in a stylized manner, wherein the stylized method has a higher than written data. The stylized method has a higher initial stylized voltage pulse and fewer stylized voltage pulses. In the embodiment, the present invention is directed to a method and apparatus for writing in different stylized ways in different regions of a cell array. - In an embodiment, the invention is directed to a method and apparatus, where each stylized method is more efficient in terms of the form of the material stored therein. In an embodiment, the present invention is directed to a method and apparatus in which other regions of the cell array are written in a slower stylized manner. In an embodiment, the invention is directed to a method and CYCLE TIME). In the embodiment, the present invention has a longer path/gate for certain regions of the cell array and a shorter program period for the other regions of the cell memory in the embodiment. The present invention is directed to a method and apparatus. Here, 1267864 16693pif.doc is 'over-stylized in certain areas of the cell array, and is not allowed in other areas of the cell memory. 6A, 6B, and 6C are diagrams showing the use of different stylized methods for flags, control flags, targets, control flags, or other control information and cell data, in accordance with an embodiment of the present invention. As shown in FIG. 6A, the method of programming the cell array can start with (4) a relatively low initial voltage, for example: Vpgml, and can include several incremental steps (INCREMENT STEP PULSE), for example: The four increments shown in the 6A towel. In contrast, as shown in Figures 6B and 6C, the method of stylizing flags, control flags, flags, control flags, or other control information can begin with a relatively high initial voltage, such as: Vpgm4 shown in Figure 6β, or Vpgm5 as shown in Figure 6C, and may include fewer incremental stepping pulses, such as an increment as shown in Figure 6B, or as shown in Figure 6C The monkey is added. The method of stylizing cellular data can be viewed as a normal (or slower) stylized party with flags, control flags, flags, control flags, or other control assets. The stylized method can be considered as a faster stylized method. Because the method of staging the cell data has a longer stylized time, as shown in FIGS. 6A to 6C. The method of stylizing flags, control flags, flags, control flags, or other control information has a shorter stylized time. In an embodiment, the stylized method illustrated in FIG. 6A can be regarded as a full incremental step pulse program (FULL ISPP), and the program 16 1267864 16693pif.doc method illustrated in FIG. 6B can be regarded as a partial increment. The stepping pulse program (PARTIA) LISPP), and the stylized method illustrated in Figure 6C can be considered as a one-click (〇NE-SH〇T) stylized method. The Full Incremental Stepping Pulse Program (ISPP) increases the stylized time, reduces or minimizes the Vth dispersion (DISPERSION), and/or reduces or avoids over-staging. Partial incremental stepping (ISPP) and click-to-stylization methods can reduce stylization time, increase cell Vth dispersion, reduce storage performance, and/or increase possible over-programming. In another embodiment, a partial incremental step pulse program (ISPP) and/or a click program can be applied to the cell data. FIG. 7A and FIG. 7B are diagrams showing a comparison between the present invention and the prior art embodiment. Here, the embodiment implements a one-click stylization method. According to the content shown, it can be clear that if the two are implemented as a full incremental step pulse program (ISPP), the standard cell programming time may be the same. However, in the first embodiment of the present invention, this confirms the programmed time of the cell, and thus the entire stylization and time. 'It may be shortened by the use of the example click-to-stylization method. The 'attack' click is equal to the voltage applied to the post-voltage in the fully incremental stepping pulse program _. 6, FIG. 8A and FIG. 8Β are shown as two private diagrams of the method according to the present invention. Figure 8A is a flow diagram of a method of privateizing cell data in accordance with an embodiment of the present invention. The figure 8 is a flow chart of a method for entering a flag, a control flag #, a standard, a control flag, or other control information according to an embodiment of the present invention. An exemplary method of programming cell data as shown in FIG. 8A may include, in steps, receiving a command (COMMAND), such as

17 1267864 16693pif.doc

The sequence data input command (SEQUENTIAL DATA ΙΝ ί gt υ τ COMMAND), and in step 220, the receive address (ADDRESS) 〇 in step 230, the programmatic data can be loaded, and in step 240, the programmatic command can be received (RPOGRAM) COMMAND). In step 250, the method can perform stylization work with a Vpgml word line voltage (WORLD LINE VOLTAGE). At step 260, the method can perform the verification work. At step 270, if successful, the method will be terminated. If not, the flow proceeds to step 280 where the word line voltage will increase by a Δν and then to step 250 to perform the stroke operation with the new word line voltage. As shown in FIG. 8A, an example method of stylizing a flag, a control flag, a flag, a control flag, or other control information may include: receiving a command, such as a sequential data rounding command, in step 610, and in steps 620 'Receive address. In step 63, the data to be programmed can be loaded, and the program command can be received in step 64G'. In step (4), the method can perform stylized work such as the voltage of 70 Vpgm4. In the step series f can perform verification work. In (4) (10), if successful, j will stop the law. If necessary, the ride will proceed to step _, which increases Δν, then proceeds to step, and the new sub 7L line voltage performs stylized work. Figures 9A through 9B are diagrams showing more different stylized methods in accordance with the present invention. Fig. 9α= 吏: (; Figure 6Β combination. Fig. α is basically from Fig. 6Α and 9A and Fig. 9B are basically the combination of Fig. 6A and Fig. 6C. Figurine stepping (PROGRAMMING STEP) 18 1267864 16693pif.doc to add. In contrast, both Figure 9C and Figure 9D are incremented based on the initial voltage (INITIAL VOLTAGE). As shown in Figure 9c, the initial voltage of the second program may be from The final voltage of a program is the same and maintains a constant. In Figure 9D, the initial voltage of the second program may be different from the final voltage from the first program, and may vary by the total amount of the sample represented by ±a or ±. a or ± α may be a fixed voltage or a voltage based on the previous voltage 'eg, the first or last voltage of the first program. FIG. 10A to FIG. FIG. 10A is a schematic diagram of an entire cell array according to an embodiment of the present invention, and FIGS. 10A to 12B are diagrams showing an exemplary cell array region (EXAMPLE CELL ARRAY REGION) according to an embodiment of the present invention. Main area (MAIN REGION) and / or reserved Example of 'writing flags, control flags, flags, control flags, or other control information in the area (SPARE REGION). As shown in Figure 10A, the cell array can be read/written by the control circuit (CONTROL CIRCUIT) Controlled by READ/WRITE CIRCUIT, with /φ or X-DECODER, this hardware is widely known to those skilled in the art. Cell arrays can have two or more array regions ( ARRAY REGION. Figure 10A is a schematic diagram of a cell array including a LOWER SPEED WRITE REGION 110A and a HIGH SPEED WRITE REGION 11 OB. In an embodiment, The lower speed writing area 110A may be a MAIN CELL STORAGE FIELD, and may be programmed in a low-speed stylized version of the standard 19 1267864 16693pif.doc ^, and (4) a fully incremental stepping pulse program (ISPP) In the embodiment, the 'vehicle speed writing area l1〇B can be a SPARE CELL STORAGE FIELD, and can be a faster program. Write in it, can be reduced Incremental stepping pulses (talking) are written in the presentation, can be written into it by click programming, and/or allowed to be over-programmed. As shown in Figure 10B, in one embodiment, the flag can be flagged. The target, control flag, flag, control flag, or other control information (identified by the shadow portion of Figure 1B) is completely written into this lower speed write area u〇A. As shown in FIG. 10C, in another embodiment, the flag, control flag, flag, control flag, or other control information (identified by the shaded portion of FIG. The higher speed is written in the area 11〇B. As shown in FIG. 10D, in another embodiment, flags, control flags, flags, control flags, or other control information (identified by the shaded portion of FIG. 10D) may be written consecutively lower. The speed is written in the area 110A. Be aware that there may be other options as well as including flags, control flags, flags, control flags, and their control information written into successive higher speed write areas 11 (^^\"" Figure 11A A more detailed schematic diagram of a main range (MAIN FIELD) and a reserved range (SPARE FIELD) of an exemplary NAND flash celella array according to an embodiment of the present invention. FIG. 11A is similar to the diagram. i〇A to the main range area (MAIN FIELD REGION) and the reserved area area (SPARE FIELD REGION) shown in the log. As shown in Figure 1, a NAND flash cell array can be several Each block can hold 20 1267864 16693pif.doc Easily obtained by column selector (ROW SELECTOR) and row selector (COLLUMN SELECTOR). Column selector can pass word line (WORD LINE) (WL) The row selector can pass through the BIT LINE (BL). Each square can be divided into two or more groups (GROUP), and the main cell area (MAIN CELL AREA) can be used for main storage (MAIN STORAGE). The SPARE CELL BLOCK is used for control flags and or redundancy. The program operation can be performed by a page unit, which can be a unit of a cell that is usually connected to a common word line (COMMAN WORD LINE). FIG. 11B illustrates an embodiment of the present invention, written A flowchart of an exemplary NAND 'flash cell array. As shown in step 10, the method can include receiving data and an address; and in step 30, enabling the word line (WL). In step 50, the method This may include using a lower speed program to program the received data in the MAIN BLOCK CELL, and in step 70, using a higher speed program, will be located by the enable word line (WL). The selected cell's flag, control flag, flag, control flag, or other control information is programmed. At step 90, the word line (WL) may change and the process returns the word line (WL). Step 30 is to enable the next word line.Figure 12A and Figure 12B are flow diagrams of a more general method of Figure 8B in accordance with other embodiments of the present invention. Figure 12A illustrates a lower speed stylization And then confirmed that this lower speed stylization industry has correctly invented an implementation After the execution of the example, the method of executing the higher speed programming = flow, Fig. 12B is a flow chart of a method for receiving the first data by using the first stylized method, and writing the data to the first memory 21 1267864 16693pif.doc body region and after the stylized method has been confirmed - after the embodiment is correctly executed, the second program = the data of the present invention is used, and the data is written into the second memory region: The second low 逹 解 solution, return to 12G, including the implementation of the financial. In step 140, the method can include checking for the lower speed result, for example, if the mosquito is slower stylized correctly. In step 16G, #Step 14G has determined that this lower speed is correctly and/or fully executed, the method may include performing a higher speed as shown in Figure 12β, in step 13〇, and in another method may include receiving To write in the first-memory area of the "example ^ this 150, this ancient, soil ... ~ version of the armor of the shellfish. In the step of the first - remember tongue 1 column using the first spear presentation method, Write this information into the skirt two "Μ. In step 17G, # in step 15G, it has been determined that the ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ In the second step of the step: 姊 (10), Qing wrote the quasi-capital chart 12 Β narration narrative, the first - shouting method can be the standard stylized standard 4, control miscellaneous, or other financial control faster or the first ― / / The first memory area can be the main block of the cell array, and / / ^ ^ ^, body area can be reserved for the cell array. Just as shown in the present invention - the semiconductor memory device is not considered. As shown in FIG. 13, the semiconductor memory device 1 22 1267864 16693pif.doc, the cell array memory m and the memory drive

The cell array memory shown in Fig. 1GA to Fig. 1GD can write the human area 11GA and the higher speed writing area I: at a lower speed. As mentioned above, the low-speed write area u〇A can be the main cell storage target, which can be written in standard and/or lower-speed programming, and can be written in full incremental step pulse program (ISPP). Among them, and/or not allowed to over-type 3 also - as described above, 'higher-speed writing area Ugb can be reserved cell storage range' can be written in a faster program, which can be reduced in increments The step pulse program (ISPP) is written to it and can be written to it with a click, and/or allowed to be over-programmed. In one embodiment, the 'memory driver 140 may include an X-decoder or column decoder 14 for column control and a Y-decoder- or row decoder for line control, where γ_ The decoder or row decoder includes a page buffer (PAGE BUFFER) 142, a _-gate (Y_gate) 143, and a Din/Dout buffer (Din/Dout BUFFER) 143. Semiconductor memory

The garment 100 can also include the entire control circuit including a program control WORD LINE VOLTAGE GENERATOR 146 and a program termination circuit (Rp 〇 GRAM FINISHED (P/F) CIRCUIT) 145. Program Control 120 includes Status Staging as (STATUS REGISTER)' This status register keeps track of all work. An example word line voltage generator 146 is described in more detail in Figure 14A. Figure 14A is a diagram showing the generation of the word line voltage of Figure 13 in accordance with an embodiment of the present invention. In an embodiment, the word line voltage generator 23 1267864 16693pif.doc 146 may include a SIGNAL CONTROL LOGIC 200, an OSCILLATOR 210, a reference voltage generator (REFERENCE VOLTAGE GENERATOR) 220, and a voltage divider. (VOLTAGE DIVIDER) 230, comparator (COMPARATOR) 240, and charging pump (CHARGE PUMP) 250. As shown, the signal control logic 200 can provide a step signal (STEP SIGNAL), STEP - CNTL [5 · · 0] to the voltage divider 230. The voltage divider 230 can generate a VARIABLE LEVEL SIGNAL Vdvd, which can be supplied to the comparator 240 along with a reference signal (REFERENCE SIGNAL) Vref supplied from the reference voltage generator 220. . The comparator - 240 compares the Vdvd and Vref voltages and supplies the comparison result COMP to the charging pump 250 for generating the desired voltage Vpgm. This Vpgm can then be provided to the cell array memory 11 via the X-decoder 141. Figure 14B is a schematic diagram of a voltage divider 230 of the Figure μ, in accordance with an embodiment of the present invention. As shown, the voltage divider 230 can be implemented to have a transistor logic (TRANSISTOR LOGIC) based on the step signal STEP-CNTL[5 ·· 0] provided by the signal φ control logic 200. An incremental step voltage is generated, such as voltages of Vpgml to Vpgm5 of FIGS. 6A to 6C and FIGS. 9A to 9C. Figure 14C is a schematic diagram of the implementation of the comparator 240 of Figure 14a, in accordance with an embodiment of the present invention. As shown, the comparator 24, under the control of the signal OSC from the oscillator 21, compares the voltage Vdvd from the voltage divider 230 with the voltage Vref from the reference voltage generator 220, and outputs a comparison signal COMP for charging. Pump 250.

24 !267864 16693pif.d〇c mode: =:=诏 is shown as according to the invention - an embodiment, double stylized (or slower 'work: come = two f:, can be made by standard include · # The raft enters the quasi-poor material. As shown, this can be entered into the standard standard cell data, the address of the standard cell (4), the written and executed standard (or slower) program. Or other batches of 41 can carry people's flags, control flags, signs, and control signs ', Zhi, or: he two: 丄 write this flag, control flag, mark the ', control mark, the shell is in place Address, write this flag, control flag, standard or other control information, and perform faster program work. Μ * = 5 Α In the example, 'this cylinder is divided and used two separate standards (or slower) Program work _ and faster process (scarf this - the advantage of the arrangement is to provide flexibility in the standard and sub-programs that can be executed individually. The 'cutting standard' shown in dm (or slower) program work poor. As shown, this can include loading standard cell data D), writing the address of this standard cell data (WRITE A DDRESS), ^ and write this standard cell data (WRITE DATA). As shown, the next two can be loaded with flags, control flags, flags, control flags, or other controls = (LOAD) write The flag, control flag, standard, control, or WRITE ADDRESS, and the writing of the flag, control flag, standard, (4) mark, or Other control rite DATA) 〇 In the example in Figure 15Β, the standard (or slower) program and the faster program can be executed together with the common command U〇h/20h) (Β〇ΤΗ

25 1267864 16693pif.doc PROGRAM). The advantage of this arrangement is that it can shorten the entire stylized time.

Embodiments of the invention may be semiconductor devices. Embodiments of the invention may be non-electrical memory. Embodiments of the invention may be flash memory. Embodiments of the invention may be NAND or NOR flash memory. Embodiments of the present invention are applicable to a single locating cell (SINGLE LEVE) L, and/or a multi-level cell (MULTILEVEL CELL) (MLC). The embodiments of the present invention can be applied to mass storage applications and/or code memories. The embodiment of the present invention refers to a flag, a control flag, a flag, a control flag, or an acknowledgement flag as an example of a control information form. We can use a different writing method than the standard data and/or faster than the standard data. The writing method is used to write these control information forms. 1 Embodiments of the present invention increase the word line voltage, but those skilled in the art are aware of other techniques. The present embodiment increases the word field voltage. It is preferred that the skilled artisan prefers that four is an arbitrary number and can actually be changed while still being within the scope of the invention. In an embodiment of the invention, the word line voltage includes a program voltage (RPOGRAM). VOLTAGE) and verification voltage (νΕ·γ VOLTAGE), but other voltages are known to those skilled in the art. Although the examples of the present invention have been described with respect to the example voltage panel sample duration (DURATION), the skilled artisan Knowable to change Each of these voltages (including the values mentioned in the prior art) does not depart from the scope and spirit of the present invention. Although the embodiments of the present invention have described the associated determined voltage, 26 1267864 16693pif.doc It is well known to those skilled in the art that the value of each of these voltages can also be changed or fixed. For example, incremental stepping can be implemented (Ispp) with initial voltage VL and N stylization steps (PROGRAMMING STEPs), here, N It is an integer; and other pulses can be implemented to have an initial voltage VH and a Μ stylization step, where μ is an integer less than n. Furthermore, VH can be greater than, less than, or equal to V1. In another embodiment, Incremental stepping pulse stylization (ISpp) can be implemented with initial voltage VL and N stylization steps, where N is an integer, and the HIGH-SPEED PROGRAMMING contains the initial voltage VH and the stylized REDUCED INCREMENT STEP PULSE PROGRAMMING (RISPP), where Vh > Vl, and M is an integer such as i < M < N. Furthermore, vH can In other examples, the high-speed stylized initial voltage VH can be fixed. In other examples, the initial voltage VH of the high-speed stylized operation needs to be regarded as the final of the lower-speed stylized work. The voltage vL is determined. Although the embodiment of the present invention has been described as using the logic state 仏001(:: STATE) "low" ("[(^'' iodine "high" ^ ^ ^ ^ ^ but the skilled artisan will understand these The logic states are all interchangeable without departing from the scope and spirit of the invention. Although the embodiments of the present invention have been described as including NM〇s and PM〇s transistors, those skilled in the art will appreciate that any other circuit implementation can be used without departing from the scope and spirit of the invention. 27 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The scope of protection of the present invention is therefore defined by the scope of the appended claims. [Simple diagram of the figure] Figure 1 shows the word line voltage

A schematic diagram of the relationship between Vw〇RD LINE (for example: 0V), read voltage (READ VOLTAGE) VREAD, and deprogrammed (or erased) cells and the cell voltage distribution Vth of the programmed cell. 2A and 2B are schematic illustrations of prior art incremental stepping pulse programs (ISPPs). FIG. 3 is a schematic diagram showing the problem of over-staging in the prior art. FIG. 4A is a schematic diagram showing an example of successfully completing the confirmation flag, and FIG. 4B is a schematic diagram showing an example of not successfully completing the confirmation flag. Figure 5A is a schematic diagram showing prior art standard cell programming and validation cell programming, as well as prior art standard cell programming time and confirming cell programming time. Figure 5B is a diagram showing an example of prior art standard cell programming and acknowledging cell programming memory locations. 6A, 6B, and 6C illustrate different methods for performing a stylization method on a flag, a control flag, a display 4, a control flag, or other control information and cell data according to an embodiment of the present invention. schematic diagram. 7A and 7B are diagrams for comparison with the prior art according to an embodiment of the present invention. 8A and 8B are diagrams showing the flow of a method according to an embodiment of the present invention. 28 1267864 16693pif.doc. 9A-9D are schematic diagrams showing the use of two different stylization methods in accordance with still another embodiment of the present invention. 10A through 1D are schematic views of a cell array in accordance with an embodiment of the present invention. The figure is shown as a more detailed schematic diagram of the main fields and reserved blocks of each cell array region in accordance with an embodiment of the present invention.

Figure 11B depicts a flow diagram for writing a NAND flash cell array in accordance with an embodiment of the present invention. 12A and 12B are flow diagrams of a more general method of FIGS. 8a and 8B in accordance with other embodiments of the present invention. Figure 13 is a schematic illustration of a semiconductor memory device in accordance with one embodiment of the present invention. Figure 14A is a schematic diagram of a word line voltage generator of the semiconductor memory device of Figure 13 in accordance with an embodiment of the present invention. σ Figure 14 is a schematic diagram of a voltage divider of the word line voltage generator of Figure 14 in accordance with an embodiment of the present invention. V % Figure 14C is a schematic illustration of a comparator of the word voltage generator of Figure 14A, in accordance with an embodiment of the present invention. ~ 'Double Stylization Figure 15A and Figure 15B show two timing diagrams of mode operation in accordance with an embodiment of the present invention. It is to be understood that these are intended to be illustrative of the general nature of the method of the embodiments of the present invention, which are intended to be illustrative of the embodiments. These figures are not of a sizing size and may not reflect the characteristics of the embodiments of the invention, and should not be construed as a range or characteristic of the values of the various embodiments in the range. The invention is particularly limited in that the relative thickness and position of the layers or regions may be reduced or exaggerated. Furthermore, when the layer is directly formed on the substrate or the substrate, or is formed on other layers or patterns covering the reference layer, the layer is considered to be "on the other layer or matrix". Main component symbol description]

S210, S220, S230, S240, S250, S260, S270, S280, S610, S620, S630, S640, S650, S660, S670, S680, 10, 30, 50, 70, 90, 120, 140, 160, 130, 150, 170, 190: Flow chart steps

VwORDLINE : word line voltage VREAD : read voltage 110A : lower speed write area 110B : higher speed write area X-DEC · X-decoder 100 : semiconductor memory device 110 : cell array memory 120 : program control 140: memory driver 141: column decoder 142: page buffer 143: Y-gate 144: Din/Dout buffer 30 1267864 16693pif.doc 145: program termination circuit 146: word line voltage generator 200: signal control logic 210: Oscillator 220: Reference Voltage Generator 230: Voltage Divider 240: Comparator 250: Charging Pump

Vpgm: word line voltage STEP_CNTL[5 ·· 0] ··stepping signal

Vref ··reference signal

Vdvd: Level signal 31

Claims (1)

1267864 16693Pif.d〇c X. Patent application scope: ι A stylized method comprising: performing a low-speed stylization of a cell form in a first region of a memory array; and determining a first region of the memory array a result of one of the cell-shaped low-speed stylizations given; and/or after confirming the result of the lower-speed stylization, performing the cell form of the second region in the _H-high-speed stylization; a ' The initial stylized voltage of the southerly stylized is different from the lower speed stylized. 2. The stylized method of claim i, wherein the assigned cell form is programmable to have only two states. The stylized method of claim 3, wherein the assigned cell form is programmable to more than two states. /, 4) The stylized method described in the scope of the patent application, wherein 6 Hai lower-speed stylized execution of a data writing work. Lu. 5, the stylized method of claim 1, wherein the slower stylization performs a control information writing operation. 6. The stylized method of claim 5, wherein the higher speed stylization performs a confirmation flag write operation. 7. The stylized method of claim 1, wherein the lower speed stylization comprises an incremental stepping pulse program K (ISPP) having an initial voltage of ¥[and an N stylization step, here, N is an integer; and the higher speed stylization includes having an initial voltage ^^ and "stylization steps 32 1267864 16693pif.doc Reduced incremental stepping pulse stylization (REDUCED ISPP), where μ is an integer of <Ν. 8 is the stylized method of claim 7, wherein the higher speed programming is a stylization with a M=1 stylization step. 9. The stylized method described in claim 7 of the patent scope, Bean, VH > VL. (7) The stylized method of claim 7, wherein the initial voltage vH of the slower stylized is fixed. • The method of claim 7, wherein the higher speed stylized initial voltage VH is dependent on a final voltage of the lower speed stylized operation ‘. 12. The stylized method of claim 11, wherein the higher speed stylized initial voltage Vh is equal to or greater than the lower voltage stylized final voltage. 13. The stylized method of claim 301, wherein the slower stylized initial voltage Vh is less than the final voltage of the lower speed program φ. 14. The stylized method of claim 13, wherein the lower speed stylization has a longer time than the higher speed stylization. / ^ = · As in the stylized method described in claim 7, wherein the final stylization of the higher speed stylized is higher than the lower speed stylized. 16. The stylized method of claim 4, wherein 33 1267864 16693pif.doc is written in a main memory range. 17. As in the stylized method described in claim 4, the data write operation is performed in a reserved memory range. ", 18. If the stylized method described in claim 7 of the patent scope is applied, the control information is written in a main memory range, 19. as in the scope of claim 7 The stylized method described above is used to control the information writer's work in the pre-memory range. , in the '2 0. as described in the scope of patent application 帛 7 stylized method Ding' | the lower speed stylization and the higher speed stylization are by - life heat, in the middle, 21. The stylized party described in item 2 = 仃. In the middle, the lower-speed stylized and vocational high-speed materialization can be _ ' '22. The program described in item 7 of the patent scope ^ The lower-speed materialization _ more pure material cutting in the end The scope described in item 22 of the scope. 24.- Stylized methods, including: UT riding to the second method of execution memory - the first - in the region - the cell form given in the region of the first program stylized =: when the time is 'lidi The second stylization; the method performs the assigned cell form. The initial stylized voltage of the higher speed stylized is different from the lower 34 1267864 16693 pif.doc stylized. 25. A semiconductor memory device comprising: a non-electrical memory cell array comprising - a third region and a &field; and a device for performing the non-electric memory cell array - The middle ϋ secret cell type - lower speed stylization, confirm the result of the lower axis of the first region, and # the lower speed 3, execute the non-electric memory cell array The cell type given in the region is more high-speed stylized; the low, #^^录^lightized # initial stylized voltage is different from the lower stylized initial stylized voltage. 26. In the semiconductor memory package described in the 25th section of the patent scope of the cap, the 'hybrid low-speed stylized execution __ data writing work. Fan, 2 Gan 7 Shi as claimed in the patent scope *25 semiconductor memory Installed in the middle of the 'her her-speed stylized implementation—control flag writing work. The semiconductor memory package described in the 25th article of the patent application scope includes a word line voltage generator, wherein the word line = firm Generating (4) to receive - lower speed (four) to enable and call - higher speed stylized enable signal ' and provide 1 voltage to at least one memory block of the non-electric memory cell array. 29 · If the scope of patent claims 帛The semiconductor memory device is described, wherein the word line voltage generator selectively generates an incremental step-stration (ispp) having an initial voltage VL and a stylization step, where N is - Integer, or selectively generated with an initial voltage % and 35 1267864 16693pif.doc Μ Μ Μ Μ Μ Μ ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP ISP , = semiconductor as described in section 29 of the scope Memory installed such as Shen: Qing she around the 29th item mentioned in the 29th, the whistle is a program with a M=1 stylization step, L2.:, Shen! Guli range * 29 items The semiconductor memory is worn," the initial voltage v is more solid than the two-speed stylized, and 33 is fixed as claimed in the patent application. Low-speed stylized work depends on the final voltage. Despise the comparison, as described in item 29 of the scope of application, where VH>VL. Noon V body 圮 体 · 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 H sees the lower speed 36. As set forth in claim 35, wherein the higher speed stylized initial voltage V phase w: is the last voltage programmed at the lower speed. δ is at or greater 37. As described in claim 35, the higher speed stylized _ initial voltage ν = the final voltage of the body speed stylized. H j, at the lower 38. If the semiconductor memory device 36 1267864 16693pif.doc described in claim 29 is applied, the word line voltage generator further includes: a voltage divider for generating A voltage increment is applied to each of the N and Μ stylization steps in the incremental step pulse program (ISPP); a reference voltage generator that produces a reference for comparison with the voltage divider a comparator that compares the voltage increment signal generated by the voltage divider with a reference voltage for generating a voltage increment and controlling the oscillation signal; and • an oscillator that periodically provides an oscillation The signal is applied to the comparator; and a charging pump that provides a high voltage program voltage for the stylized operation. 39. A semiconductor memory device, comprising: a non-electric memory cell array comprising a first region and a first region, the first region comprising a plurality of memory cell strings, wherein one The string includes a plurality of memory cells, and the total number of cells of the string to be programmed in the string is less than all of the memory cells in the string, and the threshold voltage of a programmed cell is independent of a Vread voltage; and A second area includes a plurality of memory cell strings, wherein all of the memory cells in the substring are programmable. 40. The semiconductor memory device f of claim 39, wherein the programmed cell is read when the threshold voltage of the programmed cell is higher than Vread. 41. The semiconductor memory device according to claim 39, wherein the string is read by the same reading method as the memory string in the second region. 42. The semiconductor memory device of claim 39, wherein the memory cells that are not intended to be programmed are in an erased state.