US20110240957A1 - Group lll nitride semiconductor light-emitting device - Google Patents

Group lll nitride semiconductor light-emitting device Download PDF

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US20110240957A1
US20110240957A1 US13/064,536 US201113064536A US2011240957A1 US 20110240957 A1 US20110240957 A1 US 20110240957A1 US 201113064536 A US201113064536 A US 201113064536A US 2011240957 A1 US2011240957 A1 US 2011240957A1
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light
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Koji Okuno
Atsushi Miyazaki
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Toyoda Gosei Co Ltd
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Toyoda Gosei Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a Group III nitride semiconductor light-emitting device which suppresses an increase in driving voltage and which exhibits improved emission performance.
  • Japanese Patent Application Laid-Open (kokai) Nos. H11-191639 and 2007-180499 discloses a Group III nitride semiconductor light-emitting device having a structure in which a light-emitting layer is stacked on n-type layers; i.e., a third layer bonded to the light-emitting layer, a second layer bonded to the third layer, and a first layer bonded to the second layer.
  • the second layer has a superlattice structure formed of two layers (AlGaN layer and GaN layer) or a superlattice structure formed of two layers (AlGaN layer and InGaN layer), and the third layer has an impurity concentration lower than that of the second layer. This configuration of the device reduces driving voltage.
  • Japanese Patent Application Laid-Open (kokai) No. 2007-180499 discloses a Group III nitride semiconductor light-emitting device including a substrate, an n-type semiconductor layer on which an n-electrode is formed, and an intermediate layer provided between the substrate and the n-type semiconductor layer and having a periodic structure formed of AlGaN, GaN, and InGaN.
  • the intermediate layer improves the crystallinity of the n-type semiconductor layer which serves as a current path and on which the n-electrode is formed, thereby improving the reliability of the device.
  • the light-emitting layer exhibits improved crystallinity, but confinement of holes in the light-emitting layer fails to be attained, and resistance to electrons is not reduced.
  • these conventional devices fail to achieve both reduction of driving voltage and improvement of emission performance.
  • An object of the present invention is to improve emission performance without increasing driving voltage, by effectively confining holes in a light-emitting layer without causing an increase in resistance to electrons.
  • a Group III nitride semiconductor light-emitting device comprising at least an n-type-layer-side cladding layer, a light-emitting layer, and a p-type-layer-side cladding layer, each of the layers being formed of a Group III nitride semiconductor, wherein the n-type-layer-side cladding layer is a superlattice layer having a periodic structure including an In y Ga 1-y N (0 ⁇ y ⁇ 1) layer, an Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer, and a GaN layer.
  • the initial layer or final layer of the superlattice layer may be any one of the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer, the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer, and the GaN layer.
  • the initial layer i.e., the layer most distal from the light-emitting layer
  • the final layer i.e., the layer most proximal to the light-emitting layer
  • the GaN layer is not necessarily the GaN layer.
  • the superlattice layer may have a periodic structure formed of layer units each including the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer, the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer, and the GaN layer, which are stacked in this order toward the light-emitting layer, wherein the initial layer of the periodic structure may be any of these semiconductor layers.
  • the superlattice layer may have a periodic structure formed of layer units each including the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer, the GaN layer, and the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer, which are stacked in this order toward the light-emitting layer, wherein the initial layer of the periodic structure may be any of these semiconductor layers.
  • the initial layer of one layer unit of the periodic structure may be any one of the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer, the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer, and the GaN layer, and is not necessarily the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer.
  • an n-type contact layer for forming an n-electrode is provided below the n-type cladding layer, and a p-type contact layer for forming a p-electrode is provided above the p-type-layer-side cladding layer.
  • the semiconductor light-emitting device of the present invention may include a layer other than the aforementioned layers.
  • the light-emitting layer may have a single quantum well structure or a multiple quantum well structure.
  • the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer has such a thickness that electrons tunnel through the Al x Ga 1-x N layer and holes are confined in the light-emitting layer.
  • the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer acts as a barrier against holes contained in the light-emitting layer, and exhibits the effect of confining holes in the light-emitting layer.
  • the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer acts as a barrier against electrons. Since the de Broglie wavelength of electrons is greater than that of holes, electron tunneling length is larger than hole tunneling length. Therefore, the thickness of the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer can be adjusted to such a level that electrons can tunnel therethrough and holes cannot tunnel therethrough.
  • the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer can act as a barrier layer for holes injected from the p-contact layer into the light-emitting layer, whereby holes can be effectively confined in the light-emitting layer.
  • emission performance can be improved without increasing driving voltage.
  • the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer has a thickness of 0.3 nm to 2.5 nm. When the thickness falls within this range, electrons can tunnel through the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer, and passage of holes can be blocked by the layer.
  • the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer has an Al compositional proportion x of 0.05 or more and less than 1.
  • the barrier hight becomes higher, and thus the thickness of the layer must be reduced.
  • the thickness of the layer is appropriately regulated while the Al compositional proportion is adjusted so as to fall within the above range, electrons can tunnel through the layer, and passage of holes can be blocked by the layer.
  • the p-type-layer-side cladding layer is formed of a superlattice layer including an Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer, and the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer of the n-type-layer-side cladding layer has a compositional proportion x of 1 ⁇ 2 or more of the compositional proportion z of the Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer of the p-type-layer-side cladding layer.
  • At least one of the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer, the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer, and the GaN layer, which form the n-type-layer-side cladding layer preferably contains Si.
  • all the layers forming the n-type-layer-side cladding layer may contain Si.
  • Both the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer and the GaN layer may contain Si, and the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer may contain no impurity.
  • both the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer and the GaN layer may contain Si, and the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer may contain no impurity.
  • both the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer and the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer may contain Si, and the GaN layer may contain no impurity.
  • the light-emitting layer is formed directly on the n-type-layer-side cladding layer.
  • the p-type-layer-side cladding layer is a superlattice layer having a periodic structure including an In w Ga 1-x N layer and an Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer.
  • the n-type-layer-side cladding layer has a four-layer periodic structure including a second GaN layer interposed between the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer and the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer.
  • the difference in lattice constant between adjacent layers can be reduced, and the crystallinity of the Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer or the In y Ga 1-y N (0 ⁇ y ⁇ 1) layer can be improved.
  • formation of an Al x Ga 1-x-y In y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1) layer is prevented between adjacent layers.
  • the light-emitting device exhibits improved characteristics.
  • the Group III nitride semiconductor is one containing Ga as an essential element, such as GaN, AlGaN, InGaN, or AlGaInN.
  • the light-emitting layer may have a single quantum well structure or a multiple quantum well structure.
  • the multiple quantum well structure which may be employed include a multiple quantum well structure of AlGaN/GaN having any compositional proportions, a multiple quantum well structure of InGaN/GaN having any compositional proportions, a multiple quantum well structure of AlGaN/InGaN having any compositional proportions, a multiple quantum well structure of AlGaN/GaN/InGaN having any compositional proportions, and a multiple quantum well structure of GaN/AlGaN having high Al compositional proportion/AlGaN having low Al compositional proportion/InGaN.
  • the semiconductor light-emitting device of the present invention may further include a layer other than those described above, such as an n-type contact layer or a p-type contact layer.
  • a layer for improving electrostatic breakdown voltage (hereinafter may be referred to as an “ESD layer”) may be provided between the substrate and the re-contact layer.
  • the device may have any other layer configuration.
  • FIG. 1 shows the configuration of a light-emitting device 1 according to Embodiment 1;
  • FIGS. 2A to 2C are sketches showing processes for producing the light-emitting device 1 ;
  • FIG. 3 shows the band structure of the light-emitting device according to Embodiment 1;
  • FIG. 4 shows the configuration of a light-emitting device 1 according to Embodiment 2.
  • FIG. 5 shows the band structure of the light-emitting device according to Embodiment 2.
  • FIG. 1 shows the configuration of a light-emitting device 1 according to Embodiment 1 .
  • the light-emitting device 1 has a structure including a sapphire substrate 100 ; an AlN buffer layer 120 ; an n-type contact layer 101 , an ESD layer 102 , an n-type-layer-side cladding layer (referred to as “n-type cladding layer” throughout the Embodiments) 103 , a light-emitting layer 104 , an undoped cladding layer 105 , a p-type-layer-side cladding layer (referred to as “p-type cladding layer” throughout the Embodiments) 106 , and a p-type contact layer 107 , the layers 101 to 107 being formed of a Group III nitride semiconductor and deposited on the substrate 100 via the buffer layer 120 ; a p-electrode 108 formed on the p-type contact layer 107 ; and an n-electrode 130
  • the surface of the sapphire substrate 100 is embossed for improving light extraction performance.
  • the sapphire substrate may be replaced with another growth substrate made of, for example, SiC, ZnO, Si, or GaN.
  • the n-type contact layer 101 is formed of n-GaN having an Si concentration of 1 ⁇ 10 18 /cm 3 or more.
  • the n-type contact layer 101 may be formed of a plurality of layers having different carrier concentrations for attaining good contact between the layer 101 and the n-electrode 130 .
  • the ESD layer 102 has a four-layer structure including a first ESD layer 110 , a second ESD layer 111 , a third ESD layer 112 , and a fourth ESD layer 113 , the layers 110 to 113 being sequentially deposited on the n-type contact layer 101 .
  • the first ESD layer 110 is formed of n-GaN having an Si concentration of 1 ⁇ 10 16 to 5 ⁇ 10 17 /cm 3 .
  • the first ESD layer 110 has a thickness of 200 to 1 , 000 nm.
  • the surface 110 a of the first ESD layer 110 has few pits attributed to threading dislocations (pit density: 1 ⁇ 10 8 /cm 2 or less).
  • the second ESD layer 111 is formed of GaN doped with Si, and has a characteristic value, as defined by the product of Si concentration (/cm 3 ) and thickness (nm), of 0.9 ⁇ 10 20 to 3.6 ⁇ 10 20 (nm/cm 3 ). For example, when the second ESD layer 111 has a thickness of 30 nm, the layer has an Si concentration of 3.0 ⁇ 10 18 to 1.2 ⁇ 10 19 /cm 3 .
  • the third ESD layer 112 is formed of undoped GaN.
  • the third ESD layer 112 has a thickness of 50 to 200 nm.
  • the surface 112 a of the third ESD layer 112 also has pits (pit density: 2 ⁇ 10 8 /cm 2 or more).
  • the third ESD layer 112 is formed of undoped GaN, the layer has a carrier concentration (attributed to residual carriers) of 1 ⁇ 10 16 to 1 ⁇ 10 17 /cm 3 .
  • the third ESD layer 112 may be doped with Si such that the layer has a carrier concentration of 5 ⁇ 10 17 /cm 3 or less.
  • the fourth ESD layer 113 is formed of GaN doped with Si, and has a characteristic value, as defined by the product of Si concentration (/cm 3 ) and thickness (nm), of 0.9 ⁇ 10 20 to 3.6 ⁇ 10 20 (nm/cm 3 ). For example, when the fourth ESD layer 113 has a thickness of 30 nm, the layer has an Si concentration of 3.0 ⁇ 10 18 to 1.2 ⁇ 10 19 /cm 3 .
  • the n-type cladding layer 103 has a superlattice structure including 15 layer units, each including sequentially stacked three layers: an undoped In 0.077 Ga 0.923 N layer 131 (thickness: 4 nm), an undoped Al 0.2 Ga 0.8 N layer 132 (thickness: 0.8 nm), and an Si-doped n-GaN layer 133 (thickness: 1.6 nm).
  • the initial layer of the n-type cladding layer 103 which is in contact with the fourth ESD layer 113 , is the In 0.077 Ga 0.923 N layer 131
  • the final layer of the n-type cladding layer 103 which is in contact with the light-emitting layer 104 , is the n-GaN layer 133 .
  • the overall thickness of the n-type cladding layer 103 is 96 nm.
  • the In 0.077 Ga 0.923 N layer 131 may have a thickness of 1.5 nm to 5.0 nm.
  • the Al 0.2 Ga 0.8 N layer 132 may have a thickness of 0.3 nm to 2.5 nm.
  • the n-GaN layer 133 may have a thickness of 0.3 nm to 2.5 nm.
  • the light-emitting layer (may also be referred to as “active layer”) 104 has an MQW structure including eight layer units, each including sequentially stacked four layers: an Al 0.05 Ga 0.95 N layer 141 (thickness: 2.4 nm), an In 0.2 Ga 0.8 N layer 142 (thickness: 3.2 nm), a GaN layer 143 (thickness: 0.6 nm), and an Al 0.2 Ga 0.8 N layer 144 (thickness: 0.6 nm).
  • the initial layer of the light-emitting layer 104 which is in contact with the n-type cladding layer 103 , is the Al 0.05 Ga 0.95 N layer 141
  • the final layer of the light-emitting layer 104 which is in contact with the undoped cladding layer 105 , is the Al 0.2 Ga 0.8 N layer 144 .
  • the overall thickness of the light-emitting layer 104 is 54.4 nm. All the layers of the light-emitting layer 104 are formed of undoped layers.
  • the undoped cladding layer 105 interposed between the light-emitting layer 104 and the p-type cladding layer 106 includes an undoped GaN layer 151 (thickness: 2.5 nm) and an undoped Al 0.15 Ga 0.85 N layer 152 (thickness: 3 nm).
  • the undoped cladding layer 105 is provided for the purpose of preventing diffusion of Mg contained in the layers formed above the layer 105 to the light-emitting layer 104 .
  • the p-type cladding layer 106 has a structure including seven layer units, each including a p-In 0.05 Ga 0.95 N layer 161 (thickness: 1.7 nm) and a p-Al 0.3 Ga 0.7 N layer 162 (thickness: 3.0 nm) which are sequentially stacked.
  • the initial layer of the p-type cladding layer 106 which is in contact with the undoped cladding layer 105 , is the p-In 0.05 Ga 0.95 N layer 161
  • the final layer of the p-type cladding layer 106 which is in contact with the p-type contact layer 107 , is the p-Al 0.3 Ga 0.7 N layer 162 .
  • the overall thickness of the p-type cladding layer 106 is 32.9 nm.
  • Mg is employed as a p-type impurity.
  • the p-type contact layer 107 is formed of p-GaN doped with Mg.
  • the p-type contact layer 107 may be formed of a plurality of layers having different carrier concentrations for attaining good contact between the layer 107 and the p-electrode.
  • the ESD layer 102 is configured such that, firstly, the first ESD layer 110 having few pits is formed; the second ESD layer 111 is formed on the first ESD layer 110 ; the third ESD layer 112 having pits (pit density: 2 ⁇ 10 8 /cm 2 or more) is formed on the second ESD layer 111 ; and the fourth ESD layer 113 is formed on the third ESD layer 112 having pits. With this configuration, high electrostatic breakdown voltage is attained.
  • the pit size depends on the thickness of the third ESD layer 112 (i.e., the thickness of the third ESD layer 112 and the pit size cannot be independently controlled)
  • the pit size increases, and the emission area decreases, resulting in reduction of emission performance, an increase in current leakage, and poor reliability. That is, electrostatic breakdown voltage and current leakage, reliability, or emission performance are in a trade-off relationship.
  • the ESD layer 102 is configured such that the second ESD layer 111 and the third ESD layer 112 are provided on the first ESD layer 110 formed of a good crystal having a pit density of 1 ⁇ 10 8 /cm 2 or less, and so that the pit size and the total thickness of the first ESD layer 110 and the third ESD layer 112 can be independently controlled by regulating the thickness of the first ESD layer 110 or the thickness of the third ESD layer 112 .
  • the thickness of the third ESD layer 112 is adjusted to 50 to 200 nm so that electrostatic breakdown voltage and emission performance are not reduced, and so that the pit size is regulated so as not to cause an increase in current leakage.
  • the thickness of the first ESD layer 110 is adjusted to 200 to 1,000 nm for compensating reduction of the thickness of the third ESD layer 112 , so as to attain high electrostatic breakdown voltage.
  • the first ESD layer 110 is doped with Si (Si concentration: 1 ⁇ 10 16 to 5 ⁇ 10 17 /cm 3 ) so as to match the conductivity of the first ESD layer 110 to that of the third ESD layer 112 . Thus, an increase in forward voltage is prevented.
  • the ESD layer 102 is configured as follows.
  • the first ESD layer 110 preferably has a thickness of 300 to 700 nm, an Si concentration of 5 ⁇ 10 16 to 5 ⁇ 10 17 /cm 3 , and a pit density of 1 ⁇ 10 7 /cm 2 or less.
  • the second ESD layer 112 preferably has a characteristic value of 1.5 ⁇ 10 20 to 3.6 ⁇ 10 20 nm/cm 3 and a thickness of 25 to 50 nm.
  • the third ESD layer 112 preferably has a thickness of 50 to 200 nm and a pit density of 2 ⁇ 10 8 to 1 ⁇ 10 10 /cm 2 .
  • the fourth ESD layer 113 preferably has a characteristic value of 1.5 ⁇ 10 20 to 3.6 ⁇ 10 20 nm/cm 3 and a thickness of 25 to 50 nm.
  • Crystal growth is carried out through metal-organic chemical vapor deposition (MOCVD).
  • the gases employed are as follows: hydrogen or nitrogen (H 2 or N 2 ) as a carrier gas; ammonia gas (NH 3 ) as a nitrogen source; trimethylgallium (Ga(CH 3 ) 3 , hereinafter may be referred to as “TMG”) as a Ga source; trimethylindium (In(CH 3 ) 3 , hereinafter may be referred to as “TMI”) as an In source; trimethylaluminum (Al(CH 3 ) 3 , hereinafter may be referred to as “TMA”) as an Al source; silane (SiH 4 ) as an n-type dopant gas; and cyclopentadienylmagnesium (Mg(C 5 H 5 ) 2 , hereinafter may be referred to as “Cp 2 Mg”) as a p-type dopant gas.
  • H 2 or N 2 carrier gas
  • NH 3 ammonia
  • the sapphire substrate 100 was heated in a hydrogen atmosphere for cleaning, to thereby remove deposits from the surface of the sapphire substrate 100 . Thereafter, the substrate temperature was maintained at 400° C., and the AlN buffer layer 120 was formed on the sapphire substrate 100 through MOCVD. Then, the substrate temperature was elevated to 1,100° C. under a stream of hydrogen gas (carrier gas) and ammonia gas. Immediately after the substrate temperature had reached 1,100° C., the n-type contact layer 101 formed of GaN and having an Si concentration of 4.5 ⁇ 10 18 /cm 3 was deposited on the buffer layer 120 by using TMG and ammonia gas as raw material gases, and silane gas as an impurity gas ( FIG. 2A ).
  • the ESD layer 102 was formed through the following processes. Firstly, on the n-type contact layer 101 was deposited, through MOCVD, the first ESD layer 110 formed of n-GaN and having a thickness of 200 to 1,000 nm and an Si concentration of 1 ⁇ 10 16 to 5 ⁇ 10 17 /cm 3 . The growth temperature was adjusted to 900° C. or higher so as to grow a high-quality crystal having a pit density of 1 ⁇ 10 8 /cm 2 or less. When the growth temperature is adjusted to 1,000° C. or higher, a crystal of higher quality is grown, which is preferred.
  • the second ESD layer 111 formed of n-GaN and having a characteristic value, as defined by the product of Si concentration (/cm 3 ) and thickness (nm), of 0.9 ⁇ 10 20 to 3.6 ⁇ 10 20 (nm/cm 3 ).
  • the growth temperature was adjusted to 800 to 950° C.
  • the third ESD layer 112 formed of undoped GaN and having a thickness of 50 to 200 nm was deposited on the second ESD layer 111 through MOCVD.
  • the growth temperature was adjusted to 800 to 950° C.
  • the growth temperature is adjusted to 800 to 900° C., the pit density is further increased, which is preferred.
  • the fourth ESD layer 113 formed of n-GaN and having a characteristic value, as defined by the product of Si concentration (/cm 3 ) and thickness (nm), of 0.9 ⁇ 10 20 to 3.6 ⁇ 10 20 (nm/cm 3 ).
  • the growth temperature was adjusted to 800 to 950° C.
  • the ESD layer 102 was formed on the n-type contact layer 101 ( FIG. 2B ).
  • the n-type cladding layer 103 was formed on the ESD layer 102 through MOCVD.
  • the n-type cladding layer 103 was formed by periodically stacking 15 layer units each including the undoped In 0.077 Ga 0.923 N layer 131 (thickness: 4 nm), the undoped Al 0.2 Ga 0.8 N layer 132 (thickness: 0.8 nm), and the Si-doped n-GaN layer 133 (thickness: 1.6 nm).
  • the In 0.077 Ga 0.923 N layer 131 was formed under supply of silane gas, TMG, TMI, and ammonia while the substrate temperature was maintained at 830° C.
  • the Al 0.2 Ga 0.8 N layer 132 was formed under supply of TMA, TMG, and ammonia while the substrate temperature was maintained at 830° C.
  • the n-GaN layer 133 was formed under supply of TMG and ammonia while the substrate temperature was maintained at 830° C.
  • the light-emitting layer 104 was formed on the n-type cladding layer 103 .
  • the light-emitting layer 104 was formed by periodically stacking eight layer units each including the following four layers: the Al 0.05 Ga 0.95 N layer 141 , the In 0.2 Ga 0.8 N layer 142 , the GaN layer 143 , and the Al 0.2 Ga 0.8 N layer 144 .
  • Each of the layers 141 to 144 was grown under supply of the corresponding raw material gases to form the light-emitting layer 104 .
  • the growth temperature, i.e., the substrate temperature, of the Al 0.05 Ga 0.95 N layer 141 was any temperature from 800° C. to 950° C.
  • the growth temperature of In 0.2 Ga 0.8 N layer 142 , the GaN layer 143 and the Al 0.2 Ga 0.8 N layer 144 was 770° C.
  • the growth temperature of the three layers 141 , 142 and 143 may be commonly maintained at 770° C.
  • the undoped GaN layer 151 (thickness: 2.5 nm) was grown on the light-emitting layer 104 under supply of TMG and ammonia while the substrate temperature was maintained at 855° C. Then, while the substrate temperature was maintained at 855° C., the undoped Al 0.15 Ga 0.85 N layer 152 (thickness: 3 nm) was grown under supply of TMA, TMG, and ammonia. Thus, the undoped cladding layer 105 was formed.
  • the p-type cladding layer 106 was formed on the undoped cladding layer 105 .
  • the p-In 0.05 Ga 0.95 N layer 161 (thickness: 1.7 nm) was formed under supply of CP 2 Mg, TMI, TMG, and ammonia while the substrate temperature was maintained at 855° C.
  • the p-Al 0.3 Ga 0.7 N layer 162 (thickness: 3.0 nm) was formed under supply of CP 2 Mg, TMA, TMG, and ammonia while the substrate temperature was maintained at 855° C. This layer formation process was repeated seven times.
  • the p-type contact layer 107 (thickness: 50 nm) formed of p-type GaN doped with Mg (1 ⁇ 10 20 /cm 3 ) was deposited by use of TMG, ammonia, and CP 2 Mg. Thus, the device structure shown in FIG. 2C was formed.
  • the p-type contact layer 107 may have an Mg concentration of 1 ⁇ 10 19 to 1 ⁇ 10 21 /cm 3 .
  • the p-type contact layer 107 may have a thickness of 10 nm to 100 nm.
  • the light-emitting device 1 shown in FIG. 1 was produced.
  • FIG. 3 shows the band structure of the light-emitting device 1 .
  • the undoped Al 0.2 Ga 0.8 N layer 132 of the n-type cladding layer 103 provides the highest potential barrier.
  • the Al 0.2 Ga 0.8 N layer 132 has a thickness as small as 0.8 nm, electrons from the n-type contact layer 101 tunnel through the layer 132 , and are injected into the light-emitting layer 104 .
  • the n-type cladding layer 103 has a periodic structure including the undoped In 0.077 Ga 0.923 layer 131 , the undoped Al 0.2 Ga 0.8 N layer 132 , and the Si-doped n-GaN layer 133 , which are stacked in this order on the side of the n-type contact layer 101 .
  • the n-type cladding layer 103 may have a periodic structure in which the In 0.077 Ga 0.923 N layer, the GaN layer, and the Al 0.2 Ga 0.8 N layer are stacked in this order; the Al 0.2 Ga 0.8 N layer, the GaN layer, and the In 0.077 Ga 0.923 N layer are stacked in this order; or the Al 0.2 Ga 0.8 N layer, the In 0.077 Ga 0.923 N layer, and the GaN layer are stacked in this order.
  • the In 0.077 Ga 0.923 N layer 131 or the Al 0.2 Ga 0.8 N layer 132 may be doped with Si, so as to serve as an n-type layer.
  • the GaN layer 133 may be an undoped layer.
  • the n-type cladding layer 103 is formed of 15 layer units, but the number of layer units is not limited thereto.
  • the number of layer units may be 3 to 30.
  • the Al 0.2 Ga 0.8 N layer 132 may have a thickness of 0.3 nm to 2.5 nm.
  • the GaN layer 133 may have a thickness of 0.3 nm to 2.5 nm.
  • the In 0.077 Ga 0.923 N layer 131 may have a thickness of 1.5 nm to 5.0 nm.
  • the Al x Ga 1-x N layer 132 may have a compositional proportion x of 0.05 to 1.
  • the compositional proportion x is preferably 0.1 to 0.8, more preferably 0.2 to 0.6.
  • the Al x Ga 1-x N layer 132 is formed of AlN, even when the layer has a thickness as small as 0.3 nm, electrons can tunnel through the layer, and passage of holes can be blocked by the layer. Meanwhile, in the case where the Al x Ga 1-x N layer 132 is formed of Al 0.05 Ga 0.95 N, the layer 132 must have a thickness as large as 2.5 nm. Thus, the Al x Ga 1-x N layer 132 may have a thickness of 0.3 nm to 2.5 nm.
  • the Al compositional proportion x of the Al x Ga 1-x N layer 132 of the n-type cladding layer 103 is preferably adjusted to 0.15 or more.
  • the Al compositional proportion x of the Al x Ga 1-x N layer 132 of the n-type cladding layer 103 is preferably adjusted to z/2 or more (wherein z is the Al compositional proportion of the Al z Ga 1-z N layer 162 , which is one of the layers forming the periodic structure of the p-type cladding layer 106 ).
  • the light-emitting device according to the present embodiment has the same configuration as the light-emitting device according to Embodiment 1, except that the n-type cladding layer 103 includes an undoped GaN layer 134 (thickness: 1 nm) interposed between the undoped In 0.077 Ga 0.923 N layer 131 and the undoped Al 0.2 Ga 0.8 N layer 132 .
  • the n-type cladding layer 103 includes an undoped GaN layer 134 (thickness: 1 nm) interposed between the undoped In 0.077 Ga 0.923 N layer 131 and the undoped Al 0.2 Ga 0.8 N layer 132 .
  • the undoped GaN layer 134 is formed on the In 0.077 Ga 0.923 N layer 131 , and the Al 0.2 Ga 0.8 N layer 132 is formed on the GaN layer 134 , whereby crystallinity can be improved, and an appropriate band structure can be attained.
  • the GaN layer 134 is continuous with the In 0.077 Ga 0.923 N layer 131 in terms of composition and band structure, or even when Al is incorporated into the GaN layer 134 at an final stage of growth, the GaN layer 134 is continuous with the Al 0.2 Ga 0.8 N layer 132 in terms of composition and band structure.
  • crystallinity can be improved, and formation of an Al x Ga 1-x-y In y N layer can be prevented, whereby characteristics of the device can be improved.
  • the undoped GaN layer 134 may have a thickness of 0.3 nm to 2.5 nm.
  • the GaN layer 134 may be doped with Si. Even when the order in Embodiment 1 of stacking of the undoped In 0.077 Ga 0.923 N layer 131 , the undoped Al 0.2 Ga 0.8 N layer 132 , and the Si-doped n-GaN layer 133 is changed to any order, the GaN layer may be provided between the InGaN layer and the AlGaN layer.
  • a p-GaN layer 163 may be provided between the p-In 0.05 Ga 0.95 N layer 161 and the p-Al 0.3 Ga 0.7 N layer 162 of the p-type cladding layer 106 of the device according to Embodiment 1.
  • the p-GaN layer 163 may have a thickness of 0.3 nm to 2.5 nm.
  • the GaN layer 163 may be an undoped layer.
  • the Mg-doped GaN layer 163 may be provided at an interface changing from the p-Al 0.3 Ga 0.7 N layer 162 to the p-In 0.05 Ga 0.95 N layer 161 .
  • the Mg-doped GaN layers 163 are formed at the both sides of the p-Al 0.3 Ga 0.7 N layer 162 .
  • the GaN layers may be undoped.
  • the n-type cladding layer 103 must have a good crystallinity because the light-emitting layer 104 is deposited on the n-type cladding layer 103 .
  • the p-type cladding layer 106 is not required a good crystallinity compared with the n-type cladding layer 103 because the light-emitting layer 104 required a good crystallinity is not deposited on the p-type cladding layer 106 . Accordingly it is more important and higher effective that GaN layer formed between InGaN layer and AlGaN layer is formed in the n-type cladding layer than formed in the p-type cladding layer.
  • the Group III nitride semiconductor light-emitting device of the present invention exhibits improved emission performance without increasing driving voltage.

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