US20110027597A1 - Target, method for producing the same, memory, and method for producing the same - Google Patents

Target, method for producing the same, memory, and method for producing the same Download PDF

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Publication number
US20110027597A1
US20110027597A1 US12/838,524 US83852410A US2011027597A1 US 20110027597 A1 US20110027597 A1 US 20110027597A1 US 83852410 A US83852410 A US 83852410A US 2011027597 A1 US2011027597 A1 US 2011027597A1
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Prior art keywords
target
group
memory
alloy ingot
resistance
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Kazuhiro Ohba
Yuichi Kamori
Hitoshi Kimura
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Sony Corp
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Sony Corp
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Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAMORI, YUICHI, KIMURA, HITOSHI, OHBA, KAZUHIRO
Publication of US20110027597A1 publication Critical patent/US20110027597A1/en
Priority to US14/174,917 priority Critical patent/US9419214B2/en
Priority to US15/193,907 priority patent/US10069066B2/en
Abandoned legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F9/00—Making metallic powder or suspensions thereof
    • B22F9/02—Making metallic powder or suspensions thereof using physical processes
    • B22F9/04—Making metallic powder or suspensions thereof using physical processes starting from solid material, e.g. by crushing, grinding or milling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C1/00—Making non-ferrous alloys
    • C22C1/04—Making non-ferrous alloys by powder metallurgy
    • C22C1/05—Mixtures of metal powder with non-metallic powder
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • C23C14/3414—Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31678—Of metal

Definitions

  • the present invention relates to a target containing a refractory metal element and a chalcogen element and to a method for producing the same.
  • the invention also relates to a memory including a memory device having an ionization layer formed using a target and to a method for producing the same.
  • a high-speed, high-density DRAM has been widely used as a random access memory in an information-processing apparatus, such as a computer.
  • DRAMs are volatile memories that lose their contents when the power is turned off, and the written information (data) has to be frequently refreshed, i.e., the data needs to be frequently read, reamplified, and rewritten.
  • a flash memory As non-volatile memories that do not lose their contents when the power is turned off, a flash memory, an FeRAM (ferroelectric random-access memory), an MRAM (magnetic memory device), and the like have been proposed, for example.
  • FeRAM ferroelectric random-access memory
  • MRAM magnetic memory device
  • These memories are capable of maintaining the written information for a long period of time without power supply.
  • Flash memories have high integration density, but are disadvantageous in terms of operation speed.
  • MRAMs have problems in terms of power consumption.
  • This memory device has a structure in which an ion conductor containing a specific metal is sandwiched between two electrodes. When a voltage is applied between the two electrodes, the metal in each electrode diffuses as ions into the ion conductor, thereby changing the resistance, capacitance, or like electrical characteristics of the ion conductor.
  • a memory device can be configured to utilize such characteristics.
  • the ion conductor includes a solid solution of chalcogen elements (S, Se, Te) and a metal. More specifically, the ion conductor includes a material having Ag, Cu, and Zn dissolved in AsS, GeS, and GeSe (see, e.g., JP-T-2002-536840 (the term “JP-T” as used herein means a published Japanese translation of a PCT patent application)).
  • an ionization layer contains, in addition to the chalcogen elements, Zr, Al, and like elements (see, e.g., JP-A-2009-43758).
  • the ionization layer of a memory device can be formed using a plurality of targets by co-sputtering or by periodically stacking layers of the constituent elements with a thickness of about 1 nm.
  • the ionization layers are formed using one target.
  • the ionization layer of a memory device may have the following configuration: element M1-element M2-chalcogen element.
  • elements are classified according to their melting points.
  • Elements M1 are refractory metals including Ti, Zr, Hf, V, Nb, Ta, and the like.
  • Elements M2 include Cu, Al, Si, Ge, Mg, Ga, and the like, for example, and chalcogen elements include S, Se, and Te.
  • an element M1 (refractory metal element) often has a melting point higher than or close to the boiling point of a chalcogen element. Accordingly, it is difficult to simultaneously dissolve the constituent elements, and it thus is difficult to form a target by a dissolution method.
  • a target that contains a refractory metal element and can be produced with less risk of ignition and a method for producing the same. It is also desirable to provide a memory that includes a memory device formed using the target and a method for producing the same.
  • a target containing at least one refractory metal element selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, and lanthanoids and at least one element selected from the group consisting of Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga.
  • the target further contains at least one chalcogen element selected the group consisting of S, Se, and Te.
  • a method for producing a target containing a chalcogen element includes the step of forming an alloy ingot using at least one refractory metal element selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, and lanthanoids and an additional element outside of the group, and also includes the step of pulverizing the alloy ingot.
  • the method further includes the step of forming a target using the pulverized alloy ingot and at least one chalcogen element selected from the group consisting of S, Se, and Te.
  • a memory including a plurality of memory devices.
  • the memory devices are formed using a target and have an ionization layer containing an element to be ionized.
  • the target used contains at least one refractory metal element selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, and lanthanoids and at least one element selected from the group consisting of Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga.
  • the target also contains at least one chalcogen element selected the group consisting of S, Se, and Te.
  • the memory according to this embodiment is configured such that the ionization layer of the memory devices is formed using the target according to the above embodiment.
  • a method for producing a memory including a plurality of memory devices includes the step of forming an alloy ingot using at least one refractory metal element selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, and lanthanoids and an additional element outside of the group, and also includes the step of pulverizing the alloy ingot.
  • the method further includes the step of forming a target using the pulverized alloy ingot and a chalcogen element, and the step of forming an ionization layer of the memory devices by sputtering using the alloy target, the ionization layer containing an element to be ionized.
  • the method for producing a memory according to this embodiment applies the method for producing a target according to the above embodiment, and uses a target produced by such a method to form the ionization layer of each memory device.
  • the target according to the above embodiment contains a refractory metal element, at least one element selected from the group consisting of Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga, and a chalcogen element. Therefore, a novel target containing these elements can be achieved.
  • the method for producing a target according to the above embodiment includes the step of forming an alloy ingot using a refractory metal element and an additional element outside of the group of refractory metal elements, followed by the step of pulverizing the alloy ingot.
  • a refractory metal element that is highly ignitable in the form of a powder
  • such an element can be used as a powder material for sintering with less risk of ignition.
  • the melting point of the alloy ingot is lower than the melting point of the refractory metal element, the difference from the melting point of the chalcogen element is reduced.
  • a target containing a refractory metal element and a chalcogen element can be produced with less risk of ignition at the time of sintering.
  • the memory according to the above embodiment is configured such that the ionization layer of the memory devices is formed using the target according to the embodiment of the invention. Therefore, an ionization layer containing a refractory metal element can be formed using only one target.
  • the method for producing a memory according to the above embodiment applies the method for producing a target according to the embodiment of the invention, and uses a target produced by such a method to form the ionization layer of memory devices.
  • the target containing a refractory metal element and a chalcogen element can be produced with less risk of ignition at the time of pulverization or sintering, and the use of such a target allows an ionization layer containing a refractory metal element to be formed using only one target.
  • the target according to the above embodiment makes it possible to form a layer containing a refractory metal element, a chalcogen element, and an additional metal element by sputtering using only one target.
  • a heretofore non-existing, novel target can thus be achieved.
  • the method for producing a target according to the above embodiment of the invention allows a target containing a refractory metal element and a chalcogen element to be formed with less risk of ignition at the time of pulverization or sintering.
  • a target can be increased in size to correspond to the increased size of a wafer, making it possible to form a film on a large-diameter wafer.
  • the memory and the method for producing the same allow the ionization layer of the memory devices forming the memory, which contains a refractory metal element, to be formed using only one target.
  • the production apparatus can be simplified, significantly increasing the throughput.
  • FIG. 1 is a schematic cross-section of a memory device that forms a memory according to an embodiment of the invention.
  • FIG. 2 shows the I—V characteristics of memory devices forming a memory of Example 1.
  • FIG. 3 shows the R—V characteristics of memory devices forming the memory of Example 1.
  • FIG. 4 shows the resistance of memory devices forming the memory of Example 1 at the time of repeated rewriting of the memory devices.
  • FIG. 5 shows a comparison of the change in the initial resistance of memory devices (median value) between samples of Example 1 and Comparative Example 2.
  • a target according to an embodiment of the invention contains a refractory metal element, an additional element (metal element) that is not a refractory metal element, and a chalcogen element.
  • the refractory metal element is at least one refractory metal element selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, and lanthanoids (Ln) (group of elements M1).
  • the additional element (metal element) that is not a refractory metal element is at least one element selected from the group consisting of Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga (group of element M2).
  • the chalcogen element is at least one chalcogen element selected the group consisting of S, Se, and Te.
  • a layer containing the three kinds of elements can thus be formed by sputtering using one target, and, therefore, as compared with sputtering using a plurality of targets, the layer can be provided with a more stable composition.
  • a method for producing a target according to an embodiment of the invention is a method for producing a target containing a chalcogen element, and includes the following steps:
  • the method for producing a target according to the embodiment includes the step (1) of forming an alloy ingot and the step (2) of pulverizing the alloy ingot.
  • a refractory metal element that is highly ignitable in the form of a powder can be used as a powder with less risk of ignition.
  • the melting point of the alloy ingot is lower than the melting point of the refractory metal element, the difference from the melting point of the chalcogen element is reduced.
  • a target containing a refractory metal element and a chalcogen element can be produced with less risk of ignition at the time of sintering.
  • a target can be increased in size to correspond to the increased size of a wafer, making it possible to form a film on a large-diameter wafer.
  • the refractory metal element that serves as a raw material is a material with a particle diameter of 100 or more. As a result, the danger of ignition can be further reduced.
  • the additional element outside of the group of refractory metal elements is at least one element selected from the group consisting of Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga (group of elements M2).
  • group of elements M2 the melting point of the alloy ingot can be sufficiently lower than the melting point of the refractory metal element, reducing the difference from the melting point of the chalcogen element. This facilitates the formation of a target containing a refractory metal element and a chalcogen element.
  • the method for producing a target further includes the following steps:
  • the step (3) of forming a target is performed using the alloy ingot pulverized in the step (2) and the second alloy ingot pulverized in the step (5).
  • the second alloy ingot has a melting point higher than the melting point of the chalcogen element. This facilitates sintering in the production of the second alloy ingot and thus is advantageous.
  • the additional element that is not a chalcogen element may be at least one element selected from the group consisting of Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga (group of elements M2).
  • a memory according to an embodiment of the invention is a memory including a plurality of memory devices.
  • the memory devices have an ionization layer containing an element to be ionized.
  • the ionization layer of the memory devices is formed using the target according to the above embodiment.
  • a method for producing a memory according to an embodiment of the invention applies the method for producing a target according to the above embodiment to the production of a memory including a plurality of memory devices, and uses a target produced by such a method to form an ionization layer of the memory devices.
  • a target containing a refractory metal element and a chalcogen element can be produced with less risk of ignition at the time of pulverization or sintering, and the use of such a target allows an ionization layer containing a refractory metal element to be formed using only one target.
  • the memory and the method for producing the same allow the ionization layer to be formed using only one target, and, therefore, as compared with the case of using a plurality of targets as in co-sputtering, the number of cathodes in a film formation apparatus for forming the ionization layer can be reduced.
  • the production apparatus can be simplified, significantly increasing the throughput.
  • the memory according to the embodiment of the invention has an ionization layer formed using the target according to the embodiment of the invention. Accordingly, the formed ionization layer contains the same elements as the target, i.e., a refractory metal element (element of the group of elements M1), an additional metal element that is not a refractory metal element (element of the group of elements M2), and a chalcogen element.
  • a refractory metal element element of the group of elements M1
  • an additional metal element that is not a refractory metal element (element of the group of elements M2)
  • chalcogen element chalcogen element
  • the chalcogen element serves as an ion conductive material to give negative ions.
  • the group 4A transition metal elements Ti, Zr, and Hf and the group 5A transition metal elements V, Nb, and Ta are ionized to give positive ions. They are reduced on the electrode, forming a conduction path in the metallic state (filament). Cu and like elements of the group of elements M2 also form a conduction path in the metallic state (filament).
  • the ionization layer is provided with a lower electrode and an upper electrode. A voltage is applied through these electrodes to the ionization layer of memory devices to thereby change the resistance of the ionization layer. Using the resistance state of the ionization layer, information can be recorded and retained in each memory device.
  • the metal elements to be ionized (Ti, Zr, etc.) contained in the ionization layer are ionized to positive ions.
  • the positive ions are transferred in the ionization layer (ionic conduction). They combine with electrons on the electrode side and are deposited thereon to form a low-resistance conduction path (filament) reduced to the metallic state at the interface between the ionization layer and the electrode.
  • the resistance of the ionization layer of the memory device is reduced, and the initial high-resistance state is changed into a low-resistance state.
  • the metal elements in the conduction path are oxidized and ionized.
  • the ions dissolve in the ionization layer or combine with the chalcogen element in the ionization layer, whereby the conduction path disappears.
  • the resistance of the ionization layer of the memory device is increased, and the low-resistance state is changed into a high-resistance state.
  • the following describes an embodiment of a memory device that forms a memory and an embodiment of a memory.
  • FIG. 1 shows a schematic cross-section of a memory device that forms a memory according to an embodiment of the invention.
  • the memory device 10 includes a high resistance layer 12 , an ionization layer 13 , and an upper electrode 14 stacked in this order on a lower electrode 11 .
  • the lower electrode 11 is formed on a non-illustrated silicon substrate with a CMOS circuit, for example.
  • Wiring materials for use in semiconductor processes can be used for the lower electrode 11 and the upper electrode 14 , examples thereof including TiW, Ti, W, Cu, Al, Mo, Ta, and silicides.
  • such a Cu electrode may be covered with a material with less ionic conductivity or less thermal diffusivity, such as W, WN, TiN, TaN, or the like.
  • Oxides and nitrides are usable for the high resistance layer 12 .
  • an oxide containing at least one element selected from the group of rare earth elements including La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y, or Si or Cu is used for the high resistance layer 12 .
  • the high resistance layer 12 has a sufficiently higher resistance than the ionization layer 13 .
  • the high resistance layer 12 is formed thinner than other layers so that the current flowing through the memory device 10 is not too small.
  • the ionization layer 13 may include an element to be ionized, an element (chalcogen element) selected from Te, Se, and S, and an additional element.
  • the ionization layer 13 is configured to include a refractory metal element, an additional element (metal element) that is not a refractory metal element, and a chalcogen element.
  • the refractory metal element is at least one refractory metal element selected from the group consisting of Ti, Zr, Hf, V, Nb, Ta, and lanthanoids (Ln) (group of elements M1).
  • the additional element (metal element) that is not a refractory metal element is at least one element selected from the group consisting of Al, Ge, Zn, Co, Cu, Ni, Fe, Si, Mg, and Ga (group of elements M2).
  • the chalcogen element is at least one chalcogen element selected the group consisting of S, Se, and Te.
  • the chalcogen element serves as an ion conductive material to give negative ions.
  • the group 4A transition metal elements Ti, Zr, and Hf, the group 5A transition metal elements V, Nb, and Ta, and Cu of the group of elements M2, for example, are ionized to give positive ions. They are reduced on the electrode, forming a conduction path in the metallic state (filament).
  • Al, Ge, Si, and Mg of the group of elements M2 are oxidized at the interface between the ionization layer 13 and the electrode at the time when the resistance state of the memory device changes from low to high, forming a stable oxide film.
  • the high resistance layer 12 and the ionization layer 13 can be collectively referred to as a “memory layer” for recording and storing information.
  • the memory device 10 thus configured has such characteristics that the impedance of the memory layer (the high resistance layer 12 and the ionization layer 13 ) or the impedance of the ionization layer 13 changes in response to the application of a voltage pulse or a current pulse.
  • the ionization layer 13 of the memory device 10 is formed using a target containing a refractory metal element, an additional element (metal element) that is not a refractory metal element, and a chalcogen element (i.e., the target according to the above embodiment).
  • the ionization layer 13 can be formed using only one target, and, therefore, as compared with the case of using a plurality of targets as in co-sputtering, the number of cathodes in a film formation apparatus for forming the ionization layer 13 can be reduced. Therefore, the production apparatus can be simplified, significantly increasing the throughput.
  • the memory device 10 of this embodiment can be operated as follows to store information.
  • a positive potential (+potential) is applied to the upper electrode 14 to apply a positive voltage to the memory device 10 so that its lower-electrode- 11 side is negative. Ions of the element to be ionized are thus transferred from the ionization layer 13 . They combine with electrons on the lower-electrode- 11 side and are deposited thereon to form a conduction path in the high resistance layer 12 . As a result, the resistance of the high resistance layer 12 is reduced. The resistance of other layers than the high resistance layer 12 is originally lower than that of the high resistance layer 12 . Therefore, the reduction in the resistance of the high resistance layer 12 leads to a reduction in the resistance of the entire memory device 10 .
  • a negative potential is applied to the upper electrode 14 to apply a negative voltage to the memory device 10 so that its lower-electrode- 11 side is positive.
  • the element in the conduction path formed in the high resistance layer 12 is thus oxidized and ionized. They dissolve in the ionization layer 13 or combine with the chalcogen element in the ionization layer 13 to produce a compound.
  • the conduction path disappears from the high resistance layer 12 or decreases, whereby the resistance of the high resistance layer 12 increases.
  • the resistance of other layers than the high resistance layer 12 is originally low, and, therefore, the increase in the resistance of the high resistance layer 12 leads to an increase in the resistance of the entire memory device 10 .
  • the negative voltage is removed to eliminate the voltage on the memory device 10 , whereby the resistance in the high state is retained.
  • the recorded information can thus be erased.
  • the information can be changed from “0” to “1” during the information recording process by the application of a positive voltage, while the information can be changed from “1” to “0” during the information erasing process by the application of a negative voltage.
  • the resistance after recording depends on the recording conditions including the width of the voltage pulse or the current pulse applied for recording, the amount of current, etc., rather than on the cell size of the memory device 10 and the material composition of the high resistance layer 12 .
  • the resistance after recording is within a range of about 50 ⁇ to about 50 k ⁇ .
  • the initial resistance is twice or more the resistance after recording, this is sufficient to recover the recorded data. Therefore, it is sufficient that the resistance before recording is 100 ⁇ and the resistance after recording is 50 ⁇ , or that the resistance before recording is 100 k ⁇ and the resistance after recording is 50 k ⁇ , for example.
  • the initial resistance of the high resistance layer 12 is determined to satisfy such conditions.
  • the resistance of the high resistance layer 12 can be controlled by the amount of oxygen contained in the oxide of the high resistance layer 12 before heating, the thickness of the oxide film, etc., for example.
  • the memory device 10 is configured such that the high resistance layer 12 and the ionization layer 13 are sandwiched between the lower electrode 11 and the upper electrode 14 . Accordingly, when a positive voltage (+potential) is applied to the upper electrode 14 so that the lower-electrode- 11 side is negative, a conduction path containing a large amount of ionized element is formed in the high resistance layer 12 . This reduces the resistance of the high resistance layer 12 , leading to a reduction in the resistance of the entire memory device 10 . When the application of a positive voltage is stopped so that no voltage is applied to the memory device 10 , the resistance in the low state is retained, whereby information can be recorded.
  • a memory (memory device) can be formed by arranging a large number of memory devices 10 in a linear fashion or in a matrix.
  • each memory device 10 for example, a wire is connected to its lower-electrode- 11 side, and another wire is connected to its upper electrode 14 side, so that each memory device 10 is placed near the intersection of these wires.
  • each memory device 10 is further connected via wires to a sense amplifier, an address recorder, record/erase/read circuits, etc.
  • Memories according to embodiments of the invention are applicable to various memories.
  • Examples thereof include a PROM (programmable ROM) that can be written only once, an EEPROM (Electrically Erasable ROM) that can be erased electrically, and a RAM (random access memory) that can be read, erased, and reproduced at high speed.
  • PROM programmable ROM
  • EEPROM Electrically Erasable ROM
  • RAM random access memory
  • a high resistance layer 12 is in contact with the ionization layer 13 in the above embodiment, a high resistance layer is not essential in a memory device that forms a memory according to an embodiment of the invention, and a configuration with no high resistance layer is also possible.
  • a target was actually produced, and a memory including memory devices was produced using the target.
  • the alloy ingot was pulverized in an attritor to prepare an alloy powder with a particle diameter of 106 ⁇ m or less.
  • the alloy powder was mixed with a Te powder with a particle diameter of 75 ⁇ m or less and a Ge power with a particle diameter of 32 to 106 ⁇ m, and the mixture was sintered to give an AlCuGeTeZr target base material.
  • the target base material was then cut into a disc-like piece with a thickness of 5 mm and a diameter of 300 mm to give a target.
  • the prepared target was adhered to the backing plate of a sputtering apparatus using In wax.
  • a Gd oxide film with a thickness of 2 nm was formed as a high resistance layer 12 on a CMOS circuit provided with a lower electrode 11 formed of a W (tungsten) layer.
  • an AlCuGeTeZr layer with a thickness of about 60 nm was formed as an ionization layer 13 .
  • a W layer with a thickness of 50 nm was formed thereon as an upper electrode 14 , thereby forming a memory device 10 having a cross section as shown in FIG. 1 .
  • Example 1 a memory cell array having a large number of memory devices 10 was formed on a wafer to give a sample of the memory of Example 1.
  • the operational characteristics of the memory devices forming the memory of the sample of Example 1 were examined. Specifically, the voltage supplied to the memory devices was varied to examine the change in the current or resistance of the memory devices.
  • FIG. 2 shows the I—V characteristics of the memory devices
  • FIG. 3 shows the R—V characteristics of the memory devices.
  • the memory devices have an initial resistance as high as about 10 M ⁇ . However, by negatively biasing the lower-electrode- 11 side, the memory devices enter a low-resistance state. Then, by positively biasing the lower-electrode- 11 side, the memory devices return to the high-resistance state. This indicates excellent operation of the memory.
  • a voltage pulse with a voltage Vw of 3 V, a current of about 100 ⁇ A, and a pulse width of about 10 ns was applied as a write pulse, while a voltage pulse with a voltage Ve of 2V, and a current of about 100 ⁇ A, and a pulse width of about 10 ns was applied as an erase pulse, and 1,000,000 rewrite operations were performed.
  • the resistance of the memory devices in a high-resistance state and a low-resistance state was measured.
  • FIG. 4 shows the relation between the number of operations and the resistance of the memory devices.
  • FIG. 4 shows that even when rewriting is repeatedly performed, there is no great change in the resistance values in the high-resistance state and the low-resistance state, indicating excellent operational characteristics. That is, the operational characteristics of the memory were excellent.
  • the following materials were used.
  • a powder with a particle diameter of 106 ⁇ m or less was used.
  • Al, Cu, and Ge raw materials of the group of elements M2 an Al powder with a particle diameter 53 to 106 ⁇ m, a Cu powder with a particle diameter of 25 to 35 ⁇ m, and a Ge powder with a particle diameter of 32 to 106 ⁇ m were used, respectively.
  • a powder with a particle diameter of 75 ⁇ m or less as a Te raw material of the group of chalcogen elements sintering was performed.
  • an Al powder as an Al raw material of the group of elements M2 was mixed and dissolved in a high-frequency melting furnace to prepare an AlZr alloy ingot.
  • the prepared alloy ingot was pulverized to give an alloy powder.
  • the target base material was then cut into a disc-like piece with a thickness of 5 mm and a diameter of 300 mm to give a target.
  • Example 2 a memory cell array having a large number of memory devices 10 was formed on a wafer to give a sample of the memory of Example 2.
  • the characteristics of the memory of the sample of Example 2 were evaluated as in Example 1. As a result, the characteristics of the memory were excellent.
  • Example 1 the ionization layer 13 of the memory devices 10 was formed using an AlCuGeTeZr alloy target.
  • an ionization layer 13 of memory devices 10 herein was formed by a co-sputtering method, in which four kinds of targets, Al, Zr, Cu, and GeT, were simultaneously discharged.
  • a memory cell array having a large number of memory devices 10 was formed on a wafer to give a sample of the memory of Comparative Example 2.
  • Example 1 With respect to the case of Example 1 where an alloy target was used in the film formation and the case of Comparative Example 2 where co-sputtering was employed in the film formation, the initial resistance of the memory devices 10 of the sample of each memory was measured to evaluate the variation.
  • FIG. 5 shows the variation in the initial resistance (median) of memory devices depending on the frequency of film formation, i.e., the number of wafers (1 to 11).
  • FIG. 5 shows that in the case of Comparative Example 2 where co-sputtering was employed in the film formation, the resistance increases with an increase in the frequency of film formation. Meanwhile, in the case of Example 1 where an alloy target was used in the film formation, the resistance does not greatly vary with an increase in the frequency of film formation.
  • the target used has the same components as those of the film to be formed. Therefore, even when elements adhere to the target, the components thereof are the same as the target components. There thus is only a small influence of adhesion of unwanted elements.

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CN110129759A (zh) * 2019-06-27 2019-08-16 江阴恩特莱特镀膜科技有限公司 一种用于Low-E玻璃的硅铝锆靶材及其制备方法
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US8426839B1 (en) 2009-04-24 2013-04-23 Adesto Technologies Corporation Conducting bridge random access memory (CBRAM) device structures
US9099633B2 (en) 2012-03-26 2015-08-04 Adesto Technologies Corporation Solid electrolyte memory elements with electrode interface for improved performance
CN104379802A (zh) * 2012-07-20 2015-02-25 株式会社钢臂功科研 靶组装体
US9412945B1 (en) 2013-03-14 2016-08-09 Adesto Technologies Corporation Storage elements, structures and methods having edgeless features for programmable layer(s)
US9711719B2 (en) 2013-03-15 2017-07-18 Adesto Technologies Corporation Nonvolatile memory elements having conductive structures with semimetals and/or semiconductors
US10854435B2 (en) 2014-03-25 2020-12-01 Jx Nippon Mining & Metals Corporation Sputtering target of sintered Sb—Te-based alloy
CN106164329A (zh) * 2014-03-28 2016-11-23 捷客斯金属株式会社 包含Al‑Te‑Cu‑Zr合金的溅射靶及其制造方法
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US10069066B2 (en) 2018-09-04
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