US20100073344A1 - Pixel circuit and display device - Google Patents

Pixel circuit and display device Download PDF

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Publication number
US20100073344A1
US20100073344A1 US12/312,144 US31214407A US2010073344A1 US 20100073344 A1 US20100073344 A1 US 20100073344A1 US 31214407 A US31214407 A US 31214407A US 2010073344 A1 US2010073344 A1 US 2010073344A1
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pixel circuit
driving transistor
power supply
capacitor
switching
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Seiji Ohhashi
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Sharp Corp
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Priority claimed from PCT/JP2007/068681 external-priority patent/WO2008093451A1/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67748—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber horizontal transfer of a single workpiece

Definitions

  • the present invention relates to a pixel circuit and a display device, such as an organic EL (Electro Luminescence) display or an electric field emission display (FED: Field Emission Display), to each of which a current-driven transistor is applied.
  • a display device such as an organic EL (Electro Luminescence) display or an electric field emission display (FED: Field Emission Display) to each of which a current-driven transistor is applied.
  • the relationship between the luminance and voltage of an organic EL element is easily changed by driving time, ambient temperature, and the like. Therefore, it is extremely difficult for a voltage-controlled driving method to suppress variations in luminance. However, there is a proportional relationship between the luminance and current of an organic EL element, and the relationship is less affected by an external factor such as ambient temperature. Therefore, as a method for driving an organic EL display, a current-controlled driving method is preferred.
  • TFTs Thin Film Transistors
  • amorphous silicon, low-temperature polycrystalline silicon, or CG (Continuous Grain) silicon is used.
  • CG Continuous Grain
  • pixel circuits for compensating for variations in TFT characteristics are classified broadly into two types: current-programmed pixel circuits; and voltage-programmed pixel circuits.
  • a current-programmed pixel circuit uses a current signal to program the value of a current flowing through a driving TFT
  • a voltage-programmed pixel circuit uses a voltage signal to program the value of a current flowing through a driving TFT.
  • the current-programmed pixel circuit can correct the threshold voltage and mobility of the driving TFT.
  • the voltage-programmed pixel circuit corrects the threshold voltage only.
  • it is difficult to design a current-programmed pixel or driver circuit because such a circuit is required to handle an extremely minute current value.
  • the current-programmed pixel circuit is greatly influenced by parasitic capacitance in terms of the period of time required to program a current value, and it is therefore not easy to extend the area of such a circuit.
  • the voltage-programmed pixel circuit cannot correct TFT mobility, the voltage-programmed pixel circuit uses a voltage signal to program a current value, and as such, is only slightly influenced by parasitic capacitance or the like, and it is therefore comparatively easy to design such a circuit.
  • the influence of variations in mobility on a current value is smaller than the influence of variations in threshold voltage on a current value, and it is therefore expected that the influence of variations in mobility can be curbed to some extent in the process of fabricating TFTs. Therefore, it is possible for even a voltage-programmed display device to give sufficient display quality.
  • FIG. 8 illustrates a circuit configuration disclosed in Patent Literature 1.
  • a pixel circuit Aij 100 illustrated in FIG. 8 includes a driving TFT 110 , switching TFTs 120 , 121 , and 122 , capacitors 140 and 141 , and an organic EL element (OLED: Organic Light Emitting Diode) 150 .
  • the driving TFT 110 and the switching TFTs 120 , 121 , and 122 are all p-channel TFTs.
  • the pixel circuit Aij 100 is configured such that from a power source line 164 (+VDD) to a common cathode (GND), the driving TFT 110 , the switching TFT 121 , and the organic EL element 150 are connected in series in this order. Between a gate terminal G of the driving TFT 110 and a data line 160 , the capacitor 140 and the switching TFT 122 are connected in series. Furthermore, the switching TFT 120 is connected between the gate terminal G of the driving TFT 110 and a drain terminal D of the driving TFT 110 , and the capacitor 141 is connected between the gate terminal G of the driving TFT 110 and the power source line 164 .
  • a gate terminal G of the switching TFT 122 , a gate terminal G of the switching TFT 120 , and a gate terminal G of the switching TFT 121 are connected to a select line 161 , an auto zero line 162 , and an illumination line 163 , respectively.
  • FIG. 9 illustrates an example of operation timing of the pixel circuit Aij 100 .
  • the potentials of the auto zero line 162 and the illumination line 163 are set to Low, so that the switching TFTs 120 and 121 become conductive and the drain and gate terminals D and G of the driving TFT 110 becomes equal in potential.
  • the driving TFT 110 is also conductive and a current flows from the power source line 164 through the driving TFT 110 and the switching TFT 121 to the organic EL element 150 .
  • the potential of the data line 160 is set to a standard potential Vstd and the potential of a terminal of the capacitor 140 on the side of the switching TFT 122 is set to the standard potential Vstd by setting the potential of the select line 161 to Low.
  • the potential of the auto zero line 162 is set to High, so that the switching TFT 120 becomes non-conductive.
  • the difference between the potential of the gate terminal G of the switching TFT 120 and the standard potential Vstd is stored in the capacitor 140 . That is, when the potential of the data line 160 is the standard potential Vstd, the potential of the gate terminal G of the driving TFT 110 takes on the value (+VDD+Vth) corresponding to a threshold state (where the difference in voltage between the gate terminal G of the driving TFT 110 and a source terminal S of the driving TFT 110 is the threshold voltage Vth).
  • the potential of the data line 160 is changed from the standard potential Vstd to a data voltage Vdata.
  • the potential of the gate terminal G of the driving TFT 110 is changed by a difference in potential between the standard potential Vstd and the data voltage Vdata.
  • the driving TFT 110 is set to the threshold state, so that a current corresponding to the difference in potential between the standard potential Vstd and the data voltage Vdata flows. Therefore, it is possible to determine the value of a current by the difference in potential between the standard potential Vstd and the data voltage Vdata regardless of the threshold voltage Vth of the driving TFT 110 .
  • the potential of the select line 161 is set to High, so that the switching TFT 122 becomes non-conductive, whereby the potential of the gate terminal G of the driving TFT 110 is kept as a voltage between terminals of the capacitor 141 and a select period of the pixel circuit Aij 100 is ended. Thereafter, the potential of the illumination line 163 is set to Low, so that the current whose value has been set during the fourth period flows through the driving TFT 110 to the organic EL element 150 .
  • the current flowing through the driving TFT 110 is determined without being affected by variations in the threshold voltage Vth of the driving TFT 110 . Therefore, the value of a current to be outputted to the organic EL element 150 can be set without being affected by the variations in the threshold voltage Vth of the driving TFT 110 .
  • FIG. 10 illustrates a pixel circuit disclosed in Patent Literature 2.
  • a pixel circuit Aij 200 illustrated in FIG. 10 includes a driving TFT 210 , switching TFTs 220 , 221 , and 222 , capacitors 240 and 241 , and an organic EL element 250 .
  • the driving TFT 210 and the switching TFTs 220 , 221 , and 222 are all n-channel TFTs.
  • the pixel circuit Aij 200 illustrated in FIG. 10 is configured such that from a common anode (GND) to a power source line 263 , the organic EL element 250 and the switching TFT 210 are connected in series in this order.
  • GND common anode
  • the switching TFT 220 is connected between a gate terminal G of the driving TFT 210 and a drain terminal D of the driving TFT 210 , and the capacitor 240 is connected between the gate terminal G of the driving TFT 210 and the power source line 263 . Between a data line 260 and the gate terminal G of the driving TFT 210 , the switching TFT 222 and the capacitor 241 are connected in series in this order.
  • the switching TFT 221 is connected between the node A and the power source line 263 .
  • a gate terminal G of the switching TFT 222 and a gate terminal G of the switching TFT 221 are connected to a select line 262 and a reset line 261 , respectively.
  • FIG. 11 illustrates an example of operation timing of the pixel circuit Aij 200 .
  • the potential of the power source line 263 is at a high level (High), and then the potential of the reset line 261 is set to High, so that the switching TFTs 221 and 220 become conductive. Therefore, the potential of the node A is the High potential of the power source line 263 , and the gate and drain terminals G and D of the driving TFT 210 are short-circuited.
  • the potential of the power source line 263 is set to 0 (zero) voltage, whereby the potential of the node A is set to 0 voltage. With this, the threshold voltage Vth of the driving TFT 210 is stably detected.
  • a current flows from the drain terminal D of the driving TFT 210 to the source terminal S of the driving TFT 210 so that the gate voltage of the driving TFT 210 drops and the voltage between the gate and source terminals G and S of the driving TFT 210 drops to a value equal to the threshold voltage Vth of the driving TFT 210 .
  • the potential of the reset line 261 is set to Low, so that the switching TFTs 221 and 220 become non-conductive, whereby the voltage between the gate and source terminals G and S of the driving TFT 210 is kept at the threshold voltage Vth of the driving TFT 210 .
  • the potential of the select line 262 is set to High, so that the switching TFT 222 becomes conductive and the potential of the node A becomes Vdata, which is the potential of the data line 260 .
  • the gate potential of the driving TFT 210 becomes the threshold voltage Vth+ (Vdata- 0 ).
  • Vdata- 0 shows a difference in potential of the node A between a period (4) and the period (2).
  • the potential of the select line 262 is set to Low, so that the switching TFT 222 becomes non-conductive.
  • a voltage applied to the power source line 263 is changed to a low level (Low), whereby a lower voltage is applied to the source terminal S of the driving TFT 210 than a voltage applied to the drain terminal D of the driving TFT 210 .
  • the threshold voltage Vth+ (Vdata- 0 ) for applying a desired current is kept. Therefore, the current also flows through the organic EL element 250 , whereby desired luminance is obtained.
  • the current flowing through the driving TFT 210 is determined without being affected by variations in the threshold voltage Vth. Therefore, the value of a current to be outputted to the organic EL element 250 can be set without being affected by the variations in the threshold voltage Vth of the TFT.
  • the use of the pixel circuit Aij 100 illustrated in FIG. 8 makes it possible to pass a desired current through the organic EL element 150 regardless of the threshold voltage Vth of the driving TFT 110 .
  • the pixel circuit Aij 100 in the conventional display device has such a problem that it is necessary to set the gate potential of the driving TFT 110 by setting the voltage between the gate and source terminals G and S of the driving TFT 110 to the threshold voltage Vth (correcting the threshold voltage) during the period in which the potential of the select line 161 is Low and, then, by changing the potential of the data line 160 to the data voltage Vdata, in order that a desired current flows from the driving TFT 110 to the organic EL element 150 .
  • a period in which the potential of the select line 161 is Low is about 34.7 ⁇ sec at a maximum, provided the number of select lines is 480 and the frame frequency is 60 Hz.
  • a desired current can be passed through the organic EL element 250 regardless of the threshold voltage Vth of the driving TFT 210 .
  • time for correcting the threshold of the driving TFT 210 is independent of time for setting the potential of the reset line 261 to High.
  • the present invention has been made in consideration of the aforementioned conventional problems. It is an object of the present invention to provide a pixel circuit and a display device each of which allows freely setting a period for compensation of the threshold voltage of a driving transistor and further reducing power consumption.
  • a pixel circuit of the present invention disposed so as to correspond to each intersection between a scanning line and a data line, which includes a current-driven electrooptic element and to which a display signal corresponding to a driving current of the electrooptic element is written through the data line
  • the pixel circuit includes: first and second power supply wires; a third power supply wire for supplying a constant voltage; a driving transistor for determining, in accordance with the display signal, a current that is passed through a first path connecting the first power supply wire with the second power supply wire; first and second switching elements; and first and second capacitors, the driving transistor and the electrooptic element being connected in series on the first path, the first switching element being provided between gate and drain terminals of the driving transistor, the first capacitor and the second switching element being connected in series in this order between the gate terminal of the driving transistor and the data line, the gate terminal of the driving transistor being connected through the second capacitor to the third power supply wire, a first end of the second capacitor being connected between the first capacitor and the second switching element and a second
  • the driving transistor which determines, in accordance with the display signal, the current that is passed through the first path connecting the first power supply wire with the second power supply wire, and the electrooptic element are connected in series on the first path.
  • the first switching element is provided between the gate and drain terminals of the driving transistor.
  • the first capacitor and the second switching element are connected in series in this order between the gate terminal of the driving transistor and the data line.
  • the third power supply wire for supplying the constant voltage is connected through the second capacitor to the gate terminal of the driving transistor.
  • the third power supply wire for supplying the constant voltage is connected through the second capacitor to the gate terminal of the driving transistor.
  • the first end of the second capacitor is connected between the first capacitor and the second switching element and the second end of the second capacitor is connected to the third power supply wire, or the first end of the second capacitor is connected between the gate terminal of the driving transistor and the first capacitor and the second end of the second capacitor is connected to the third power supply wire.
  • the gate-source voltage of the driving transistor when the gate-source voltage of the driving transistor is set to the threshold voltage of the driving transistor, the gate-source voltage can be set to the threshold voltage through the second capacitor by supplying the constant voltage from the third power supply wire, without the need of making the second switching element conductive.
  • the gate-source voltage of the driving transistor can be set to the threshold voltage of the driving transistor regardless of time for making the second switching element conductive. Therefore, there is no lack of a period for compensation of the threshold voltage of the driving transistor.
  • the third power supply wire to which the second capacitor has been connected, supplies the constant voltage throughout all periods. Therefore, the second capacitor consumes less power than in a case where the voltage is changed.
  • the pixel circuit of the present invention is preferably configured to include a third switching element connected between (i) the third power supply wire and (ii) a point between the first capacitor and the second switching element, wherein the first end of the second capacitor is connected between the first capacitor and the second switching element and the second end of the second capacitor is connected to the third power supply wire.
  • a method of securing the potential of one end of the first capacitor by making the second switching element conductive requires switching between supplying the constant voltage to the data line and supplying a data voltage to the data line.
  • the need of making the second switching element conductive is eliminated by making the third switching element conductive in temporarily setting the gate-source voltage of the driving transistor to not less than the threshold voltage of the driving transistor.
  • the second capacitor is also connected to the third power supply wire, and the third power supply wire supplies the constant voltage throughout all periods. Therefore, the second capacitor consumes less power than in a case where the voltage is changed.
  • the pixel circuit of the present invention is preferably configured to include a third switching element connected between (i) the third power supply wire and (ii) a point between the first capacitor and the second switching element, wherein the first end of the second capacitor is connected between the gate terminal of the driving transistor and the first capacitor and the second end of the second capacitor is connected to the third power supply wire.
  • the third power supply wire for supplying the constant voltage and (ii) the point between the first capacitor and the second switching element are connected through the third switching element. Therefore, the need of making the second switching element conductive can be eliminated by making the third switching element conductive in temporarily setting the gate-source voltage of the driving transistor to not less than the threshold voltage of the driving transistor.
  • a route on which the gate terminal of the driving transistor is connected through the first capacitor and the third switching element to the third power supply wire and (ii) a route on which the gate terminal of the driving transistor is connected through the second capacitor to the third power supply wire are provided in parallel with each other so as to extend from the gate terminal of the driving transistor to the third power supply wire.
  • the second capacitor has one end connected to the third power supply wire, and the third power supply wire supplies the constant voltage throughout all periods. This causes the second capacitor to consume less power than in a case where the voltage is changed.
  • the gate-source voltage of the driving transistor can be set to the threshold voltage of the driving transistor regardless of time for making the second switching element conductive. This makes it possible to obtain a high-quality display and to realize a pixel circuit that allows further reducing power consumption.
  • the pixel circuit of the present invention is preferably configured such that the third power supply wire is the first power supply wire.
  • the pixel circuit of the present invention is preferably configured such that a voltage applied to the electrooptic element is reverse-biased during a period in which a gate-source voltage of the driving transistor is set to a threshold voltage of the driving transistor.
  • the pixel circuit of the present invention is preferably configured such that a voltage applied to the electrooptic element is less than a light-emitting threshold voltage of the electrooptic element during a period in which a gate-source voltage of the driving transistor is set to a threshold voltage of the driving transistor.
  • a pixel circuit disposed so as to correspond to each intersection between a scanning line and a data line, which includes a current-driven electrooptic element, the pixel circuit includes: first to third power supply wires; a control wire; a driving transistor; first and second switching transistors; and first and second capacitors, the electrooptic element being connected between the first power supply wire and a second conducting terminal of the driving transistor, a first conducting terminal of the driving transistor being connected to the second power supply wire, the second conducting terminal of the driving transistor being connected through the first switching transistor to a control terminal of the driving transistor, a control terminal of the first switching transistor being connected to the control wire, the control terminal of the driving transistor being connected through the first capacitor to a node, the node being connected through the second switching transistor to the data line, a control terminal of the second switching transistor being connected to the scanning line, the node being connected through the second capacitor to the third power supply wire.
  • the present pixel circuit makes it possible to compensate for the threshold voltage of the driving transistor outside (during any period other than) the select period of the scanning line.
  • the third power supply wire, to which the second capacitor is connected only needs to supply a constant potential, the second capacitor only needs to consume a small amount of power.
  • the pixel circuit of the present invention may further include a third switching transistor, wherein: the node is connected through the third switching transistor to the third power supply wire; and a control terminal of the third switching transistor is connected to the control wire. This makes it possible to charge the first and second capacitors from the third power supply wire (without the need of using a source line).
  • a pixel circuit disposed so as to correspond to each intersection between a scanning line and a data line, which includes a current-driven electrooptic element, the pixel circuit includes: first to third power supply wires; a control wire; a driving transistor; first and second switching transistors; and first and second capacitors, the electrooptic element being connected between the first power supply wire and a second conducting terminal of the driving transistor, a first conducting terminal of the driving transistor being connected to the second power supply wire, the second conducting terminal of the driving transistor being connected through the first switching transistor to a control terminal of the driving transistor, a control terminal of the first switching transistor being connected to the control wire, the control terminal of the driving transistor being connected to a first node, the first node being connected through the first capacitor to a second node, the second node being connected through the second switching transistor to the data line, a control terminal of the second switching transistor being connected to the scanning line, the first node being connected through the second capacitor to the third power supply wire.
  • the present pixel circuit makes it possible to compensate for the threshold voltage of the driving transistor outside (during any period other than) the select period of the scanning line.
  • the third power supply wire, to which the second capacitor is connected only needs to supply a constant potential, the second capacitor only needs to consume a small amount of power.
  • the pixel circuit of the present invention may further comprise a third switching transistor, wherein the second node is connected through the third switching transistor to the third power supply wire; and a control terminal of the third switching transistor is connected to the control wire.
  • the pixel circuit of the present invention may also be configured such that during a period between a point of time where a current is passed through the driving transistor by the first and second capacitors' being charged in a state where the first switching transistor is ON and a point of time where a potential of the control terminal of the driving transistor is changed to take on a value at which the driving transistor is turned OFF, a voltage applied to the electrooptic element takes on a value to be reverse-biased or a value less than a light-emitting threshold voltage.
  • the pixel circuit of the present invention is preferably configured such that the electrooptic element is an organic EL element.
  • the pixel circuit of the present invention is preferably configured such that at least the driving transistor is constituted by an insulated gate field effect transistor.
  • the pixel circuit of the present invention is preferably configured such that each of the driving transistor and the switching elements is constituted by a thin-film transistor.
  • the pixel circuit of the present invention may also be configured such that the thin-film transistor is made of amorphous silicon.
  • amorphous silicon when the pixel circuit is driven by using amorphous silicon, it takes time to set the gate-source voltage of the driving transistor to the threshold voltage of the driving transistor, because amorphous silicon is lower in mobility than low-temperature polycrystalline silicon or CG (Continuous Grain) silicon.
  • the time for setting the gate-source voltage of the driving transistor to the threshold voltage of the driving transistor is independent of time for writing the data voltage (time for pixel selection). This makes it possible to realize a pixel circuit that gives a high-quality display.
  • the pixel circuit of the present invention may be configured such that each of the switching elements is constituted by an n-channel transistor.
  • the insulated gate field effect transistor to be disposed in the pixel circuit can be fabricated by the same process. This makes it possible to avoid such a complication in process as an increase in variety of masks and the like due to a mixture of different channel polarities. This brings about an effect of reducing the cost of a display device. Moreover, sameness in channel polarity of transistors makes it possible to dispose two transistors in close proximity, so that a larger number of transistors can be disposed for the same area.
  • a display device including a pixel circuit as set forth above includes: a scanning signal output circuit; and a display signal output circuit, the pixel circuit being made writable by a scanning signal outputted from the scanning signal output circuit to the scanning line, a display signal corresponding to a driving current of the electrooptic element being written from the display signal output circuit through the data line to the pixel circuit thus made writable.
  • the aforementioned invention makes it possible to provide a display device including a pixel circuit that allows freely setting a period for compensation of the threshold voltage of a driving transistor and further reducing power consumption.
  • a pixel circuit of the present invention includes: first and second power supply wires; a third power supply wire for supplying a constant voltage; a driving transistor for determining, in accordance with the display signal, a current that is passed through a first path connecting the first power supply wire with the second power supply wire; first and second switching elements; and first and second capacitors, the driving transistor and the electrooptic element being connected in series on the first path, the first switching element being provided between gate and drain terminals of the driving transistor, the first capacitor and the second switching element being connected in series in this order between the gate terminal of the driving transistor and the data line, the gate terminal of the driving transistor being connected through the second capacitor to the third power supply wire, a first end of the second capacitor being connected between the first capacitor and the second switching element and a second end of the second capacitor being connected to the third power supply wire or a first end of the second capacitor being connected between the gate terminal of the driving transistor and the first capacitor and a second end of the second capacitor being connected to the third power supply wire.
  • the display device of the present invention is a display device including a pixel circuit as set forth above, the display device including: a scanning signal output circuit; and a display signal output circuit, the pixel circuit being made writable by a scanning signal outputted from the scanning signal output circuit to the scanning line, a display signal corresponding to a driving current of the electrooptic element being written from the display signal output circuit through the data line to the pixel circuit thus made writable.
  • FIG. 1 A first figure.
  • FIG. 1 showing an embodiment of a display device according to the present invention, is a circuit diagram illustrating a configuration of a pixel circuit.
  • FIG. 2 is a block diagram illustrating an overall configuration of the display device according to the present invention.
  • FIG. 3 is a timing chart illustrating operation of the pixel circuit in the display device according to the present invention.
  • FIG. 4 is a circuit diagram illustrating a configuration of a modification of the pixel circuit in the display device according to the present invention.
  • FIG. 5 is a circuit diagram illustrating a configuration of another embodiment of the pixel circuit in the display device according to the present invention.
  • FIG. 6 is a timing chart illustrating operation of the another embodiment of the pixel circuit in the display device according to the present invention.
  • FIG. 7 is a circuit diagram illustrating a configuration of still another embodiment of the pixel circuit in the display device according to the present invention.
  • FIG. 8 is a circuit diagram illustrating a configuration of a pixel circuit in a conventional display device.
  • FIG. 9 is a timing chart illustrating operation of the pixel circuit in the conventional display device.
  • FIG. 10 is a circuit diagram illustrating a configuration of another pixel circuit in the conventional display device.
  • FIG. 11 is a timing chart illustrating operation of the another pixel circuit in the conventional display device.
  • Vcom Common anode First power supply wire
  • Vp Power supply wire (Second power supply wire)
  • Vref Power supply wire (Third power supply wire)
  • a switching element for use in the present embodiment can be constituted by a low-temperature polysilicon TFT, a CG (Continuous Grain) silicon TFT, or an amorphous silicon TFT. Configurations of such TFTs and processes for fabricating such TFTs are publicly known, and as such, are not described here. Moreover, a configuration of an organic EL element serving as an electrooptic element for use in the present embodiment is also publicly known, and as such, is not described here.
  • FIG. 2 illustrates a configuration of a display device 10 of the present embodiment.
  • the pixel circuits Aij are disposed in a matrix pattern so as to correspond to the intersections between a plurality of data lines Sj arranged in parallel with one another and a plurality of scanning lines Gi crossing at right angles to the data lines Sj and arranged in parallel with one another.
  • the data lines Sj are connected to the source driver circuit 1 so as to supply signals to the pixel circuit Aij.
  • the scanning lines Gi are connected to the gate driver circuit 2 .
  • the source driver circuit 1 includes an m-bit shift register 1 a, a register 1 b, a latch 1 c, and m D/A converters 1 d.
  • the shift register 1 a which includes m cascade-arranged registers, transfers, in synchronization with a clock CLK, a start pulse SP inputted from the control circuit 3 to a first register (not illustrated) and outputs the start pulse SP as timing pulses DLP from output stages of the registers.
  • the register 1 b receives display data DA from the control circuit 3 at the timing of input of the timing pulses.
  • the latch circuit 1 c receives the column of display data DA in synchronization with a latch pulse LP inputted from the control circuit 3 to the latch 1 c.
  • Each piece of display data DA retained in the latch 1 c is outputted to a D/A converter 1 d corresponding to that piece of display data DA.
  • the D/A converters 1 d are provided in one-to-one correspondence with the data lines Sj.
  • Each of the D/A converters 1 d supplies its corresponding data line Sj with display data DA inputted from the latch 1 c, in the form of an analog signal voltage Da.
  • the gate driver circuit 2 includes a shift register circuit, a logic circuit, and a buffer, none of which is illustrated.
  • the gate driver circuit 2 receives a start pulse YI, transfers the start pulse YI in the shift register circuit in synchronization with a clock YCK, uses the logic circuit to perform a logic operation with pulses outputted from output stages of the shift register circuit and a timing signal OE, and outputs a necessary voltage through the buffer to the corresponding scanning line Gi and the corresponding control wire Wi.
  • To each of the scanning lines Gi a plurality of pixel circuits Aij are connected. The pixel circuits Aij are scanned by the scanning line Gi as a group.
  • the source driver circuit 1 is a line-sequential scanning circuit for transmitting data to a single scanning line of pixel circuits Aij at a time. Furthermore, the source driver circuit 1 may also be a dot-sequential scanning circuit for sequentially transmitting data to the pixels one by one. Here, a specific description of the dot-sequential scanning circuit is omitted.
  • the control circuit 3 is a circuit for outputting the start pulse SP, the clock CLK, the display data DA, and the latch pulse LP to the source driver circuit 1 . Moreover, the control circuit 3 outputs the timing signal OE, the start pulse YI, and the clock YCK, which are to be given to the gate driver circuit 2 . Furthermore, in a region where a pixel circuit Aij is disposed, a power supply wire Vp, a common anode Vcom, and a power supply wire Vref are disposed. This will be described later.
  • the description of the present embodiment refers the common anode Vcom, the power supply wire Vp, and the power supply wire Vref for supplying a constant voltage Va as a first power supply wire, a second power supply wire, and a third power supply wire, respectively.
  • the after-mentioned switching TFTs 22 , 23 , and 34 correspond to first, second, and third switching elements of the present invention, respectively.
  • the after-mentioned capacitors C 1 or C 1 ′ and C 2 correspond to first and second capacitors of the present invention, respectively.
  • an organic EL element ELD for use in the present embodiment corresponds to an electrooptic element of the present invention, and is a current-driven electrooptic element.
  • the following describes embodiments of the pixel circuits Aij provided in the display device 10 .
  • FIG. 1 is a circuit diagram illustrating a configuration of a pixel circuit Aij 20 of the present embodiment.
  • the pixel circuit Aij 20 includes: a driving TFT 21 serving as a driving transistor; switching TFTs 22 and 23 ; capacitors C 1 and C 2 ; and an organic EL element ELD. It should be noted that the driving TFT 21 and the switching TFTs 22 and 23 are all n-channel TFTs.
  • the driving TFT 21 and the organic EL element ELD are connected in series in this order on a first path connecting a common anode Vcom. (first power supply wire) with a power supply wire Vp (second power supply wire) so that the driving TFT 21 faces a power supply wire Vp.
  • the driving TFT 21 is a driving transistor for supplying a driving current to the organic EL element ELD.
  • a fixed potential VDD is applied to the common anode Vcom, which serves as a common electrode for the corresponding organic EL element ELD.
  • the switching TFT 22 is connected between a gate terminal G (a terminal of the driving TFT 21 which is indicated by G in FIG. 1 ) serving as a gate of the driving TFT 21 and a drain terminal D (a terminal of the driving TFT 21 which is indicated by D in FIG. 1 ). Furthermore, the capacitors C 1 and C 2 are connected between the gate terminal G of the driving TFT 21 and a power supply wire Vref, to which a constant voltage Va is applied. Moreover, the power supply wire Vref may be the common anode Vcom. In this case, the number of wires can be reduced, whereby the display device 10 can realize a high aperture ratio. The same applies to the embodiments described later.
  • the switching TFT 23 is connected between the node K and a data line Sj. Moreover, a gate terminal G of the switching TFT 23 and a gate terminal G of the switching TFT 22 are connected to a scanning line Gi and a control wire Wi, respectively.
  • the pixel circuit Aij 20 of FIG. 1 is configured as below. That is, an anode side of the organic EL element ELD and a cathode side thereof are connected to Vcom and the drain terminal D of the driving TFT 21 , respectively.
  • a source terminal S of the driving TFT 21 is connected to the power supply wire Vp.
  • the switching TFT 22 has two conducting terminals and a control terminal (gate terminal G). One of the conducting terminals is connected to the drain terminal D of the driving TFT 21 , and the other conducting terminal is connected to the gate terminal G of the driving TFT 21 .
  • the control terminal is connected to the control wire Wi.
  • the capacitor C 1 has two electrodes, one of which is connected to the gate terminal G of the driving TFT 21 and the other of which is connected to the node K.
  • the switching TFT 23 has two conducting terminals and a control terminal (gate terminal G). One of the conducting terminals is connected to the node K, and the other conducting terminal is connected to the data line Sj. The control terminal is connected to the scanning line Gi. Furthermore, the node K is connected through the capacitor C 2 to the power supply wire Vref.
  • FIG. 3 is a timing chart illustrating operation of the pixel circuit Aij 20 thus configured.
  • the operation of the pixel circuit Aij 20 is controlled by the source driver circuit 1 and the gate driver circuit 2 in accordance with the aforementioned various signals supplied from the control circuit 3 .
  • the operation of the present pixel circuit Aij 20 is described below with reference to the timing chart of FIG. 3 .
  • FIG. 3 illustrates the timing of changes in potentials individually set for the scanning line Gi, the control wire Wi, the power supply wire Vp, and the data line Sj. Furthermore, each of the scanning line Gi+1 and the control wire Wi+1 is connected to the same data line Sj and corresponds to the pixel circuit A(i+1)j connected to the scanning line Gi+1 which is scanned next to the scanning line Gi.
  • Vp_H is set so that a voltage applied to the organic EL element ELD is reverse-biased or less than the light-emitting threshold voltage of the organic EL element ELD during a period t 2 described later. Since the amplitude of Vp_H is lower when Vp_H is set so that the voltage applied to the organic EL element ELD is less than the light-emitting threshold voltage of the organic EL element ELD during the period t 2 described later, the display device 10 can be made lower in power consumption.
  • the source terminal S (that terminal of the driving TFT 21 which is indicated by S in FIG. 1 ) serving as a source and the drain terminal D are here indicated as in FIG. 1 .
  • the drain terminal D is higher in potential than the source terminal S. For this reason, in some situations, the source terminal S and the drain terminal D switch positions with each other. The same applies to the embodiments below.
  • the potential of each of the scanning line Gi and the control wire Wi is set to High, so that the switching TFTs 22 and 23 become conductive. This causes the gate and drain terminals G and D of the driving TFT 21 to be short-circuited.
  • the potential of the data line Sj is a data voltage Vpc
  • the potential of the node K is the data voltage Vpc.
  • the data voltage Vpc is set so that the voltage between the gate and source terminals G and S of the driving TFT 21 is not less than the threshold voltage Vth of the driving TFT 21 (where the threshold voltage Vth is the voltage between the gate terminal G and the source terminal S).
  • the potential of the scanning line Gi is set to Low, so that the switching TFT 23 becomes non-conductive.
  • the driving TFT 21 a current flows to the power supply wire Vp. Therefore, the potential of the gate terminal G of the driving TFT 21 is gradually decreased.
  • the potential of the gate terminal G of the driving TFT 21 takes on a value (Vs+Vth, where Vs is the source voltage of the driving TFT 21 ) corresponding to the threshold voltage Vth of the driving TFT 21 , the driving TFT 21 becomes non-conductive. That is, this period is a period for compensation of variations in the threshold voltage Vth of the driving TFT 21 .
  • the driving TFT 21 can be put in a threshold state (where the difference in voltage between the gate terminal G and the source terminal S is the threshold voltage Vth) during the period t 2 , regardless of the threshold voltage Vth of the driving TFT 21 .
  • the gate potential of the driving TFT 21 at this time is stored in the capacitor C 1 .
  • the capacitor C 1 can keep a potential corresponding to the threshold voltage Vth of the driving TFT 21 .
  • the potential of the scanning line Gi is set to High, so that the switching TFT 23 becomes conductive.
  • the potential of the data line Sj is a data voltage Vdata
  • the potential of the node K is the data voltage Vdata.
  • the data voltage Vdata is adjusted so that a current flowing from the organic EL element ELD to the power supply wire Vp during a period t 4 described later takes on a desired current value.
  • FIG. 3 illustrates the data line Sj so that there exists two lines for supplying the data voltage Vdata and for supplying the data voltage Vpc, respectively. One or the other of the voltages is supplied to the data line Sj at a time.
  • the potential of the scanning line Gi is set to Low, so that the switching TFT 23 becomes non-conductive.
  • the potential of the power supply wire Vp is set to Vp_L, so that a desired current flows from the organic EL element ELD to the power supply wire Vp. This allows the organic EL element ELD to emit light at luminance corresponding to the designated display data.
  • the period from the beginning of the period t 4 until resetting of the power supply wire Vp to Vp_H is a period during which the organic EL element ELD emits light at the luminance corresponding to the designated display data.
  • the gate-source voltage of the driving TFT 21 can be set to the threshold voltage Vth (the variations in the threshold voltage Vth of the driving TFT 21 can be compensated for) by making the switching TFT 23 non-conductive. That is, the present pixel circuit makes it possible to compensate for the threshold voltage Vth of the driving TFT 21 during any period other than the select period (t 3 ) of the scanning line Gi.
  • the potential of the power supply wire Vp is not changed during the period for compensation of the variations in the threshold voltage Vth of the driving TFT 21 . Furthermore, the capacitor C 2 is not connected to the power supply wire Vp during the periods t 1 and t 4 . Therefore, even if the potential of the power supply wire Vp is changed, the consumption of power in the capacitor C 2 is zero. Consequently, with use of the pixel circuit Aij 20 of the present embodiment, the display device 10 can be made lower in power consumption.
  • the capacitor C 1 is connected between the node K and the gate terminal G of the driving TFT 21 .
  • the present invention is not necessarily limited to this.
  • a pixel circuit Aij 20 ′ in which a capacitor C 1 ′ is connected between a node L directly connected to the gate terminal G of the driving TFT 21 and the switching TFT 23 is possible.
  • the pixel circuit Aij 20 ′ of FIG. 4 is configured as below. That is, the anode side of the organic EL element ELD and the cathode side thereof are connected to Vcom and the drain terminal D of the driving TFT 21 , respectively.
  • the source and gate terminals S and G of the driving TFT 21 are connected to the power supply wire Vp and the node L, respectively.
  • the switching TFT 22 has two conducting terminals and a control terminal (gate terminal G). One of the conducting terminals is connected to the drain terminal D of the driving TFT 21 , and the other conducting terminal is connected to the gate terminal G of the driving TFT 21 .
  • the control terminal is connected to the control wire Wi.
  • the node L is connected through a capacitor C 1 ′ to one conducting terminal of the switching TFT 23 .
  • the other conducting terminal of the switching TFT 23 and a control terminal (gate terminal G) of the switching TFT 23 are connected to the data line Sj and the scanning line Gi, respectively.
  • the node L is connected through the capacitor C 2 to the power supply wire Vref.
  • the period for threshold correction depends on a period during which the potential of the scanning line Gi is High.
  • the connection of one end of the capacitor C 2 to the constant-potential power supply wire Vref brings about an effect of reducing power consumption in the same manner as in the pixel circuit Aij 20 .
  • Embodiments 2 and 3 described later have been obtained by remedying such a disadvantage of the pixel circuit Aij 20 ′ that the period for threshold correction depends on a period during which the potential of the scanning line Gi is High.
  • one terminal of the capacitor C 1 is connected only to the gate terminal G of the driving TFT 21 . Therefore, when the data voltage Vdata is written after the driving TFT 21 is corrected to be in the threshold state, the potential of the gate terminal G of the driving TFT 21 can be changed by the data voltage Vdata.
  • one terminal of the capacitor C 1 ′ is connected to the gate terminal G of the driving TFT 21 and the capacitor C 2 . Therefore, there is such a disadvantage that even when the data voltage Vdata is written, the potential of the gate terminal G cannot be changed by the data voltage Vdata and this causes an increase in the amplitude of the data voltage Vdata (i.e., the difference in the data voltage Vdata between the time for writing zero gradation and the time for writing maximum gradation).
  • FIG. 5 is a circuit diagram illustrating a configuration of a pixel circuit Aij 30 of the present embodiment.
  • the pixel circuit Aij 30 includes: a driving TFT 21 ; switching TFTs 22 , 23 , and 34 ; capacitors C 1 and C 2 ; and an organic EL element ELD.
  • the present embodiment is different from Embodiment 1 in that the switching TFT 34 is further provided in the pixel circuit Aij 30 . Therefore, the present embodiment omits descriptions similar to those given in Embodiment 1.
  • the switching TFT 34 is connected between (i) a node M provided between the aforementioned node K and the switching TFT 23 and (ii) the power supply wire Vref.
  • a gate terminal G of the switching TFT 34 is connected to the control wire Wi. Furthermore, the node K and the node M may coincide with each other.
  • the pixel circuit Aij 30 of FIG. 5 is configured as below. That is, the anode side of the organic EL element ELD and the cathode side thereof are connected to Vcom and the drain terminal D of the driving TFT 21 , respectively.
  • the source terminal S of the driving TFT 21 is connected to the power supply wire Vp.
  • the switching TFT 22 has two conducting terminals and a control terminal (gate terminal G). One of the conducting terminals is connected to the drain terminal D of the driving TFT 21 , and the other conducting terminal is connected to the gate terminal G of the driving TFT 21 .
  • the control terminal is connected to the control wire Wi.
  • the capacitor C 1 has two electrodes, one of which is connected to the gate terminal G of the driving TFT 21 and the other of which is connected through the node K to the node M.
  • the switching TFT 23 has two conducting terminals and a control terminal (gate terminal G). One of the conducting terminals is connected to the node M, and the other conducting terminal is connected to the data line Sj. The control terminal is connected to the scanning line Gi.
  • the node K is connected through the capacitor C 2 to the power supply wire Vref.
  • the switching TFT 34 has two conducting terminals and a control terminal (gate terminal G). One of the conducting terminals is connected to the power supply wire Vref, and the other conducting terminal is connected to the node M. The control terminal is connected to the control wire Wi.
  • FIG. 6 is a timing chart illustrating operation of the pixel circuit Aij 30 thus configured.
  • the operation of the pixel circuit Aij 30 is controlled by the source driver circuit 1 and the gate driver circuit 2 in accordance with the aforementioned various signals supplied from the control circuit 3 .
  • FIG. 6 illustrates the timing of changes in potentials individually set for the scanning line Gi, the control wire Wi, the power supply wire Vp, and the data line Sj. Furthermore, each of the scanning line Gi+1 and the control wire Wi+1 is connected to the same data line Sj and corresponds to the pixel circuit A(i+1)j connected to the scanning line Gi+1 which is scanned next to the scanning line Gi.
  • Vp_H the potential of the power supply wire Vp is increased to Vp_H.
  • the potential is set so that Vp_H>Vd, where Vd is the drain terminal D of the driving TFT 21 .
  • Vp_H is set so that a voltage applied to the organic EL element ELD is reverse-biased or less than the light-emitting threshold voltage of the organic EL element ELD during a period t 2 described later. Since the amplitude of Vp_H is lower when Vp_H is set so that the voltage applied to the organic EL element ELD is less than the light-emitting threshold voltage of the organic EL element ELD during the period t 2 described later, the display device can be made lower in power consumption.
  • the potential of the control wire Wi is set to High during the period T 2 , so that the switching TFTs 22 and 34 become conductive. This causes the gate and drain terminals G and D of the driving TFT 21 to be short-circuited.
  • the potential of the power supply wire Vref is a constant voltage Va
  • the potential of each of the nodes K and M is the constant voltage Va.
  • the constant voltage Va is set so that the voltage between the gate and source terminals G and S of the driving TFT 21 is not less than the threshold voltage Vth of the driving TFT 21 (where the threshold voltage Vth is the voltage between the gate terminal G and the source terminal S).
  • the driving TFT 21 can be put in a threshold state (where the difference in voltage between the gate terminal G and the source terminal S is the threshold voltage Vth) during the period t 2 , regardless of the threshold voltage Vth of the driving TFT 21 .
  • the gate potential of the driving TFT 21 at this time is stored in the capacitor C 1 .
  • the display device 10 can realize high quality.
  • the capacitor C 1 can keep a potential corresponding to the threshold voltage Vth of the driving TFT 21 .
  • the difference in potentials at both ends of the capacitor C 1 is Vs+Vth ⁇ Vref (where Vg is the gate voltage of the driving TFT 21 .)
  • the potential of the scanning line Gi is set to High, so that the switching TFT 23 becomes conductive.
  • the potential of the data line Sj is a data voltage Vdata
  • the potential of each of the nodes K and M is the data voltage Vdata.
  • the potential of the scanning line Gi is set to Low, so that the switching TFT 23 becomes non-conductive.
  • the potential of the power supply wire Vp is set to Vp_L, so that a desired current flows from the organic EL element ELD to the power supply wire Vp. This allows the organic EL element ELD to emit light at luminance corresponding to the designated display data.
  • the period from the beginning of the period t 4 until resetting of the power supply wire Vp to Vp_H is a period during which the organic EL element ELD emits light at the luminance corresponding to the designated display data.
  • the gate-source voltage of the driving TFT 21 can be set to the threshold voltage Vth (the variations in the threshold voltage Vth of the driving TFT 21 can be compensated for) by putting the switching TFT 23 in a non-conductive state (where the potential of the scanning line Gi is Low). That is, the present pixel circuit makes it possible to compensate for the threshold voltage of the driving TFT 21 during any period other than the select period (t 3 ) of the scanning line Gi.
  • the potential of the power supply wire Vp is not changed during the period for compensation of the variations in the threshold voltage Vth of the driving TFT 21 . Furthermore, the capacitor C 2 is not connected to the power supply wire Vp during the periods t 1 and t 4 . Therefore, even if the potential of the power supply wire Vp is changed, the consumption of power in the capacitor C 2 is zero. Consequently, with use of the pixel circuit Aij 30 of the present embodiment, the display device can be made lower in power consumption.
  • FIG. 7 is a circuit diagram illustrating a configuration of a pixel circuit Aij 40 of the present embodiment.
  • the pixel circuit Aij 40 includes: a driving TFT 21 ; switching TFTs 22 , 23 , and 34 ; capacitors C 1 ′ and C 2 ; and an organic EL element ELD. It should be noted that the driving TFT 21 and the switching TFTs 22 , 23 , and 34 are all n-channel TFTs.
  • the present embodiment is different from Embodiment 2 in that the capacitor C 2 is connected between the gate terminal G of the driving TFT 21 and the power supply wire Vref for supplying the constant voltage Va. That is, the present embodiment is different from Embodiment 2 in that the capacitor 2 is directly connected to the gate terminal G of the driving TFT 21 by being connected to the node L and that the capacitor C 1 ′ is provided between the node L and a node N provided between the node L and the switching TFT 23 . Therefore, the present embodiment omits descriptions similar to those given in Embodiments 1 and 2.
  • the pixel circuit Aij 40 of FIG. 7 is configured as below. That is, an anode side of the organic EL element ELD and a cathode side thereof are connected to Vcom and the drain terminal D of the driving TFT 21 , respectively.
  • the source and gate terminals S and G of the driving TFT 21 are connected to the power supply wire Vp and the node L (first node), respectively.
  • the switching TFT 22 has two conducting terminal and a control terminal (gate terminal G). One of the conducting terminals is connected to the drain terminal D of the driving TFT 21 , and the other conducting terminal is connected to the gate terminal G of the driving TFT 21 .
  • the control terminal is connected to the control wire Wi.
  • the node L is connected through the capacitor C 1 ′ to the node N (second node), which is connected to one conducting terminal of the switching TFT 23 .
  • the other conducting terminal of the switching TFT 23 and a control terminal (gate terminal G) of the switching TFT 23 are connected to the data line Sj and the scanning line Gi, respectively.
  • the node L is connected through the capacitor C 2 to the power supply wire Vref.
  • the switching TFT 34 has two conducting terminals and a control terminal (gate terminal G). One of the conducting terminals is connected to the power supply wire Vref, and the other conducting terminal is connected to the node N.
  • the control terminal is connected to the control wire Wi.
  • Operation of the pixel circuit Aij 40 thus configured is illustrated by the same timing chart as FIG. 6 . That is, the operation of the pixel circuit Aij 40 is controlled by the source driver circuit 1 and the gate driver circuit 2 in accordance with the aforementioned various signals supplied from the control circuit 3 .
  • the organic EL element ELD is used as an electrooptic element for the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 .
  • the electrooptic element is not limited to this, provided that it is a current-driven electrooptic element. Therefore, a semiconductor LED, a light-emitting portion of an FED, or the like can also be used as an electrooptic element that is provided in the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 .
  • the driving TFT 21 is used, which is a MOS transistor formed on an insulating substrate such as a glass substrate (referred to as a MOS transistor, including a silicon gate MOS structure).
  • the driving transistor is not limited to this, provided that it is a voltage-controlled element whose output current is controlled by a control voltage applied to its current control terminal and which has as a control voltage a threshold voltage Vth for determining the presence of an output current. Therefore, a general insulated gate field effect transistor, including a MOS transistor formed on a semiconductor substrate or the like, can be used.
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 and the display device 10 of the present embodiment are configured such that: the driving TFT 21 for determining, in accordance with a display signal, a current that is passed through a first path connecting the common anode Vcom with the power supply wire Vp and the organic EL element ELD are connected in series on the first path; the switching TFT 22 is provided between the gate and drain terminals G and D of the driving TFT 21 ; the capacitor C 1 and the switching TFT 23 are connected in series in this order between the gate terminal G of the driving TFT 21 and the data line Sj; and the power supply wire Vref for supplying a constant voltage is connected through the capacitor C 2 to the gate terminal G of the driving TFT 21 .
  • the threshold voltage Vth of the driving TFT 21 can be compensated for. This makes it possible, even in a state where the organic EL element ELD emits light, to perform a high-quality display by keeping the voltage of the gate terminal G of the driving TFT 21 at a desired value.
  • the power supply wire Vref for supplying the constant voltage is connected through the capacitor C 2 to the gate terminal G of the driving TFT 21 .
  • a first end of the capacitor C 2 is connected to the node K between the capacitor C 1 and the switching TFT 23 and a second end of the capacitor C 2 is connected to the power supply wire Vref, or a first end of the capacitor C 2 is connected to the node L between the gate terminal G of the driving TFT 21 and the capacitor C 1 and a second end of the capacitor C 2 is connected to the power supply wire Vref.
  • the power supply wire Vref to which the capacitor C 2 has been connected, supplies the constant voltage Va throughout all periods. Therefore, the capacitor C 2 consumes less power than in a case where the voltage is changed.
  • a pixel circuit Aij 20 that allows freely setting a period for compensation of the threshold voltage Vth of a driving TFT 21 and further reducing power consumption; and a display device 10 including such a pixel circuit Aij 20 .
  • the pixel circuit Aij 20 or Aij 20 ′ secures the potential of the node K by making the switching TFT 23 conductive.
  • such a method requires switching between supplying the data voltage Vpc to the data line Sj and supplying the data voltage Vdata to the data line Sj.
  • the node M between the capacitor C 1 and the switching TFT 23 and the power supply wire Vref for supplying the constant voltage Va are connected through the switching TFT 34 .
  • the need of making the switching TFT 23 conductive is eliminated by making the switching TFT 34 conductive in temporarily setting the voltage between the gate and source terminals G and S of the driving TFT 21 to not less than the threshold voltage Vth of the driving TFT 21 .
  • the capacitor C 2 is also connected to the power supply wire Vref, and the power supply wire Vref supplies the constant voltage Va throughout all periods. Therefore, the capacitor C 2 consumes less power than in a case where the voltage is changed.
  • the node N between the capacitor C 1 and the switching TFT 23 and the power supply wire Vref for supplying the constant voltage Va are connected through the switching TFT 34 . Accordingly, the need of making the switching TFT 23 conductive can be eliminated by making the switching TFT 34 conductive in temporarily setting the voltage between the gate and source terminals G and S of the driving TFT 21 to not less than the threshold voltage Vth of the driving TFT 21 .
  • a route on which the gate terminal G of the driving TFT 21 is connected through the capacitor C 1 and the switching TFT 34 to the power supply wire Vref and (ii) a route on which the gate terminal G of the driving TFT 21 is connected through the capacitor C 2 to the power supply wire Vref are provided in parallel with each other so as to extend from the gate terminal of the driving TFT 21 to the power supply wire Vref.
  • the capacitor C 2 has one end connected to the power supply wire Vref, and the power supply wire Vref supplies the constant voltage Va throughout all periods. This causes the capacitor C 2 to consume less power than in a case where the voltage is changed.
  • the voltage between the gate and source terminals G and S of the driving TFT 21 can be set to the threshold voltage Vth of the driving TFT 21 regardless of time for making the switching TFT 23 conductive. This makes it possible to obtain a high-quality image and to realize a pixel circuit Aij 40 that allows further reducing power consumption.
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 is preferably configured such that the power supply wire Vref is the common anode Vcom.
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 is preferably configured such that a voltage applied to the organic EL element ELD is reverse-biased during a period in which the voltage between the gate and source terminals G and S of the driving TFT 21 is set to the threshold voltage of the driving TFT 21 .
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 is preferably configured such that a voltage applied to the organic EL element ELD is set to less than a light-emitting threshold voltage of the organic EL element ELD during a period in which a voltage between the gate and source terminals G and S of the driving TFT 21 is set to a threshold voltage Vth of the driving TFT 21 .
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 is preferably configured such that the electrooptic element is an organic EL element.
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 is preferably configured such that at least the driving TFT 21 is constituted by an insulated gate field effect transistor.
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 is preferably configured such that each of the driving TFT 21 and the switching TFTs 22 , 23 , and 34 is constituted by a thin-film transistor.
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 may also be configured such that the thin-film transistor is made of amorphous silicon.
  • amorphous silicon when the pixel circuit is driven by using amorphous silicon, it takes time to set the voltage between the gate and source terminals G and S of the driving TFT 21 to the threshold voltage Vth of the driving TFT 21 , because amorphous silicon is lower, in mobility than low-temperature polycrystalline silicon or CG (Continuous Grain) silicon.
  • the time for setting the voltage between the gate and source terminals G and S of the driving TFT 21 to the threshold voltage Vth of the driving TFT 21 is made independent of time for writing the data voltage (time for pixel selection). Therefore, the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 realizes a high-quality display.
  • the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 may be configured such that each of the switching TFTs 22 , 23 , and 34 is constituted by an n-channel transistor.
  • the insulated gate field effect transistor to be disposed in the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 can be fabricated by the same process. This makes it possible to avoid such a complication in process as an increase in variety of masks and the like due to a mixture of different channel polarities. This brings about an effect of reducing the cost of a display device 10 . Moreover, sameness in channel polarity of transistors makes it possible to dispose two transistors in close proximity, so that a larger number of transistors can be disposed for the same area.
  • a display device 10 of the present embodiment including any one of the pixel circuits Aij 20 , Aij 20 ′, Aij 30 , and Aij 40 includes: the gate driver circuit 2 ; and the source driver circuit 1 , the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 being made writable by a scanning signal outputted from the gate driver circuit 2 to the scanning line Gi, a display signal corresponding to a driving current of the organic EL element ELD being written from the source driver circuit 1 through the data line Sj to the pixel circuit Aij 20 , Aij 20 ′, Aij 30 , or Aij 40 thus made writable.
  • the present invention is applicable to a pixel circuit and a display device, each of which allows freely setting a period for compensation of the threshold of a driving transistor and uses a current-driven display element low in power consumption.

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PCT/JP2007/068681 WO2008093451A1 (ja) 2007-01-31 2007-09-26 画素回路及び表示装置

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US20230140604A1 (en) * 2021-11-03 2023-05-04 Samsung Display. Co., Ltd Pixel and display device including the same
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US8349085B2 (en) 2013-01-08
JP2008192642A (ja) 2008-08-21
US20080179006A1 (en) 2008-07-31
TW200847267A (en) 2008-12-01
TWI449097B (zh) 2014-08-11
CN101236894A (zh) 2008-08-06
KR100961007B1 (ko) 2010-05-31
CN101236894B (zh) 2011-07-20

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