US20090096073A1 - Semiconductor device and lead frame used for the same - Google Patents

Semiconductor device and lead frame used for the same Download PDF

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Publication number
US20090096073A1
US20090096073A1 US12/252,584 US25258408A US2009096073A1 US 20090096073 A1 US20090096073 A1 US 20090096073A1 US 25258408 A US25258408 A US 25258408A US 2009096073 A1 US2009096073 A1 US 2009096073A1
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United States
Prior art keywords
leads
mounting region
lead portion
inner leads
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/252,584
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English (en)
Inventor
Yoshiaki Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GOTO, YOSHIAKI
Publication of US20090096073A1 publication Critical patent/US20090096073A1/en
Priority to US13/177,257 priority Critical patent/US8618643B2/en
Priority to US14/086,253 priority patent/US9177900B2/en
Priority to US14/875,287 priority patent/US9589870B2/en
Priority to US15/428,801 priority patent/US10199300B2/en
Priority to US16/236,824 priority patent/US10777479B2/en
Priority to US17/002,238 priority patent/US11688659B2/en
Abandoned legal-status Critical Current

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    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device and a lead frame used for the same.
  • a semiconductor package having plural semiconductor elements stacked and sealed in one package has already been put into practical use.
  • a lead frame is used as a circuit base material where semiconductor elements are mounted.
  • semiconductor package such as TSOP
  • plural semiconductor elements are sequentially stacked on the lead frame.
  • the electrode pads of the semiconductor elements are electrically connected with the inner leads of the lead frame through the metal wires.
  • plural semiconductor elements having a one-side pad structure are stacked in a step-like fashion to electrically connect the inner leads of the lead frame and the electrode pads of the semiconductor elements via metal wires (see JP-A 2001-298150(KOKAI), JP-A 2005-340766(KOKAI)).
  • the inner leads and the electrode pads are connected (wire bonded) on only a region along one side of the semiconductor element. Therefore, there is used a lead frame where the inner leads are at least partly routed via a mounting region of the semiconductor element.
  • Such a lead frame has plural semiconductor elements stacked on the element-mounting region where at least part of the inner leads are routed.
  • the gaps between the inner leads routed in the element-mounting region are open upward, so that a resin used for sealing enters easily into the gaps between the inner leads. Therefore, the gaps in the inner lead portion corresponding to the element-mounting region do not cause a problem.
  • the semiconductor package is demanded to increase the number of semiconductor elements. Therefore, it is being studied to mount the semiconductor elements on both the top and bottom surfaces of a lead frame. But, when the semiconductor elements are mounted on both the top and bottom surfaces of the lead frame, the gaps between the inner leads are closed by the top and bottom semiconductor elements to produce an elongate space. It is hard to fill the space with the sealing resin, and the elongate space remains in the semiconductor package. If such a semiconductor package is placed under a high-humidity environment, water content absorbed into the package enters the gaps between the inner leads, and a short circuit might be caused between the inner leads by the water content.
  • a semiconductor device includes: a circuit substrate provided with an element-mounting region, an outer lead portion having a plurality of outer leads, an inner lead portion having a plurality of inner leads which are at least partly routed in the element-mounting region, and an insulation resin filled into gaps between the inner leads located on at least part of the element-mounting region; a first element group, mounted on the element-mounting region in a first surface of the circuit substrate, including at least one first semiconductor element having electrode pads; a second element group, mounted on the element-mounting region on a second surface in the circuit substrate, including at least one second semiconductor element having electrode pads; first metal wires electrically connecting the electrode pads of the first semiconductor element and the inner leads of the circuit substrate; second metal wires electrically connecting the electrode pads of the second semiconductor element and the inner leads of the circuit substrate; and a resin-sealed portion sealing the first and second element groups together with the first and second metal wires.
  • a semiconductor device includes: a circuit substrate provided with an element-mounting region, an outer lead portion having a plurality of outer leads, an inner lead portion having a plurality of inner leads which are connected to the outer leads and at least partly routed in the element-mounting region, and an insulation resin filled into gaps between the inner leads located on the element-mounting region; a first element group, mounted on the element-mounting region in a first surface of the circuit substrate, including a plurality of first semiconductor elements having electrode pads; a second element group, mounted on the element-mounting region in a second surface of the circuit substrate, including a plurality of second semiconductor elements having electrode pads; first metal wires electrically connecting the electrode pads of the first semiconductor element and the inner leads of the circuit substrate; second metal wires electrically connecting the electrode pads of the second semiconductor element and the inner leads of the circuit substrate; and a resin-sealed portion sealing the first and second element groups together with the first and second metal wires.
  • a lead frame includes: an element-mounting region; an outer lead portion having a plurality of outer leads; an inner lead portion having a plurality of inner leads, at least part of the inner leads being routed in the element-mounting region; and an insulation resin filled into gaps between the inner leads located on at least part of the element-mounting region.
  • FIG. 1 is a plan view showing a lead frame according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing an example of a cross section taken along line A-A of FIG. 1 .
  • FIG. 3 is a diagram showing another example of the cross section taken along line A-A of FIG. 1 .
  • FIG. 4 is a diagram showing still another example of the cross section taken along line A-A of FIG. 1 .
  • FIG. 5 is a plan view of the lead frame shown in FIG. 4 .
  • FIG. 6A is a sectional view taken along line A-A of FIG. 5 , showing an arranging stage of an insulation resin sheet in the manufacturing process of the lead frame shown in FIG. 4 .
  • FIG. 6B is a sectional view taken along line B-B of FIG. 5 , showing an arranging stage of the insulation resin sheet in the manufacturing process of the lead frame shown in FIG. 4 .
  • FIG. 7A is a sectional view showing a stage that the insulation resin sheet shown in FIG. 6A is compression-bonded.
  • FIG. 7B is a sectional view showing a stage that the insulation resin sheet shown in FIG. 6B is compression-bonded.
  • FIG. 8 is a plan view showing a lead frame according to another embodiment of the present invention.
  • FIG. 9 is a plan view showing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 10 is a diagram showing a cross section taken along line A-A of FIG. 9 .
  • FIG. 11 is a diagram showing a cross section taken along line B-B of FIG. 9 .
  • FIG. 12 is a plan view showing a lead frame according to a second embodiment of the present invention.
  • FIG. 13 is a diagram showing a region where gaps between inner leads of the lead frame shown in FIG. 12 are filled with an insulation resin.
  • FIG. 14 is a plan view showing a state that a semiconductor element is mounted on the lead frame shown in FIG. 12 .
  • FIG. 15 is a sectional view showing a state that semiconductor elements are mounted on the lead frame shown in FIG. 12 .
  • FIG. 16 is a sectional view showing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 17 is a front view of the semiconductor device shown in FIG. 16 .
  • FIG. 18 is a plan view showing a lead frame according to a third embodiment of the present invention.
  • FIG. 19 is a plan view showing a state that a semiconductor element is mounted on the lead frame shown in FIG. 18 .
  • FIG. 20 is a sectional view showing a state that semiconductor elements are mounted on the lead frame shown in FIG. 18 .
  • FIG. 21 is a sectional view showing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 1 is a plan view showing a structure of the lead frame according to the first embodiment.
  • FIG. 2 through FIG. 4 are sectional views taken along line A-A of FIG. 1 .
  • the lead frame 1 shown in these drawings is provided with an inner lead portion 2 which becomes a connection portion to the semiconductor element mounted on it, and first and second outer lead portions 3 , 4 which become external connection terminals.
  • the first outer lead portion 3 has plural outer leads (first outer leads) 3 A.
  • the second outer lead portion 4 has plural outer leads (second outer leads) 4 A.
  • the inner lead portion 2 has plural first inner leads 2 A connected to the first outer leads 3 A, and plural second inner leads 2 B connected to the second outer leads 4 A.
  • the lead frame 1 has a first surface 1 a which is its top surface and a second surface 1 b which is its bottom surface.
  • a rectangular element-mounting region X is set on the first and second surfaces 1 a, 1 b of the lead frame 1 .
  • the lead frame 1 is a lead frame for dual-side mounting to mount semiconductor elements on both the top and bottom surfaces 1 a, 1 b. At least one semiconductor element is mounted on each of the first and second surfaces 1 a, 1 b of the lead frame 1 .
  • plural semiconductor elements having a one-side pad structure are stacked with pad arrangement sides directed in the same direction on the first surface 1 a of the lead frame 1 .
  • plural semiconductor elements having a one-side pad structure are stacked with pad arrangement sides directed to the same direction on the second surface 1 b of the lead frame 1 .
  • the pad arrangement sides of the semiconductor elements mounted on the first surface 1 a and the semiconductor elements mounted on the second surface 1 b are aligned in the same direction.
  • the first outer lead portion 3 is arranged along one short side of the element-mounting region X.
  • the second outer lead portion 4 is arranged along the other short side of the element-mounting region X.
  • the first outer lead portion 3 and the second outer lead portion 4 are arranged to oppose to each other with the element-mounting region X between them.
  • the first and second outer lead portions 3 , 4 are arranged such that the outer leads 3 A, 4 A are protruded from both the short sides of an element sealing portion of the semiconductor device (semiconductor package) configured by using the lead frame 1 .
  • FIG. 1 shows the lead frame 1 that the connection region Y of the inner lead portion 2 to the semiconductor elements is set on the side of the first outer lead portion 3 . Since the first inner leads 2 A are arranged on the side of the first outer lead portion 3 , their one ends can be connected to the first outer leads 3 A, while the other ends can be arranged in the connection region Y to the semiconductor elements.
  • the second inner leads 2 B have their one ends connected to the second outer leads 4 A, and the other ends arranged in the connection region Y on the side of the first outer lead portion 3 which is arranged to oppose to the second outer lead portion 4 with the element-mounting region X between them. Therefore, the second inner leads 2 B are extended from the one ends connected to the second outer leads 4 A to the other ends arranged in the connection region Y set on the side of the first outer lead portion 3 . The second inner leads 2 B are routed from the second outer lead portion 4 to the side of the first outer lead portion 3 via the element mounting region X.
  • the inner lead portion 2 having the first and second inner leads 2 A, 2 B enables to mount the semiconductor element having a single-short-side pad structure with the pad arrangement sides aligned on both the top and bottom surfaces 1 a , 1 b of the lead frame 1 .
  • the second inner leads 2 B are routed from the second outer lead portion 4 to the side of the first outer lead portion 3 , they are partially sandwiched between the semiconductor elements mounted on both the top and bottom surfaces 1 a, 1 b of the lead frame 1 . Gaps of the second inner leads 2 B cannot be filled sufficiently with a sealing resin only.
  • the gaps in a part of the second inner leads 2 B located on the element-mounting region X are filled with an insulation resin 5 as shown in FIG. 2 .
  • the insulation resin 5 is filled in the gaps of the inner leads 2 B independent of the resin configuring the resin-sealed portion of the semiconductor device (semiconductor package).
  • Either thermosetting resin or thermoplastic resin may be used for the insulation resin 5 .
  • a ratio of gaps within the element-mounting region X is kept constant as much as possible for uniform filling of the insulation resin 5 into the gaps of the second inner leads 2 B. Since portions 6 other than the second inner leads 2 B in the element-mounting region X function simply as an element supporting portion, they may have originally a simple plate shape. For uniformization of the ratio of gaps in the element-mounting region X, similar gaps as those of the second inner leads 2 B are also provided for the element supporting portions 6 located at both sides of the second inner lead 2 B. The insulation resin 5 is filled in the gaps of the second inner leads 2 B located on the element-mounting region X and the gaps of the element supporting portions 6 .
  • the insulation resin 5 is not limited to be filled in the gaps (including the gaps of the element supporting portions 6 ) of the second inner leads 2 B but may be provided in a layer shape on, for example, the top surface 1 a (or under surface 1 b ) of the lead frame 1 as shown in FIG. 3 .
  • An insulation resin sheet having the insulation resin 5 coated on a base film 7 may be used to provide a state that the base film 7 is arranged by compression-bonding on the top surface 1 a (or under surface 1 b ) of the lead frame 1 while the insulation resin 5 is filled in the gaps of the second inner leads 2 B as shown in FIG. 4 and FIG. 5 .
  • FIG. 6A and FIG. 7A are sectional views taken along line A-A of FIG. 5 .
  • FIG. 6B and FIG. 7B are sectional views taken along line B-B of FIG. 5 .
  • an insulation resin sheet 9 is prepared by forming an insulation resin layer 8 on the support film (base film) 7 having insulating properties by coating an insulation resin composition which becomes the insulation resin 5 .
  • the insulation resin sheet 9 has the same area as the element-mounting region X.
  • the insulation resin layer 8 is determined to have a thickness considering the volume of the gaps to be filled.
  • the insulation resin sheet 9 is bonded by thermocompression bonding to the element-mounting region X from the side of the top surface 1 a of the lead frame 1 , and the insulation resin layer 8 is filled in the gaps (including the gaps of the element supporting portion 6 ) of the second inner leads 2 B.
  • the insulation resin layer 8 is filled in the gaps of the element-mounting region X by provision of fluidity by heating and applying a pressurizing force via the support film 7 .
  • the lead frame 1 having the support film (insulation resin film) 7 of the insulation resin sheet 9 used to fill the insulation resin 5 applied to the element-mounting region X can be obtained. Since the support film 7 functions as a deformation preventing member for the second inner leads 2 B, it is used in a state pasted to the lead frame 1 . The support film 7 may be separated from the second inner leads 2 B, if necessary.
  • a lead fixing tape is used to prevent the inner leads from deforming.
  • the support film 7 can be used as a deformation preventing member for the second inner leads 2 B instead of a conventional lead fixing tape.
  • the wire bonding property to the second inner leads 2 B and the handling property of the lead frame 1 can be improved.
  • the support film 7 since the support film 7 has the same area as that of the element-mounting region X, it does not disturb the mounting of semiconductor elements different from the conventional lead fixing tape which partially covers the inner leads in the element-mounting region.
  • FIG. 5 through FIG. 7 show a state that the insulation resin sheet 9 is compression-bonded to the top surface 1 a of the lead frame 1 .
  • the insulation resin sheet 9 may be compression-bonded to the under surface 1 b of the lead frame 1 .
  • Irregularities might be formed between the under surface 1 b of the lead frame 1 and the insulation resin 5 depending on the distance of the insulation resin 5 entering the gaps of the second inner leads 2 B.
  • the irregularities can be smoothened by covering with an adhesive for adhering the semiconductor element to the under surface 1 b of the lead frame 1 . Therefore, there is no possibility of remaining gaps (spaces) after the adhesion of the semiconductor element.
  • the state that the insulation resin 5 is filled in the gaps between the second inner leads 2 B shown in FIG. 2 or the state that insulation resin 5 is filled in the gaps between the second inner leads 2 B and also partially formed in a layer shape on the top surface 1 a of the lead frame 1 shown in FIG. 3 can be realized by thermocompression bonding of the insulation resin film having only the insulation resin formed into the film to the element-mounting region X of the lead frame 1 . It is also possible to fill the insulation resin 5 into the gaps between the second inner leads 2 B by coating a liquid insulation resin on the element-mounting region X of the lead frame 1 . For example, an epoxy thermosetting resin is used as the liquid insulation resin. The liquid insulation resin is coated by a screen printing method or the like, and a pressurizing force is added, if necessary.
  • the insulation resin 5 for filling the gaps between the inner leads was applied to the lead frame 1 where only the second inner leads 2 B were routed via the element-mounting region X.
  • the shape of the lead frame to which the insulation resin is applied is not limited to what was described above.
  • the connection region to the semiconductor element by the inner lead portion is arranged along one long side of the element-mounting region.
  • both the first inner leads connected to the first outer leads and the second inner leads connected to the second outer leads are routed via the element-mounting region.
  • Such a lead frame is shown in FIG. 8 .
  • the first outer lead portion 3 has plural outer leads (first outer leads) 3 A.
  • the second outer lead portion 4 has plural outer leads (second outer leads) 4 A.
  • the inner lead portion 2 has the first inner leads 2 A connected to the first outer leads 3 A, and the second inner leads 2 B connected to the second outer leads 4 A.
  • the first outer lead portion 3 is arranged along one short side (first outline side) of the element-mounting region X.
  • the second outer lead portion 4 is arranged along the other short side (second outline side) of the element-mounting region X.
  • the first outer lead portion 3 and the second outer lead portion 4 are arranged to oppose through the element-mounting region X.
  • the first and second outer lead portions 3 , 4 are arranged such that the outer leads 3 A, 4 A are protruded from both short sides of the element sealing portion of the semiconductor device configured by using the lead frame 10 .
  • At least one semiconductor element having a single-long-side pad structure is mounted in the element-mounting region X by stacking with the pad arrangement side directed to the same direction on first and second surfaces 10 a, 10 b of the lead frame 10 .
  • the connection region Y of the inner lead portion 2 to the semiconductor element is determined on the side of one long side (third outline side) of the element-mounting region X.
  • the first and second inner leads 2 A, 2 B each have their one end portion connected to the first and second outer leads 3 A, 4 A with the other end portion arranged in the connection region Y which is set on the side of one long side (third outline side) of the element-mounting region X.
  • the first and second inner leads 2 A, 2 B each are routed from the connection portion with respect to the first and second outer leads 3 A, 4 A toward the connection region Y with respect to the semiconductor elements via the element-mounting region X.
  • the first inner leads 2 A are bent twice in the direction of, for example, 45 degrees such that the direction is changed by 90 degrees from the connection portion with respect to the first outer leads 3 A and routed toward the connection region Y with respect to the semiconductor element via the element-mounting region X.
  • the second inner leads 2 B are routed from the connection portion with respect to the second outer leads 4 A toward the connection region Y with respect to the semiconductor elements via the element-mounting region X.
  • the inner lead portion 2 having the first and second inner leads 2 A, 2 B can be applied to both the top and bottom surfaces 10 a , 10 b of the lead frame 10 to mount the semiconductor elements having a single-long-side pad structure by stacking with the pad arrangement sides aligned. But, since the inner leads 2 A, 2 B are routed from the outer lead portions 3 , 4 to the connection region Y with respect to the semiconductor element, they are partly sandwiched between the semiconductor elements mounted on both the top and bottom surfaces 10 a , 10 b of the lead frame 10 .
  • the insulation resin 5 is filled into the gaps of the first and second inner leads 2 A, 2 B at a portion located on the element-mounting region X.
  • a specific structure of the insulation resin 5 is as described in the above embodiment.
  • the insulation resin 5 filling the gaps between the inner leads is effective on the lead frames 1 , 10 where at least either the first inner leads 2 A connected to the first outer leads 3 A or the second inner leads 2 B connected to the second outer leads 4 A are routed via the element-mounting region X.
  • the first outer lead portion 3 and the second outer lead portion 4 are arranged to oppose to each other via the element-mounting region X.
  • the first inner leads 2 A are connected to the first outer leads 3 A which configure the first outer lead portion 3
  • the second inner leads 2 B are connected to the second outer leads 4 A which configure the second outer lead portion 4 .
  • the insulation resin 5 is filled into the gaps of the whole inner leads located on the element-mounting region X on the lead frames 1 , 10 described above.
  • the filling range of the insulation resin 5 is not limited to the above.
  • the insulation resin 5 may be filled into the gaps of the inner leads positioned on the area where the semiconductor elements mounted on the top surface and the semiconductor elements mounted on the under surface are overlapped.
  • the insulation resin 5 is charged to fill the gaps of the inner leads located on at least part of the element-mounting region in addition to the element-mounting region as a whole.
  • the insulation resin for filling the gaps of the inner leads can also be applied to the lead frame having the inner lead portion where at least part of the plural inner leads is routed in the element-mounting region X.
  • the insulation resin is effective when at least part of the inner leads is routed in the element-mounting region X. Therefore, the semiconductor element mounted on the lead frame is not limited to the single-short-side pad structure or the single-long-side pad structure.
  • the semiconductor elements having various types of pad structures such as a both-side pad structure, an L-shaped pad structure and the like can be mounted depending on a shape of the lead frame.
  • FIG. 9 is a plan view showing a semiconductor device (semiconductor package) according to the first embodiment.
  • FIG. 10 is a sectional view taken along line A-A of FIG. 9
  • FIG. 11 is a sectional view taken along line B-B of FIG. 9 .
  • a semiconductor device 11 shown in these drawings is provided with the lead frame 1 of the above-described embodiment as a circuit base material for mounting elements. The resin-sealed portion is omitted in FIG. 9 .
  • a first semiconductor element 13 A, a second semiconductor element 13 B, a third semiconductor element 13 C and a fourth semiconductor element 13 D which configure a first element group 12 are sequentially stacked on the first surface (top surface) 1 a of the lead frame 1 .
  • the first through fourth semiconductor elements 13 A to 13 D have the same rectangular shape and electrode pads 14 A to 14 D.
  • the first through fourth electrode pads 14 A to 14 D are arranged along one side, and specifically along one short side, of the outer shape of each of the first through fourth semiconductor elements 13 A to 13 D.
  • the first through fourth semiconductor elements 13 A to 13 D have a single-short-side pad structure.
  • the first semiconductor element 13 A has its electrode formation surface, on which the first electrode pads 14 A are formed, directed upward and is adhered onto the element-mounting region X on the top surface 1 a of the lead frame 1 via an adhesive layer (not shown). If the support film 7 is pasted to the top surface 1 a of the lead frame 1 , the first semiconductor element 13 A is adhered to the support film 7 via the adhesive layer.
  • a die attach film which is mainly composed of a general polyimide resin, or the like is used. The same adhesive layer is also used for the other semiconductor elements.
  • the first semiconductor element 13 A is arranged with a pad arrangement side (one short side) located on the side of the first outer lead portion 3 .
  • the second semiconductor element 13 B is adhered onto the first semiconductor element 13 A via an adhesive layer (unshown) with the electrode formation surface, on which the second electrode pads 14 B are formed, directed upward.
  • the third semiconductor element 13 C is adhered onto the second semiconductor element 13 B
  • the fourth semiconductor element 13 D is adhered onto the third semiconductor element 13 C via the adhesive layer (not shown), respectively.
  • the second through fourth semiconductor elements 13 B to 13 D are sequentially stacked in a step-like fashion onto the first semiconductor element 13 A with the pad arrangement sides directed to the same direction as the first semiconductor element 13 A and to expose the electrode pads 14 (the electrode pads 14 A of the first semiconductor element 13 A for the second semiconductor element 13 B) of the lower semiconductor elements 13 .
  • the first through fourth semiconductor elements 13 A to 13 D are stacked in a step-like fashion with their pad arrangement sides directed to the same direction, the long sides aligned and the short sides displaced in the direction of the long sides to expose the electrode pads 14 of the lower semiconductor elements 13 . Therefore, the electrode pads 14 A to 14 D of the first through fourth semiconductor elements 13 A to 13 D are located in a state exposed upward on the side of the first outer lead portion 3 .
  • the electrode pads 14 A to 14 D of the first through fourth semiconductor elements 13 A to 13 D are electrically connected to the first inner leads 2 A through first metal wires 15 .
  • first through fourth electrode pads 14 A to 14 D have the same electric properties and signal characteristics, they can be connected sequentially by the first metal wires 15 .
  • the fourth electrode pads 14 D and the third electrode pads 14 C are connected by the metal wires 15 .
  • the metal wires 15 are used to connect between the third electrode pads 14 C and the second electrode pads 14 B and between the second electrode pads 14 B and the first electrode pads 14 A.
  • the first electrode pads 14 A and the first inner leads 2 A are connected by the metal wires 15 . Wire bonding of the individual pads may be conducted independently or they may be connected sequentially by a single metallic wire.
  • a fifth semiconductor element 13 E, a sixth semiconductor element 13 F, a seventh semiconductor element 13 G and an eighth semiconductor element 13 H which configure a second element group 16 are sequentially stacked on the second surface (under surface) 1 b of the lead frame 1 .
  • the fifth through eighth semiconductor elements 13 E to 13 H have the same rectangular shape and respectively have electrode pads 14 E to 14 H.
  • the fifth through eighth electrode pads 14 E to 14 H are arranged along one sides, and specifically along one short sides, of the contours of the fifth through eighth semiconductor elements 13 E to 13 H.
  • the fifth through eighth semiconductor elements 13 E to 13 H have a single-short-side pad structure.
  • the fifth semiconductor element 13 E is adhered with the electrode formation surface, on which the fifth electrode pads 14 E are formed, directed downward to the element-mounting region X on the under surface 1 b of the lead frame 1 via an adhesive layer (unshown).
  • the fifth semiconductor element 13 E is arranged to position the pad arrangement side (one short side) on the side of the first outer lead portion 3 .
  • the fifth semiconductor element 13 E is arranged on the first semiconductor element 13 A with the lead frame 1 between them with the pad arrangement sides directed to the same direction and the electrode formation surfaces directed to the opposite directions (vertically opposite directions).
  • the sixth semiconductor element 13 F is adhered with the electrode formation surface, on which the sixth electrode pads 14 F are formed, directed downward to the electrode formation surface of the fifth semiconductor element 13 E via an adhesive layer (unshown).
  • the seventh semiconductor element 13 G is adhered to the electrode formation surface of the sixth semiconductor element 13 F
  • the eighth semiconductor element 13 H is adhered to the electrode formation surface of the seventh semiconductor element 13 G via an adhesive layer (unshown).
  • the sixth through eighth semiconductor elements 13 F to 13 H are sequentially stacked in a step-like fashion on the electrode formation surface of the fifth semiconductor element 13 E with the pad arrangement side directed to the same direction as the fifth semiconductor element 13 E and the electrode pads 14 of the lower semiconductor elements 13 (the upper semiconductor elements 13 with respect to the stacked direction) exposed.
  • the fifth through eighth semiconductor elements 13 E to 13 H are stacked in a step-like fashion with their pad arrangement sides directed to the same direction as the first element group 12 , their long sides aligned, and the short sides displaced in the direction of the long sides to expose the electrode pads 14 of the lower semiconductor elements 13 . Therefore, the electrode pads 14 E to 14 H of the fifth through eighth semiconductor elements 13 E to 13 H are located in a state exposed downward on the side of the first outer lead portion 3 .
  • the electrode pads 14 E to 14 H of the fifth through eighth semiconductor elements 13 E to 13 H are electrically connected to the second inner leads 2 B through second metal wires 17 .
  • the fifth through eighth electrode pads 14 E to 14 H have the same electric properties and signal characteristics, they can be connected sequentially by the second metal wires 17 .
  • the eighth electrode pads 14 H and the seventh electrode pads 14 G are connected by the metal wires 17 .
  • the metal wires 17 are used to connect between the seventh electrode pads 14 G and the sixth electrode pads 14 F and between the sixth electrode pads 14 F and the fifth electrode pads 14 E.
  • the fifth electrode pads 14 E and the second inner leads 2 B are connected by the metal wires 17 . Wire bonding of the individual pads may be conducted independently or they may be connected sequentially by a single metallic wire.
  • first through eighth semiconductor elements 13 A to 13 H include a semiconductor memory element such as a NAND-type flash memory.
  • the number of stacked semiconductor elements 13 configuring each of the element groups 12 , 16 is not limited to four (eight in total).
  • the semiconductor element 13 is not limited to the NAND-type flash memory only but may be a laminate of the NAND-type flash memory and its controller element.
  • the metal wires 15 , 17 are configured of general Au wires or Cu wires. To connect the metal wires 15 , 17 , it is preferable to apply reverse bonding capable of lowering the loop height.
  • the first element group 12 mounted on the top surface la of the lead frame 1 and the second element group 16 mounted on the under surface 1 b are sealed together with the inner lead portion 2 and the metal wires 15 , 17 by a resin-sealed portion 18 .
  • a general epoxy resin is used for the resin-sealed portion 18 .
  • the semiconductor device 11 having a dual-side stacking structure is configured.
  • the semiconductor device 11 of this embodiment is suitable for a semiconductor memory device which is provided with high capacity by stacking semiconductor memory elements into multiple layers.
  • the number of semiconductor elements mounted on both the top and bottom surfaces 1 a, 1 b of the lead frame 1 is adequately one or more, and for example one semiconductor element may be mounted on one surface.
  • the lead frame 1 is finally cut and constitutes a circuit substrate.
  • the circuit substrate includes the element-mounting region X, the inner lead portion 2 , the outer lead portions 3 , 4 , and the insulation resin 5 .
  • the insulation resin 5 is filled in the gaps between the second inner leads 2 B located on the element-mounting region X of the lead frame 1 before sealing with the resin. Therefore, the first and second element groups 12 , 16 each are mounted on the element-mounting region X of both the top and bottom surfaces 1 a, 1 b of the lead frame 1 , and even when the element-mounting region X of the lead frame 1 is interposed between the first semiconductor element 13 A and the fifth semiconductor element 13 E, the gaps between the second inner leads 2 B located on the element-mounting region X do not remain as a space in the package.
  • the semiconductor device 11 of this embodiment has the plural semiconductor elements 13 mounted on both the top and bottom surfaces of the lead frame 1 to increase the number of the mounted semiconductor elements 13 , and reliability can also be improved. In other words, the semiconductor device 11 having the number of the mounted semiconductor elements 13 increased and reliability improved can be provided.
  • the semiconductor device 11 Since the semiconductor device 11 has the semiconductor elements 13 stacked on both the top and bottom surfaces of the lead frame 1 , a package width can be made narrower in comparison with, for example, a semiconductor device which has the same number of semiconductor elements mounted by stacking on only one surface of the lead frame. When the latter semiconductor device has the number of semiconductor elements halved and folded for stacking in order to have the same package width, an intermediate spacer is required, and the package thickness increases as a result. In other words, the semiconductor device 11 can provide downsizing of the package size.
  • the plural semiconductor elements are stacked in a step-like fashion on the lead frame 1 , but the plural semiconductor elements may be stacked with the pad arrangement sides (one short sides in this embodiment) aligned.
  • the metal wire ends connected to the semiconductor elements can be buried into the adhesive layer to prevent the metal wires and the upper semiconductor elements from contacting mutually.
  • the semiconductor elements may also be mounted on only one surface of the lead frame 1 .
  • the semiconductor device 11 is not limited to the above-described structure that the semiconductor elements 13 having a single-short-side pad structure are mounted on both the surfaces of the lead frame 1 .
  • the lead frame 10 shown in FIG. 8 can be used to configure a semiconductor device which has semiconductor elements having a single-long-side pad structure mounted on both the surfaces.
  • the electrode pads of the semiconductor elements are electrically connected to the inner leads 2 A, 2 B arranged in the connection region Y through metal wires.
  • the semiconductor device of the embodiment is effective when the used lead frame has thereon at least either the first inner leads or the second inner leads routed via the element-mounting region X.
  • FIG. 12 and FIG. 13 are plan views showing the lead frame according to the second embodiment.
  • the lead frame 21 shown in these drawings is provided with an inner lead portion 22 which becomes a connection portion to semiconductor elements mounted on the lead frame 21 , and first and second outer lead portions 23 , 24 which become external connection terminals.
  • the first outer lead portion 23 has plural outer leads (first outer leads) 23 A.
  • the second outer lead portion 24 has plural outer leads (second outer leads) 24 A.
  • the inner lead portion 22 has first inner leads 25 A connected to the first outer leads 23 A, second inner leads 25 B connected to the second outer leads 24 A, and third inner leads 25 C which are electrically independent of the first and second outer leads 23 A, 24 A.
  • the lead frame 21 has a first surface (top surface) 21 a and a second surface (bottom surface) 21 b which is on a side opposite to it.
  • the lead frame 21 is a dual-side mounting lead frame having semiconductor elements mounted on both the top and bottom surfaces 21 a , 21 b.
  • a first element-mounting region X 1 is set on the first surface 21 a of the lead frame 21 .
  • a small first semiconductor element 26 is mounted on the first element-mounting region X 1 of the lead frame 21 .
  • the first element-mounting region X 1 has a shape corresponding to the first semiconductor element 26 .
  • the first semiconductor element 26 is adhered to the first element-mounting region X 1 in the first surface 21 a of the lead frame 21 via an adhesive layer with the electrode formation surface on which electrode pads 27 are formed directed upward.
  • the first semiconductor element 26 configures a first element group.
  • the electrode pads 27 of the first semiconductor element 26 are electrically connected to the inner leads 25 (first, second and third inner leads 25 A to 25 C) through first metal wires 28 .
  • a second element-mounting region X 2 is set on the second surface 21 b of the lead frame 21 .
  • a second semiconductor element 29 ( 29 A, 29 B) having a shape (outer shape) larger than the first semiconductor element 26 is mounted on the second element-mounting region X 2 of the lead frame 21 .
  • Two semiconductor elements 29 A, 29 B are mounted on the second surface 21 b of the lead frame 21 .
  • the two semiconductor elements 29 A, 29 B are stacked in a step-like fashion.
  • the second element-mounting region X 2 has a shape corresponding to the lower semiconductor element 29 A.
  • the second element-mounting region X 2 where the first element-mounting region X 1 is located inside is determined as an element-mounting region X. Apart of the first element-mounting region X 1 may be protruded from the second element-mounting region X 2 .
  • the two semiconductor elements 29 A, 29 B configure a second element group.
  • the lower semiconductor element 29 A is adhered to the second element-mounting region X 2 of the second surface 21 b of the lead frame 21 via an adhesive layer with the electrode formation surface, where electrode pads 30 A are formed, directed downward.
  • the semiconductor element 29 B is stacked in a step-like fashion on the semiconductor element 29 A such that the electrode pads 30 A of the semiconductor element 29 A are exposed.
  • the electrode pads 30 A, 30 B of the semiconductor elements 29 A, 29 B are electrically connected to the inner leads 25 through second metal wires 31 .
  • the second semiconductor elements 29 A, 29 B include a semiconductor memory element such as a NAND-type flash memory.
  • Specific examples of the first semiconductor element 26 include a controller element of a NAND-type flash memory.
  • the number of stacked semiconductor elements 29 in the second element group is not limited to two but may be three or more.
  • the semiconductor device provided with the semiconductor memory element (second semiconductor element 29 ) and its controller element (first semiconductor element 26 ) configures a semiconductor memory device.
  • the first outer lead portion 23 is arranged along one short side of the element-mounting region X.
  • the second outer lead portion 24 is arranged along the other short side of the element-mounting region X.
  • the first outer lead portion 23 and the second outer lead portion 24 are arranged to oppose to each other with the element-mounting region X between them.
  • the first and second outer lead portions 23 , 24 are arranged such that the individual outer leads 23 A, 24 A are protruded from both short sides of the element sealing portion of the semiconductor device (semiconductor package) configured by using the lead frame 21 .
  • the first, second and third inner leads 25 A, 25 B, 25 C each are routed within the element-mounting region X. Therefore, the inner leads 25 are partly interposed between the first semiconductor element 26 mounted on the first element-mounting region X 1 of the lead frame 21 and the second semiconductor element 29 A mounted on the second element-mounting region X 2 .
  • the gaps between the inner leads 25 located on a region (first element-mounting region X 1 ) where the first semiconductor element 26 and the second semiconductor element 29 A are overlapped cannot be filled sufficiently by the sealing resin only.
  • an insulation resin 32 is filled into the gaps between the inner leads 25 located on the first element-mounting region X 1 .
  • the insulation resin 32 is formed by a different process from the resin which configures the resin-sealed portion of the semiconductor device (semiconductor package).
  • the insulation resin 32 is previously filled into the gaps between the inner leads 25 before the resin-sealed portion is formed.
  • a constituting material and a forming process of the insulation resin 32 are same as those described in the first embodiment.
  • the support film of the insulation resin sheet for filling the insulation resin may be pasted to the lead frame 21 .
  • the insulation resin 32 is filled in the gaps in a portion located on at least the first element-mounting region X 1 of the inner leads 25 .
  • a filling region Z 1 of the insulation resin 32 is set to include the first element-mounting region X 1 .
  • the insulation resin 32 is filled into the gaps between the inner leads 25 located on the filling region Z 1 .
  • the insulation resin 32 has functions to prevent the inner leads 25 from falling and deforming. Therefore, the filling region of the insulation resin 32 can be set in addition to the filling region Z 1 including the first element-mounting region X 1 .
  • the lead frame 21 has second, third, fourth and fifth filling regions Z 2 , Z 3 , Z 4 , Z 5 other than the first filling region Z 1 .
  • the insulation resin 32 is filled into the gaps between the inner leads 25 located on the individual regions Z 2 to Z 5 .
  • the wire bonding property to the inner leads 25 and the handling property of the lead frame 21 are improved. If there is a possibility of causing falling or the like of the inner leads 25 before the insulation resin 32 is filled, it is preferable that the inner leads of such a portion are mutually connected, and the connected portion is cut after the insulation resin 32 is filled to provide the function of the inner leads 25 .
  • the first and second semiconductor elements 26 , 29 mounted on the lead frame 21 are sealed together with the inner lead portion 22 and the metal wires 28 , 31 by the resin-sealed portion 33 to configure a semiconductor device 34 having a dual-side mounting structure as shown in FIG. 16 and FIG. 17 .
  • the lead frame 21 is finally cut and constitutes a circuit substrate.
  • the semiconductor device 34 of the second embodiment has the insulation resin 32 previously filled into the gaps between the inner leads 25 . Therefore, even when the element-mounting region X 1 of the lead frame 21 is interposed between the first semiconductor element 26 and the second semiconductor element 29 A, the gaps between the inner leads 25 located on the element-mounting region X 1 do not remain as a space in the package.
  • the insulation resin 32 is filled into the gaps between the inner leads 25 located on the element-mounting region X 1 , occurrence of a short circuit due to entrance of the water content, which is absorbed into the semiconductor device 34 , into the gaps between the inner leads 25 can be suppressed. Therefore, reliability can be improved by the semiconductor device 34 of this embodiment when the semiconductor elements 25 , 29 are mounted on both the top and bottom surfaces of the lead frame 21 . Besides, the semiconductor device 34 is highly sophisticated and its cost can be reduced by mounting the semiconductor elements 25 , 29 on both the top and bottom surfaces of the lead frame 21 .
  • FIG. 18 is a plan view showing the lead frame according to the third embodiment.
  • a lead frame 41 shown in FIG. 18 is provided with an inner lead portion 42 which becomes a connection portion to the semiconductor element mounted on it, and first and second outer lead portions 43 , 44 which become external connection terminals.
  • the first outer lead portion 43 has plural outer leads (first outer leads) 43 A.
  • the second outer lead portion 44 has plural outer leads (second outer leads) 44 A.
  • the inner lead portion 42 has first inner leads 45 A connected to the first outer leads 43 A and second inner leads 45 B connected to the second outer leads 44 A.
  • the lead frame 41 has a first surface (top surface) 41 a and a second surface (bottom surface) 41 b which is opposite to it.
  • the lead frame 41 is a dual-side mounting lead frame which has semiconductor elements mounted on both the top and bottom surfaces 41 a , 41 b. Similar to the second embodiment, a first element-mounting region X 1 is set on the first surface 41 a of the lead frame 41 , and a second element-mounting region X 2 is set on the second surface 41 b.
  • the second element-mounting region X 2 where the first element-mounting region X 1 is located inside is determined as an element-mounting region X.
  • a first semiconductor element 26 is mounted on the first element-mounting region X 1 of the lead frame 41
  • a second semiconductor element 29 ( 29 A, 29 B) having a shape (outer shape) larger than the first semiconductor element 26 is mounted on the second element-mounting region X 2
  • Two semiconductor elements 29 A, 29 B are stacked in a step-like fashion on the second element-mounting region X 2 .
  • the first semiconductor element 26 configures a first element group
  • the second semiconductor elements 29 A, 29 B configure a second element group.
  • the mounting structure and connection structure of the first and second semiconductor elements 26 , 29 with respect to the lead frame 41 are similar to those in the second embodiment.
  • the first outer lead portion 43 is arranged along one short side of the element-mounting region X.
  • the second outer lead portion 44 is arranged along the other short side of the element-mounting region X.
  • the first outer lead portion 43 and the second outer lead portion 44 are arranged to oppose to each other with the element-mounting region X between them.
  • the first and second outer lead portions 43 , 44 are arranged such that the outer leads 43 A, 44 A are protruded from both short sides of an element sealing portion of the semiconductor device (semiconductor package) configured by using the lead frame 41 .
  • the first and second inner leads 45 A, 45 B each are routed within the element-mounting region X. Therefore, inner leads 45 are partly (specifically, parts of the first inner leads 45 A) interposed between the first semiconductor element 26 mounted on the first element-mounting region X 1 and the second semiconductor element 29 A mounted on the second element-mounting region X 2 .
  • the gaps between the inner leads 45 located on the region (first element-mounting region X 1 ) where the first semiconductor element 26 and the second semiconductor element 29 A are overlapped cannot be filled sufficiently with the sealing resin only.
  • an insulation resin 46 is previously filled into the gaps between the inner leads 25 located on the first element-mounting region X 1 .
  • the adhesive resin (insulation resin) of the first semiconductor element 26 is used to fill the gaps between the inner leads 45 with the insulation resin 46 .
  • the insulating adhesive paste (insulation resin paste having the adhesion properties) is coated onto the first element-mounting region X 1 of the lead frame 41 .
  • the first semiconductor element 26 is adhered by pressing onto the adhesive paste-coated layer.
  • the adhesive paste enters the gaps between the inner leads 25 .
  • the gaps between the inner leads 25 are filled with the insulation resin 46 .
  • the adhesive paste which functions as the adhesive layer for the first semiconductor element 26 and as the insulation resin 46 is coated considering a filling amount into the gaps between the inner leads 45 . If the coating amount of the adhesive paste is insufficient, the first semiconductor element 26 might be contacted to the lead frame 41 .
  • An insulating layer 47 is formed on the back surface (adhered surface) of the first semiconductor element 26 in order to prevent the contact to the lead frame 41 if the coating amount of the adhesive paste is insufficient.
  • the insulating layer 47 is formed by pasting an insulating film to the back surface of the first semiconductor element 26 .
  • the first and second semiconductor elements 26 , 29 mounted on the lead frame 41 are sealed together with the inner lead portion 42 and the metal wires 28 , 31 by the resin-sealed portion 33 to configure a semiconductor device 48 having a dual-side mounting structure.
  • the lead frame 41 is finally cut and constitutes a circuit substrate. Sealing by the resin is performed after the semiconductor device 48 has the insulation resin 46 filled into the gaps between the inner leads 45 . Therefore, even when the element-mounting region X 1 of the lead frame 41 is interposed between the first semiconductor element 26 and the second semiconductor element 29 A, the gaps between the inner leads 45 located on the element-mounting region X 1 do not remain as a space within the package.
  • the insulation resin 46 is filled into the gaps between the inner leads 45 located on the element-mounting region X 1 , occurrence of a short circuit due to entrance of the water content, which is absorbed into the semiconductor device 48 , into the gaps between the inner leads 45 can be suppressed. Therefore, reliability can be improved by the semiconductor device 48 of this embodiment even when the semiconductor elements 26 , 29 are mounted on both the top and bottom surfaces of the lead frame 41 . Besides, the semiconductor device 48 is highly sophisticated and its cost can be reduced by mounting the semiconductor elements 26 , 29 on both the top and bottom surfaces of the lead frame 41 .
  • the present invention is not limited to the above-described embodiments, but can be applied to a lead frame which has semiconductor elements mounted on its both front and rear surfaces and a semiconductor device having a dual-side mounting structure using it. Such a lead frame and a semiconductor device are also included in the present invention.
  • the embodiments of the present invention can be expanded or modified within the scope of technical idea of the invention, and the expanded and modified embodiments are also included in the technical scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
US12/252,584 2007-10-16 2008-10-16 Semiconductor device and lead frame used for the same Abandoned US20090096073A1 (en)

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US13/177,257 US8618643B2 (en) 2007-10-16 2011-07-06 Semiconductor device and lead frame used for the same
US14/086,253 US9177900B2 (en) 2007-10-16 2013-11-21 Semiconductor device and lead frame used for the same
US14/875,287 US9589870B2 (en) 2007-10-16 2015-10-05 Semiconductor device and lead frame used for the same
US15/428,801 US10199300B2 (en) 2007-10-16 2017-02-09 Semiconductor package including a device and lead frame used for the same
US16/236,824 US10777479B2 (en) 2007-10-16 2018-12-31 Semiconductor memory device
US17/002,238 US11688659B2 (en) 2007-10-16 2020-08-25 Method for manufacturing a semiconductor device having a semiconductor element mounted on a lead frame

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US13/177,257 Active US8618643B2 (en) 2007-10-16 2011-07-06 Semiconductor device and lead frame used for the same
US14/086,253 Active 2028-10-17 US9177900B2 (en) 2007-10-16 2013-11-21 Semiconductor device and lead frame used for the same
US14/875,287 Active US9589870B2 (en) 2007-10-16 2015-10-05 Semiconductor device and lead frame used for the same
US15/428,801 Active US10199300B2 (en) 2007-10-16 2017-02-09 Semiconductor package including a device and lead frame used for the same
US16/236,824 Active US10777479B2 (en) 2007-10-16 2018-12-31 Semiconductor memory device
US17/002,238 Active 2029-05-15 US11688659B2 (en) 2007-10-16 2020-08-25 Method for manufacturing a semiconductor device having a semiconductor element mounted on a lead frame

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US14/875,287 Active US9589870B2 (en) 2007-10-16 2015-10-05 Semiconductor device and lead frame used for the same
US15/428,801 Active US10199300B2 (en) 2007-10-16 2017-02-09 Semiconductor package including a device and lead frame used for the same
US16/236,824 Active US10777479B2 (en) 2007-10-16 2018-12-31 Semiconductor memory device
US17/002,238 Active 2029-05-15 US11688659B2 (en) 2007-10-16 2020-08-25 Method for manufacturing a semiconductor device having a semiconductor element mounted on a lead frame

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US20090166829A1 (en) * 2007-12-27 2009-07-02 Kabushiki Kaisha Toshiba Semiconductor memory device
US8004071B2 (en) * 2007-12-27 2011-08-23 Kabushiki Kaisha Toshiba Semiconductor memory device
US8395268B2 (en) 2007-12-27 2013-03-12 Kabushiki Kaisha Toshiba Semiconductor memory device
US20100164080A1 (en) * 2008-12-26 2010-07-01 Kabushiki Kaisha Toshiba Semiconductor device
US8143707B2 (en) 2008-12-26 2012-03-27 Kabushiki Kaisha Toshiba Semiconductor device
US8912636B2 (en) 2009-02-05 2014-12-16 Kabushiki Kaisha Toshiba Semiconductor device

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US10777479B2 (en) 2020-09-15
JP4970610B2 (ja) 2012-07-11
JP4970401B2 (ja) 2012-07-04
JP2011181967A (ja) 2011-09-15
US11688659B2 (en) 2023-06-27
US8618643B2 (en) 2013-12-31
US9589870B2 (en) 2017-03-07
US20170154832A1 (en) 2017-06-01
US20200388547A1 (en) 2020-12-10
US10199300B2 (en) 2019-02-05
JP2009117819A (ja) 2009-05-28
US20140077348A1 (en) 2014-03-20
US9177900B2 (en) 2015-11-03
US20190139849A1 (en) 2019-05-09
US20160027720A1 (en) 2016-01-28

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